1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2018-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 #ifndef HL_BOOT_IF_H
9 #define HL_BOOT_IF_H
10 
11 #define LKD_HARD_RESET_MAGIC		0xED7BD694 /* deprecated - do not use */
12 #define HL_POWER9_HOST_MAGIC		0x1DA30009
13 
14 #define BOOT_FIT_SRAM_OFFSET		0x200000
15 
16 #define VERSION_MAX_LEN			128
17 
18 enum cpu_boot_err {
19 	CPU_BOOT_ERR_DRAM_INIT_FAIL = 0,
20 	CPU_BOOT_ERR_FIT_CORRUPTED = 1,
21 	CPU_BOOT_ERR_TS_INIT_FAIL = 2,
22 	CPU_BOOT_ERR_DRAM_SKIPPED = 3,
23 	CPU_BOOT_ERR_BMC_WAIT_SKIPPED = 4,
24 	CPU_BOOT_ERR_NIC_DATA_NOT_RDY = 5,
25 	CPU_BOOT_ERR_NIC_FW_FAIL = 6,
26 	CPU_BOOT_ERR_SECURITY_NOT_RDY = 7,
27 	CPU_BOOT_ERR_SECURITY_FAIL = 8,
28 	CPU_BOOT_ERR_EFUSE_FAIL = 9,
29 	CPU_BOOT_ERR_PRI_IMG_VER_FAIL = 10,
30 	CPU_BOOT_ERR_SEC_IMG_VER_FAIL = 11,
31 	CPU_BOOT_ERR_PLL_FAIL = 12,
32 	CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL = 13,
33 	CPU_BOOT_ERR_BOOT_FW_CRIT_ERR = 18,
34 	CPU_BOOT_ERR_BINNING_FAIL = 19,
35 	CPU_BOOT_ERR_TPM_FAIL = 20,
36 	CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL = 21,
37 	CPU_BOOT_ERR_EEPROM_FAIL = 22,
38 	CPU_BOOT_ERR_ENABLED = 31,
39 	CPU_BOOT_ERR_SCND_EN = 63,
40 	CPU_BOOT_ERR_LAST = 64 /* we have 2 registers of 32 bits */
41 };
42 
43 /*
44  * Mask for fatal failures
45  * This mask contains all possible fatal failures, and a dynamic code
46  * will clear the non-relevant ones.
47  */
48 #define CPU_BOOT_ERR_FATAL_MASK					\
49 		((1 << CPU_BOOT_ERR_DRAM_INIT_FAIL) |		\
50 		 (1 << CPU_BOOT_ERR_PLL_FAIL) |			\
51 		 (1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL) |	\
52 		 (1 << CPU_BOOT_ERR_BINNING_FAIL) |		\
53 		 (1 << CPU_BOOT_ERR_DRAM_SKIPPED) |		\
54 		 (1 << CPU_BOOT_ERR_EEPROM_FAIL))
55 
56 /*
57  * CPU error bits in BOOT_ERROR registers
58  *
59  * CPU_BOOT_ERR0_DRAM_INIT_FAIL		DRAM initialization failed.
60  *					DRAM is not reliable to use.
61  *
62  * CPU_BOOT_ERR0_FIT_CORRUPTED		FIT data integrity verification of the
63  *					image provided by the host has failed.
64  *
65  * CPU_BOOT_ERR0_TS_INIT_FAIL		Thermal Sensor initialization failed.
66  *					Boot continues as usual, but keep in
67  *					mind this is a warning.
68  *
69  * CPU_BOOT_ERR0_DRAM_SKIPPED		DRAM initialization has been skipped.
70  *					Skipping DRAM initialization has been
71  *					requested (e.g. strap, command, etc.)
72  *					and FW skipped the DRAM initialization.
73  *					Host can initialize the DRAM.
74  *
75  * CPU_BOOT_ERR0_BMC_WAIT_SKIPPED	Waiting for BMC data will be skipped.
76  *					Meaning the BMC data might not be
77  *					available until reset.
78  *
79  * CPU_BOOT_ERR0_NIC_DATA_NOT_RDY	NIC data from BMC is not ready.
80  *					BMC has not provided the NIC data yet.
81  *					Once provided this bit will be cleared.
82  *
83  * CPU_BOOT_ERR0_NIC_FW_FAIL		NIC FW loading failed.
84  *					The NIC FW loading and initialization
85  *					failed. This means NICs are not usable.
86  *
87  * CPU_BOOT_ERR0_SECURITY_NOT_RDY	Chip security initialization has been
88  *					started, but is not ready yet - chip
89  *					cannot be accessed.
90  *
91  * CPU_BOOT_ERR0_SECURITY_FAIL		Security related tasks have failed.
92  *					The tasks are security init (root of
93  *					trust), boot authentication (chain of
94  *					trust), data packets authentication.
95  *
96  * CPU_BOOT_ERR0_EFUSE_FAIL		Reading from eFuse failed.
97  *					The PCI device ID might be wrong.
98  *
99  * CPU_BOOT_ERR0_PRI_IMG_VER_FAIL	Verification of primary image failed.
100  *					It mean that ppboot checksum
101  *					verification for the preboot primary
102  *					image has failed to match expected
103  *					checksum. Trying to program image again
104  *					might solve this.
105  *
106  * CPU_BOOT_ERR0_SEC_IMG_VER_FAIL	Verification of secondary image failed.
107  *					It mean that ppboot checksum
108  *					verification for the preboot secondary
109  *					image has failed to match expected
110  *					checksum. Trying to program image again
111  *					might solve this.
112  *
113  * CPU_BOOT_ERR0_PLL_FAIL		PLL settings failed, meaning that one
114  *					of the PLLs remains in REF_CLK
115  *
116  * CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL	Device is unusable and customer support
117  *					should be contacted.
118  *
119  * CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR	Critical error was detected during
120  *					the execution of ppboot or preboot.
121  *					for example: stack overflow.
122  *
123  * CPU_BOOT_ERR0_BINNING_FAIL		Binning settings failed, meaning
124  *					malfunctioning components might still be
125  *					in use.
126  *
127  * CPU_BOOT_ERR0_TPM_FAIL		TPM verification flow failed.
128  *
129  * CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL	Failed to set threshold for tmperature
130  *					sensor.
131  *
132  * CPU_BOOT_ERR_EEPROM_FAIL		Failed reading EEPROM data. Defaults
133  *					are used.
134  *
135  * CPU_BOOT_ERR0_ENABLED		Error registers enabled.
136  *					This is a main indication that the
137  *					running FW populates the error
138  *					registers. Meaning the error bits are
139  *					not garbage, but actual error statuses.
140  */
141 #define CPU_BOOT_ERR0_DRAM_INIT_FAIL		(1 << CPU_BOOT_ERR_DRAM_INIT_FAIL)
142 #define CPU_BOOT_ERR0_FIT_CORRUPTED		(1 << CPU_BOOT_ERR_FIT_CORRUPTED)
143 #define CPU_BOOT_ERR0_TS_INIT_FAIL		(1 << CPU_BOOT_ERR_TS_INIT_FAIL)
144 #define CPU_BOOT_ERR0_DRAM_SKIPPED		(1 << CPU_BOOT_ERR_DRAM_SKIPPED)
145 #define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED		(1 << CPU_BOOT_ERR_BMC_WAIT_SKIPPED)
146 #define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY		(1 << CPU_BOOT_ERR_NIC_DATA_NOT_RDY)
147 #define CPU_BOOT_ERR0_NIC_FW_FAIL		(1 << CPU_BOOT_ERR_NIC_FW_FAIL)
148 #define CPU_BOOT_ERR0_SECURITY_NOT_RDY		(1 << CPU_BOOT_ERR_SECURITY_NOT_RDY)
149 #define CPU_BOOT_ERR0_SECURITY_FAIL		(1 << CPU_BOOT_ERR_SECURITY_FAIL)
150 #define CPU_BOOT_ERR0_EFUSE_FAIL		(1 << CPU_BOOT_ERR_EFUSE_FAIL)
151 #define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL		(1 << CPU_BOOT_ERR_PRI_IMG_VER_FAIL)
152 #define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL		(1 << CPU_BOOT_ERR_SEC_IMG_VER_FAIL)
153 #define CPU_BOOT_ERR0_PLL_FAIL			(1 << CPU_BOOT_ERR_PLL_FAIL)
154 #define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL	(1 << CPU_BOOT_ERR_DEVICE_UNUSABLE_FAIL)
155 #define CPU_BOOT_ERR0_BOOT_FW_CRIT_ERR		(1 << CPU_BOOT_ERR_BOOT_FW_CRIT_ERR)
156 #define CPU_BOOT_ERR0_BINNING_FAIL		(1 << CPU_BOOT_ERR_BINNING_FAIL)
157 #define CPU_BOOT_ERR0_TPM_FAIL			(1 << CPU_BOOT_ERR_TPM_FAIL)
158 #define CPU_BOOT_ERR0_TMP_THRESH_INIT_FAIL	(1 << CPU_BOOT_ERR_TMP_THRESH_INIT_FAIL)
159 #define CPU_BOOT_ERR0_EEPROM_FAIL		(1 << CPU_BOOT_ERR_EEPROM_FAIL)
160 #define CPU_BOOT_ERR0_ENABLED			(1 << CPU_BOOT_ERR_ENABLED)
161 #define CPU_BOOT_ERR1_ENABLED			(1 << CPU_BOOT_ERR_ENABLED)
162 
163 enum cpu_boot_dev_sts {
164 	CPU_BOOT_DEV_STS_SECURITY_EN = 0,
165 	CPU_BOOT_DEV_STS_DEBUG_EN = 1,
166 	CPU_BOOT_DEV_STS_WATCHDOG_EN = 2,
167 	CPU_BOOT_DEV_STS_DRAM_INIT_EN = 3,
168 	CPU_BOOT_DEV_STS_BMC_WAIT_EN = 4,
169 	CPU_BOOT_DEV_STS_E2E_CRED_EN = 5,
170 	CPU_BOOT_DEV_STS_HBM_CRED_EN = 6,
171 	CPU_BOOT_DEV_STS_RL_EN = 7,
172 	CPU_BOOT_DEV_STS_SRAM_SCR_EN = 8,
173 	CPU_BOOT_DEV_STS_DRAM_SCR_EN = 9,
174 	CPU_BOOT_DEV_STS_FW_HARD_RST_EN = 10,
175 	CPU_BOOT_DEV_STS_PLL_INFO_EN = 11,
176 	CPU_BOOT_DEV_STS_SP_SRAM_EN = 12,
177 	CPU_BOOT_DEV_STS_CLK_GATE_EN = 13,
178 	CPU_BOOT_DEV_STS_HBM_ECC_EN = 14,
179 	CPU_BOOT_DEV_STS_PKT_PI_ACK_EN = 15,
180 	CPU_BOOT_DEV_STS_FW_LD_COM_EN = 16,
181 	CPU_BOOT_DEV_STS_FW_IATU_CONF_EN = 17,
182 	CPU_BOOT_DEV_STS_FW_NIC_MAC_EN = 18,
183 	CPU_BOOT_DEV_STS_DYN_PLL_EN = 19,
184 	CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN = 20,
185 	CPU_BOOT_DEV_STS_EQ_INDEX_EN = 21,
186 	CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN = 22,
187 	CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN = 23,
188 	CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN = 24,
189 	CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN = 25,
190 	CPU_BOOT_DEV_STS_MAP_HWMON_EN = 26,
191 	CPU_BOOT_DEV_STS_ENABLED = 31,
192 	CPU_BOOT_DEV_STS_SCND_EN = 63,
193 	CPU_BOOT_DEV_STS_LAST = 64 /* we have 2 registers of 32 bits */
194 };
195 
196 /*
197  * BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
198  *
199  * CPU_BOOT_DEV_STS0_SECURITY_EN	Security is Enabled.
200  *					This is an indication for security
201  *					enabled in FW, which means that
202  *					all conditions for security are met:
203  *					device is indicated as security enabled,
204  *					registers are protected, and device
205  *					uses keys for image verification.
206  *					Initialized in: preboot
207  *
208  * CPU_BOOT_DEV_STS0_DEBUG_EN		Debug is enabled.
209  *					Enabled when JTAG or DEBUG is enabled
210  *					in FW.
211  *					Initialized in: preboot
212  *
213  * CPU_BOOT_DEV_STS0_WATCHDOG_EN	Watchdog is enabled.
214  *					Watchdog is enabled in FW.
215  *					Initialized in: preboot
216  *
217  * CPU_BOOT_DEV_STS0_DRAM_INIT_EN	DRAM initialization is enabled.
218  *					DRAM initialization has been done in FW.
219  *					Initialized in: u-boot
220  *
221  * CPU_BOOT_DEV_STS0_BMC_WAIT_EN	Waiting for BMC data enabled.
222  *					If set, it means that during boot,
223  *					FW waited for BMC data.
224  *					Initialized in: u-boot
225  *
226  * CPU_BOOT_DEV_STS0_E2E_CRED_EN	E2E credits initialized.
227  *					FW initialized E2E credits.
228  *					Initialized in: u-boot
229  *
230  * CPU_BOOT_DEV_STS0_HBM_CRED_EN	HBM credits initialized.
231  *					FW initialized HBM credits.
232  *					Initialized in: u-boot
233  *
234  * CPU_BOOT_DEV_STS0_RL_EN		Rate limiter initialized.
235  *					FW initialized rate limiter.
236  *					Initialized in: u-boot
237  *
238  * CPU_BOOT_DEV_STS0_SRAM_SCR_EN	SRAM scrambler enabled.
239  *					FW initialized SRAM scrambler.
240  *					Initialized in: linux
241  *
242  * CPU_BOOT_DEV_STS0_DRAM_SCR_EN	DRAM scrambler enabled.
243  *					FW initialized DRAM scrambler.
244  *					Initialized in: u-boot
245  *
246  * CPU_BOOT_DEV_STS0_FW_HARD_RST_EN	FW hard reset procedure is enabled.
247  *					FW has the hard reset procedure
248  *					implemented. This means that FW will
249  *					perform hard reset procedure on
250  *					receiving the halt-machine event.
251  *					Initialized in: preboot, u-boot, linux
252  *
253  * CPU_BOOT_DEV_STS0_PLL_INFO_EN	FW retrieval of PLL info is enabled.
254  *					Initialized in: linux
255  *
256  * CPU_BOOT_DEV_STS0_SP_SRAM_EN		SP SRAM is initialized and available
257  *					for use.
258  *					Initialized in: preboot
259  *
260  * CPU_BOOT_DEV_STS0_CLK_GATE_EN	Clock Gating enabled.
261  *					FW initialized Clock Gating.
262  *					Initialized in: preboot
263  *
264  * CPU_BOOT_DEV_STS0_HBM_ECC_EN		HBM ECC handling Enabled.
265  *					FW handles HBM ECC indications.
266  *					Initialized in: linux
267  *
268  * CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN	Packets ack value used in the armcpd
269  *					is set to the PI counter.
270  *					Initialized in: linux
271  *
272  * CPU_BOOT_DEV_STS0_FW_LD_COM_EN	Flexible FW loading communication
273  *					protocol is enabled.
274  *					Initialized in: preboot
275  *
276  * CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN	FW iATU configuration is enabled.
277  *					This bit if set, means the iATU has been
278  *					configured and is ready for use.
279  *					Initialized in: ppboot
280  *
281  * CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN	NIC MAC channels init is done by FW and
282  *					any access to them is done via the FW.
283  *					Initialized in: linux
284  *
285  * CPU_BOOT_DEV_STS0_DYN_PLL_EN		Dynamic PLL configuration is enabled.
286  *					FW sends to host a bitmap of supported
287  *					PLLs.
288  *					Initialized in: linux
289  *
290  * CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN	GIC access permission only from
291  *					previleged entity. FW sets this status
292  *					bit for host. If this bit is set then
293  *					GIC can not be accessed from host.
294  *					Initialized in: linux
295  *
296  * CPU_BOOT_DEV_STS0_EQ_INDEX_EN	Event Queue (EQ) index is a running
297  *					index for each new event sent to host.
298  *					This is used as a method in host to
299  *					identify that the waiting event in
300  *					queue is actually a new event which
301  *					was not served before.
302  *					Initialized in: linux
303  *
304  * CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN	Use multiple scratchpad interfaces to
305  *					prevent IRQs overriding each other.
306  *					Initialized in: linux
307  *
308  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN
309  *					NIC STAT and XPCS91 access is restricted
310  *					and is done via FW only.
311  *					Initialized in: linux
312  *
313  * CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN
314  *					NIC STAT get all is supported.
315  *					Initialized in: linux
316  *
317  * CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN
318  *					F/W checks if the device is idle by reading defined set
319  *					of registers. It returns a bitmask of all the engines,
320  *					where a bit is set if the engine is not idle.
321  *					Initialized in: linux
322  *
323  * CPU_BOOT_DEV_STS0_MAP_HWMON_EN
324  *					If set, means f/w supports proprietary
325  *					HWMON enum mapping to cpucp enums.
326  *					Initialized in: linux
327  *
328  * CPU_BOOT_DEV_STS0_ENABLED		Device status register enabled.
329  *					This is a main indication that the
330  *					running FW populates the device status
331  *					register. Meaning the device status
332  *					bits are not garbage, but actual
333  *					statuses.
334  *					Initialized in: preboot
335  *
336  */
337 #define CPU_BOOT_DEV_STS0_SECURITY_EN		(1 << CPU_BOOT_DEV_STS_SECURITY_EN)
338 #define CPU_BOOT_DEV_STS0_DEBUG_EN		(1 << CPU_BOOT_DEV_STS_DEBUG_EN)
339 #define CPU_BOOT_DEV_STS0_WATCHDOG_EN		(1 << CPU_BOOT_DEV_STS_WATCHDOG_EN)
340 #define CPU_BOOT_DEV_STS0_DRAM_INIT_EN		(1 << CPU_BOOT_DEV_STS_DRAM_INIT_EN)
341 #define CPU_BOOT_DEV_STS0_BMC_WAIT_EN		(1 << CPU_BOOT_DEV_STS_BMC_WAIT_EN)
342 #define CPU_BOOT_DEV_STS0_E2E_CRED_EN		(1 << CPU_BOOT_DEV_STS_E2E_CRED_EN)
343 #define CPU_BOOT_DEV_STS0_HBM_CRED_EN		(1 << CPU_BOOT_DEV_STS_HBM_CRED_EN)
344 #define CPU_BOOT_DEV_STS0_RL_EN			(1 << CPU_BOOT_DEV_STS_RL_EN)
345 #define CPU_BOOT_DEV_STS0_SRAM_SCR_EN		(1 << CPU_BOOT_DEV_STS_SRAM_SCR_EN)
346 #define CPU_BOOT_DEV_STS0_DRAM_SCR_EN		(1 << CPU_BOOT_DEV_STS_DRAM_SCR_EN)
347 #define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN	(1 << CPU_BOOT_DEV_STS_FW_HARD_RST_EN)
348 #define CPU_BOOT_DEV_STS0_PLL_INFO_EN		(1 << CPU_BOOT_DEV_STS_PLL_INFO_EN)
349 #define CPU_BOOT_DEV_STS0_SP_SRAM_EN		(1 << CPU_BOOT_DEV_STS_SP_SRAM_EN)
350 #define CPU_BOOT_DEV_STS0_CLK_GATE_EN		(1 << CPU_BOOT_DEV_STS_CLK_GATE_EN)
351 #define CPU_BOOT_DEV_STS0_HBM_ECC_EN		(1 << CPU_BOOT_DEV_STS_HBM_ECC_EN)
352 #define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN		(1 << CPU_BOOT_DEV_STS_PKT_PI_ACK_EN)
353 #define CPU_BOOT_DEV_STS0_FW_LD_COM_EN		(1 << CPU_BOOT_DEV_STS_FW_LD_COM_EN)
354 #define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN	(1 << CPU_BOOT_DEV_STS_FW_IATU_CONF_EN)
355 #define CPU_BOOT_DEV_STS0_FW_NIC_MAC_EN		(1 << CPU_BOOT_DEV_STS_FW_NIC_MAC_EN)
356 #define CPU_BOOT_DEV_STS0_DYN_PLL_EN		(1 << CPU_BOOT_DEV_STS_DYN_PLL_EN)
357 #define CPU_BOOT_DEV_STS0_GIC_PRIVILEGED_EN	(1 << CPU_BOOT_DEV_STS_GIC_PRIVILEGED_EN)
358 #define CPU_BOOT_DEV_STS0_EQ_INDEX_EN		(1 << CPU_BOOT_DEV_STS_EQ_INDEX_EN)
359 #define CPU_BOOT_DEV_STS0_MULTI_IRQ_POLL_EN	(1 << CPU_BOOT_DEV_STS_MULTI_IRQ_POLL_EN)
360 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_XPCS91_EN	(1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_XPCS91_EN)
361 #define CPU_BOOT_DEV_STS0_FW_NIC_STAT_EXT_EN	(1 << CPU_BOOT_DEV_STS_FW_NIC_STAT_EXT_EN)
362 #define CPU_BOOT_DEV_STS0_IS_IDLE_CHECK_EN	(1 << CPU_BOOT_DEV_STS_IS_IDLE_CHECK_EN)
363 #define CPU_BOOT_DEV_STS0_MAP_HWMON_EN		(1 << CPU_BOOT_DEV_STS_MAP_HWMON_EN)
364 #define CPU_BOOT_DEV_STS0_ENABLED		(1 << CPU_BOOT_DEV_STS_ENABLED)
365 #define CPU_BOOT_DEV_STS1_ENABLED		(1 << CPU_BOOT_DEV_STS_ENABLED)
366 
367 enum cpu_boot_status {
368 	CPU_BOOT_STATUS_NA = 0,		/* Default value after reset of chip */
369 	CPU_BOOT_STATUS_IN_WFE = 1,
370 	CPU_BOOT_STATUS_DRAM_RDY = 2,
371 	CPU_BOOT_STATUS_SRAM_AVAIL = 3,
372 	CPU_BOOT_STATUS_IN_BTL = 4,	/* BTL is H/W FSM */
373 	CPU_BOOT_STATUS_IN_PREBOOT = 5,
374 	CPU_BOOT_STATUS_IN_SPL,		/* deprecated - not reported */
375 	CPU_BOOT_STATUS_IN_UBOOT = 7,
376 	CPU_BOOT_STATUS_DRAM_INIT_FAIL,	/* deprecated - will be removed */
377 	CPU_BOOT_STATUS_FIT_CORRUPTED,	/* deprecated - will be removed */
378 	/* U-Boot console prompt activated, commands are not processed */
379 	CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
380 	/* Finished NICs init, reported after DRAM and NICs */
381 	CPU_BOOT_STATUS_NIC_FW_RDY = 11,
382 	CPU_BOOT_STATUS_TS_INIT_FAIL,	/* deprecated - will be removed */
383 	CPU_BOOT_STATUS_DRAM_SKIPPED,	/* deprecated - will be removed */
384 	CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
385 	/* Last boot loader progress status, ready to receive commands */
386 	CPU_BOOT_STATUS_READY_TO_BOOT = 15,
387 	/* Internal Boot finished, ready for boot-fit */
388 	CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
389 	/* Internal Security has been initialized, device can be accessed */
390 	CPU_BOOT_STATUS_SECURITY_READY = 17,
391 };
392 
393 enum kmd_msg {
394 	KMD_MSG_NA = 0,
395 	KMD_MSG_GOTO_WFE,
396 	KMD_MSG_FIT_RDY,
397 	KMD_MSG_SKIP_BMC,
398 	RESERVED,
399 	KMD_MSG_RST_DEV,
400 	KMD_MSG_LAST
401 };
402 
403 enum cpu_msg_status {
404 	CPU_MSG_CLR = 0,
405 	CPU_MSG_OK,
406 	CPU_MSG_ERR,
407 };
408 
409 /* communication registers mapping - consider ABI when changing */
410 struct cpu_dyn_regs {
411 	__le32 cpu_pq_base_addr_low;
412 	__le32 cpu_pq_base_addr_high;
413 	__le32 cpu_pq_length;
414 	__le32 cpu_pq_init_status;
415 	__le32 cpu_eq_base_addr_low;
416 	__le32 cpu_eq_base_addr_high;
417 	__le32 cpu_eq_length;
418 	__le32 cpu_eq_ci;
419 	__le32 cpu_cq_base_addr_low;
420 	__le32 cpu_cq_base_addr_high;
421 	__le32 cpu_cq_length;
422 	__le32 cpu_pf_pq_pi;
423 	__le32 cpu_boot_dev_sts0;
424 	__le32 cpu_boot_dev_sts1;
425 	__le32 cpu_boot_err0;
426 	__le32 cpu_boot_err1;
427 	__le32 cpu_boot_status;
428 	__le32 fw_upd_sts;
429 	__le32 fw_upd_cmd;
430 	__le32 fw_upd_pending_sts;
431 	__le32 fuse_ver_offset;
432 	__le32 preboot_ver_offset;
433 	__le32 uboot_ver_offset;
434 	__le32 hw_state;
435 	__le32 kmd_msg_to_cpu;
436 	__le32 cpu_cmd_status_to_host;
437 	__le32 gic_host_pi_upd_irq;
438 	__le32 gic_tpc_qm_irq_ctrl;
439 	__le32 gic_mme_qm_irq_ctrl;
440 	__le32 gic_dma_qm_irq_ctrl;
441 	__le32 gic_nic_qm_irq_ctrl;
442 	__le32 gic_dma_core_irq_ctrl;
443 	__le32 gic_host_halt_irq;
444 	__le32 gic_host_ints_irq;
445 	__le32 gic_host_soft_rst_irq;
446 	__le32 gic_rot_qm_irq_ctrl;
447 	__le32 cpu_rst_status;
448 	__le32 eng_arc_irq_ctrl;
449 	__le32 reserved1[20];		/* reserve for future use */
450 };
451 
452 /* TODO: remove the desc magic after the code is updated to use message */
453 /* HCDM - Habana Communications Descriptor Magic */
454 #define HL_COMMS_DESC_MAGIC	0x4843444D
455 #define HL_COMMS_DESC_VER	3
456 
457 /* HCMv - Habana Communications Message + header version */
458 #define HL_COMMS_MSG_MAGIC_VALUE	0x48434D00
459 #define HL_COMMS_MSG_MAGIC_MASK		0xFFFFFF00
460 #define HL_COMMS_MSG_MAGIC_VER_MASK	0xFF
461 
462 #define HL_COMMS_MSG_MAGIC_VER(ver)	(HL_COMMS_MSG_MAGIC_VALUE |	\
463 					((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
464 #define HL_COMMS_MSG_MAGIC_V0		HL_COMMS_DESC_MAGIC
465 #define HL_COMMS_MSG_MAGIC_V1		HL_COMMS_MSG_MAGIC_VER(1)
466 #define HL_COMMS_MSG_MAGIC_V2		HL_COMMS_MSG_MAGIC_VER(2)
467 #define HL_COMMS_MSG_MAGIC_V3		HL_COMMS_MSG_MAGIC_VER(3)
468 
469 #define HL_COMMS_MSG_MAGIC		HL_COMMS_MSG_MAGIC_V3
470 
471 #define HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC(magic)			\
472 		(((magic) & HL_COMMS_MSG_MAGIC_MASK) ==			\
473 		HL_COMMS_MSG_MAGIC_VALUE)
474 
475 #define HL_COMMS_MSG_MAGIC_VALIDATE_VERSION(magic, ver)			\
476 		(((magic) & HL_COMMS_MSG_MAGIC_VER_MASK) >=		\
477 		((ver) & HL_COMMS_MSG_MAGIC_VER_MASK))
478 
479 #define HL_COMMS_MSG_MAGIC_VALIDATE(magic, ver)				\
480 		(HL_COMMS_MSG_MAGIC_VALIDATE_MAGIC((magic)) &&		\
481 		HL_COMMS_MSG_MAGIC_VALIDATE_VERSION((magic), (ver)))
482 
483 enum comms_msg_type {
484 	HL_COMMS_DESC_TYPE = 0,
485 	HL_COMMS_RESET_CAUSE_TYPE = 1,
486 	HL_COMMS_FW_CFG_SKIP_TYPE = 2,
487 	HL_COMMS_BINNING_CONF_TYPE = 3,
488 };
489 
490 /*
491  * Binning information shared between LKD and FW
492  * @tpc_mask_l - TPC binning information lower 64 bit
493  * @dec_mask - Decoder binning information
494  * @dram_mask - DRAM binning information
495  * @edma_mask - EDMA binning information
496  * @mme_mask_l - MME binning information lower 32
497  * @mme_mask_h - MME binning information upper 32
498  * @rot_mask - Rotator binning information
499  * @xbar_mask - xBAR binning information
500  * @reserved - reserved field for future binning info w/o ABI change
501  * @tpc_mask_h - TPC binning information upper 64 bit
502  * @nic_mask - NIC binning information
503  */
504 struct lkd_fw_binning_info {
505 	__le64 tpc_mask_l;
506 	__le32 dec_mask;
507 	__le32 dram_mask;
508 	__le32 edma_mask;
509 	__le32 mme_mask_l;
510 	__le32 mme_mask_h;
511 	__le32 rot_mask;
512 	__le32 xbar_mask;
513 	__le32 reserved0;
514 	__le64 tpc_mask_h;
515 	__le64 nic_mask;
516 	__le32 reserved1[8];
517 };
518 
519 /* TODO: remove this struct after the code is updated to use message */
520 /* this is the comms descriptor header - meta data */
521 struct comms_desc_header {
522 	__le32 magic;		/* magic for validation */
523 	__le32 crc32;		/* CRC32 of the descriptor w/o header */
524 	__le16 size;		/* size of the descriptor w/o header */
525 	__u8 version;	/* descriptor version */
526 	__u8 reserved[5];	/* pad to 64 bit */
527 };
528 
529 /* this is the comms message header - meta data */
530 struct comms_msg_header {
531 	__le32 magic;		/* magic for validation */
532 	__le32 crc32;		/* CRC32 of the message w/o header */
533 	__le16 size;		/* size of the message w/o header */
534 	__u8 version;	/* message payload version */
535 	__u8 type;		/* message type */
536 	__u8 reserved[4];	/* pad to 64 bit */
537 };
538 
539 enum lkd_fw_ascii_msg_lvls {
540 	LKD_FW_ASCII_MSG_ERR = 0,
541 	LKD_FW_ASCII_MSG_WRN = 1,
542 	LKD_FW_ASCII_MSG_INF = 2,
543 	LKD_FW_ASCII_MSG_DBG = 3,
544 };
545 
546 #define LKD_FW_ASCII_MSG_MAX_LEN	128
547 #define LKD_FW_ASCII_MSG_MAX		4	/* consider ABI when changing */
548 
549 struct lkd_fw_ascii_msg {
550 	__u8 valid;
551 	__u8 msg_lvl;
552 	__u8 reserved[6];
553 	char msg[LKD_FW_ASCII_MSG_MAX_LEN];
554 };
555 
556 /* this is the main FW descriptor - consider ABI when changing */
557 struct lkd_fw_comms_desc {
558 	struct comms_desc_header header;
559 	struct cpu_dyn_regs cpu_dyn_regs;
560 	char fuse_ver[VERSION_MAX_LEN];
561 	char cur_fw_ver[VERSION_MAX_LEN];
562 	/* can be used for 1 more version w/o ABI change */
563 	char reserved0[VERSION_MAX_LEN];
564 	__le64 img_addr;	/* address for next FW component load */
565 	struct lkd_fw_binning_info binning_info;
566 	struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX];
567 };
568 
569 enum comms_reset_cause {
570 	HL_RESET_CAUSE_UNKNOWN = 0,
571 	HL_RESET_CAUSE_HEARTBEAT = 1,
572 	HL_RESET_CAUSE_TDR = 2,
573 };
574 
575 /* TODO: remove define after struct name is aligned on all projects */
576 #define lkd_msg_comms lkd_fw_comms_msg
577 
578 /* this is the comms message descriptor */
579 struct lkd_fw_comms_msg {
580 	struct comms_msg_header header;
581 	/* union for future expantions of new messages */
582 	union {
583 		struct {
584 			struct cpu_dyn_regs cpu_dyn_regs;
585 			char fuse_ver[VERSION_MAX_LEN];
586 			char cur_fw_ver[VERSION_MAX_LEN];
587 			/* can be used for 1 more version w/o ABI change */
588 			char reserved0[VERSION_MAX_LEN];
589 			/* address for next FW component load */
590 			__le64 img_addr;
591 			struct lkd_fw_binning_info binning_info;
592 			struct lkd_fw_ascii_msg ascii_msg[LKD_FW_ASCII_MSG_MAX];
593 		};
594 		struct {
595 			__u8 reset_cause;
596 		};
597 		struct {
598 			__u8 fw_cfg_skip; /* 1 - skip, 0 - don't skip */
599 		};
600 		struct lkd_fw_binning_info binning_conf;
601 	};
602 };
603 
604 /*
605  * LKD commands:
606  *
607  * COMMS_NOOP			Used to clear the command register and no actual
608  *				command is send.
609  *
610  * COMMS_CLR_STS		Clear status command - FW should clear the
611  *				status register. Used for synchronization
612  *				between the commands as part of the race free
613  *				protocol.
614  *
615  * COMMS_RST_STATE		Reset the current communication state which is
616  *				kept by FW for proper responses.
617  *				Should be used in the beginning of the
618  *				communication cycle to clean any leftovers from
619  *				previous communication attempts.
620  *
621  * COMMS_PREP_DESC		Prepare descriptor for setting up the
622  *				communication and other dynamic data:
623  *				struct lkd_fw_comms_desc.
624  *				This command has a parameter stating the next FW
625  *				component size, so the FW can actually prepare a
626  *				space for it and in the status response provide
627  *				the descriptor offset. The Offset of the next FW
628  *				data component is a part of the descriptor
629  *				structure.
630  *
631  * COMMS_DATA_RDY		The FW data has been uploaded and is ready for
632  *				validation.
633  *
634  * COMMS_EXEC			Execute the next FW component.
635  *
636  * COMMS_RST_DEV		Reset the device.
637  *
638  * COMMS_GOTO_WFE		Execute WFE command. Allowed only on non-secure
639  *				devices.
640  *
641  * COMMS_SKIP_BMC		Perform actions required for BMC-less servers.
642  *				Do not wait for BMC response.
643  *
644  * COMMS_PREP_DESC_ELBI		Same as COMMS_PREP_DESC only that the memory
645  *				space is allocated in a ELBI access only
646  *				address range.
647  *
648  */
649 enum comms_cmd {
650 	COMMS_NOOP = 0,
651 	COMMS_CLR_STS = 1,
652 	COMMS_RST_STATE = 2,
653 	COMMS_PREP_DESC = 3,
654 	COMMS_DATA_RDY = 4,
655 	COMMS_EXEC = 5,
656 	COMMS_RST_DEV = 6,
657 	COMMS_GOTO_WFE = 7,
658 	COMMS_SKIP_BMC = 8,
659 	COMMS_PREP_DESC_ELBI = 10,
660 	COMMS_INVLD_LAST
661 };
662 
663 #define COMMS_COMMAND_SIZE_SHIFT	0
664 #define COMMS_COMMAND_SIZE_MASK		0x1FFFFFF
665 #define COMMS_COMMAND_CMD_SHIFT		27
666 #define COMMS_COMMAND_CMD_MASK		0xF8000000
667 
668 /*
669  * LKD command to FW register structure
670  * @size	- FW component size
671  * @cmd		- command from enum comms_cmd
672  */
673 struct comms_command {
674 	union {		/* bit fields are only for FW use */
675 		struct {
676 			u32 size :25;		/* 32MB max. */
677 			u32 reserved :2;
678 			enum comms_cmd cmd :5;		/* 32 commands */
679 		};
680 		__le32 val;
681 	};
682 };
683 
684 /*
685  * FW status
686  *
687  * COMMS_STS_NOOP		Used to clear the status register and no actual
688  *				status is provided.
689  *
690  * COMMS_STS_ACK		Command has been received and recognized.
691  *
692  * COMMS_STS_OK			Command execution has finished successfully.
693  *
694  * COMMS_STS_ERR		Command execution was unsuccessful and resulted
695  *				in error.
696  *
697  * COMMS_STS_VALID_ERR		FW validation has failed.
698  *
699  * COMMS_STS_TIMEOUT_ERR	Command execution has timed out.
700  */
701 enum comms_sts {
702 	COMMS_STS_NOOP = 0,
703 	COMMS_STS_ACK = 1,
704 	COMMS_STS_OK = 2,
705 	COMMS_STS_ERR = 3,
706 	COMMS_STS_VALID_ERR = 4,
707 	COMMS_STS_TIMEOUT_ERR = 5,
708 	COMMS_STS_INVLD_LAST
709 };
710 
711 /* RAM types for FW components loading - defines the base address */
712 enum comms_ram_types {
713 	COMMS_SRAM = 0,
714 	COMMS_DRAM = 1,
715 };
716 
717 #define COMMS_STATUS_OFFSET_SHIFT	0
718 #define COMMS_STATUS_OFFSET_MASK	0x03FFFFFF
719 #define COMMS_STATUS_OFFSET_ALIGN_SHIFT	2
720 #define COMMS_STATUS_RAM_TYPE_SHIFT	26
721 #define COMMS_STATUS_RAM_TYPE_MASK	0x0C000000
722 #define COMMS_STATUS_STATUS_SHIFT	28
723 #define COMMS_STATUS_STATUS_MASK	0xF0000000
724 
725 /*
726  * FW status to LKD register structure
727  * @offset	- an offset from the base of the ram_type shifted right by
728  *		  2 bits (always aligned to 32 bits).
729  *		  Allows a maximum addressable offset of 256MB from RAM base.
730  *		  Example: for real offset in RAM of 0x800000 (8MB), the value
731  *		  in offset field is (0x800000 >> 2) = 0x200000.
732  * @ram_type	- the RAM type that should be used for offset from
733  *		  enum comms_ram_types
734  * @status	- status from enum comms_sts
735  */
736 struct comms_status {
737 	union {		/* bit fields are only for FW use */
738 		struct {
739 			u32 offset :26;
740 			enum comms_ram_types ram_type :2;
741 			enum comms_sts status :4;	/* 16 statuses */
742 		};
743 		__le32 val;
744 	};
745 };
746 
747 /**
748  * HL_MODULES_MAX_NUM is determined by the size of modules_mask in struct
749  *      hl_component_versions
750  */
751 enum hl_modules {
752 	HL_MODULES_BOOT_INFO = 0,
753 	HL_MODULES_EEPROM,
754 	HL_MODULES_FDT,
755 	HL_MODULES_I2C,
756 	HL_MODULES_LZ4,
757 	HL_MODULES_MBEDTLS,
758 	HL_MODULES_MAX_NUM = 16
759 };
760 
761 /**
762  * HL_COMPONENTS_MAX_NUM is determined by the size of components_mask in
763  *      struct cpucp_versions
764  */
765 enum hl_components {
766 	HL_COMPONENTS_PID = 0,
767 	HL_COMPONENTS_MGMT,
768 	HL_COMPONENTS_PREBOOT,
769 	HL_COMPONENTS_PPBOOT,
770 	HL_COMPONENTS_ARMCP,
771 	HL_COMPONENTS_CPLD,
772 	HL_COMPONENTS_UBOOT,
773 	HL_COMPONENTS_MAX_NUM = 16
774 };
775 
776 /**
777  * struct hl_component_versions - versions associated with hl component.
778  * @struct_size: size of all the struct (including dynamic size of modules).
779  * @modules_offset: offset of the modules field in this struct.
780  * @component: version of the component itself.
781  * @fw_os: Firmware OS Version.
782  * @modules_mask: i'th bit (from LSB) is a flag - on if module i in enum
783  *              hl_modules is used.
784  * @modules_counter: number of set bits in modules_mask.
785  * @reserved: reserved for future use.
786  * @modules: versions of the component's modules. Elborated explanation in
787  *              struct cpucp_versions.
788  */
789 struct hl_component_versions {
790 	__le16 struct_size;
791 	__le16 modules_offset;
792 	__u8 component[VERSION_MAX_LEN];
793 	__u8 fw_os[VERSION_MAX_LEN];
794 	__le16 modules_mask;
795 	__u8 modules_counter;
796 	__u8 reserved[1];
797 	__u8 modules[][VERSION_MAX_LEN];
798 };
799 
800 /**
801  * struct hl_fw_versions - all versions (fuse, cpucp's components with their
802  *              modules)
803  * @struct_size: size of all the struct (including dynamic size of components).
804  * @components_offset: offset of the components field in this struct.
805  * @fuse: silicon production FUSE information.
806  * @components_mask: i'th bit (from LSB) is a flag - on if component i in enum
807  *              hl_components is used.
808  * @components_counter: number of set bits in components_mask.
809  * @reserved: reserved for future use.
810  * @components: versions of hl components. Index i corresponds to the i'th bit
811  *              that is *on* in components_mask. For example, if
812  *              components_mask=0b101, then *components represents arcpid and
813  *              *(hl_component_versions*)((char*)components + 1') represents
814  *              preboot, where 1' = components[0].struct_size.
815  */
816 struct hl_fw_versions {
817 	__le16 struct_size;
818 	__le16 components_offset;
819 	__u8 fuse[VERSION_MAX_LEN];
820 	__le16 components_mask;
821 	__u8 components_counter;
822 	__u8 reserved[1];
823 	struct hl_component_versions components[];
824 };
825 
826 /* Max size of struct hl_component_versions */
827 #define HL_COMPONENT_VERSIONS_MAX_SIZE \
828 	(sizeof(struct hl_component_versions) + HL_MODULES_MAX_NUM * \
829 	 VERSION_MAX_LEN)
830 
831 /* Max size of struct hl_fw_versions */
832 #define HL_FW_VERSIONS_MAX_SIZE (sizeof(struct hl_fw_versions) + \
833 		HL_COMPONENTS_MAX_NUM * HL_COMPONENT_VERSIONS_MAX_SIZE)
834 
835 #endif /* HL_BOOT_IF_H */
836