1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2020-2022 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef CPUCP_IF_H 9 #define CPUCP_IF_H 10 11 #include <linux/types.h> 12 #include <linux/if_ether.h> 13 14 #include "hl_boot_if.h" 15 16 #define NUM_HBM_PSEUDO_CH 2 17 #define NUM_HBM_CH_PER_DEV 8 18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0 19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001 20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1 21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002 22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2 23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004 24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3 25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008 26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4 27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010 28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5 29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020 30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6 31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0 32 33 #define PLL_MAP_MAX_BITS 128 34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8) 35 36 /* 37 * info of the pkt queue pointers in the first async occurrence 38 */ 39 struct cpucp_pkt_sync_err { 40 __le32 pi; 41 __le32 ci; 42 }; 43 44 struct hl_eq_hbm_ecc_data { 45 /* SERR counter */ 46 __le32 sec_cnt; 47 /* DERR counter */ 48 __le32 dec_cnt; 49 /* Supplemental Information according to the mask bits */ 50 __le32 hbm_ecc_info; 51 /* Address in hbm where the ecc happened */ 52 __le32 first_addr; 53 /* SERR continuous address counter */ 54 __le32 sec_cont_cnt; 55 __le32 pad; 56 }; 57 58 /* 59 * EVENT QUEUE 60 */ 61 62 struct hl_eq_header { 63 __le32 reserved; 64 __le32 ctl; 65 }; 66 67 struct hl_eq_ecc_data { 68 __le64 ecc_address; 69 __le64 ecc_syndrom; 70 __u8 memory_wrapper_idx; 71 __u8 is_critical; 72 __u8 pad[6]; 73 }; 74 75 enum hl_sm_sei_cause { 76 SM_SEI_SO_OVERFLOW, 77 SM_SEI_LBW_4B_UNALIGNED, 78 SM_SEI_AXI_RESPONSE_ERR 79 }; 80 81 struct hl_eq_sm_sei_data { 82 __le32 sei_log; 83 /* enum hl_sm_sei_cause */ 84 __u8 sei_cause; 85 __u8 pad[3]; 86 }; 87 88 enum hl_fw_alive_severity { 89 FW_ALIVE_SEVERITY_MINOR, 90 FW_ALIVE_SEVERITY_CRITICAL 91 }; 92 93 struct hl_eq_fw_alive { 94 __le64 uptime_seconds; 95 __le32 process_id; 96 __le32 thread_id; 97 /* enum hl_fw_alive_severity */ 98 __u8 severity; 99 __u8 pad[7]; 100 }; 101 102 struct hl_eq_intr_cause { 103 __le64 intr_cause_data; 104 }; 105 106 struct hl_eq_pcie_drain_ind_data { 107 struct hl_eq_intr_cause intr_cause; 108 __le64 drain_wr_addr_lbw; 109 __le64 drain_rd_addr_lbw; 110 __le64 drain_wr_addr_hbw; 111 __le64 drain_rd_addr_hbw; 112 }; 113 114 struct hl_eq_razwi_lbw_info_regs { 115 __le32 rr_aw_razwi_reg; 116 __le32 rr_aw_razwi_id_reg; 117 __le32 rr_ar_razwi_reg; 118 __le32 rr_ar_razwi_id_reg; 119 }; 120 121 struct hl_eq_razwi_hbw_info_regs { 122 __le32 rr_aw_razwi_hi_reg; 123 __le32 rr_aw_razwi_lo_reg; 124 __le32 rr_aw_razwi_id_reg; 125 __le32 rr_ar_razwi_hi_reg; 126 __le32 rr_ar_razwi_lo_reg; 127 __le32 rr_ar_razwi_id_reg; 128 }; 129 130 /* razwi_happened masks */ 131 #define RAZWI_HAPPENED_HBW 0x1 132 #define RAZWI_HAPPENED_LBW 0x2 133 #define RAZWI_HAPPENED_AW 0x4 134 #define RAZWI_HAPPENED_AR 0x8 135 136 struct hl_eq_razwi_info { 137 __le32 razwi_happened_mask; 138 union { 139 struct hl_eq_razwi_lbw_info_regs lbw; 140 struct hl_eq_razwi_hbw_info_regs hbw; 141 }; 142 __le32 pad; 143 }; 144 145 struct hl_eq_razwi_with_intr_cause { 146 struct hl_eq_razwi_info razwi_info; 147 struct hl_eq_intr_cause intr_cause; 148 }; 149 150 #define HBM_CA_ERR_CMD_LIFO_LEN 8 151 #define HBM_RD_ERR_DATA_LIFO_LEN 8 152 #define HBM_WR_PAR_CMD_LIFO_LEN 11 153 154 enum hl_hbm_sei_cause { 155 /* Command/address parity error event is split into 2 events due to 156 * size limitation: ODD suffix for odd HBM CK_t cycles and EVEN suffix 157 * for even HBM CK_t cycles 158 */ 159 HBM_SEI_CMD_PARITY_EVEN, 160 HBM_SEI_CMD_PARITY_ODD, 161 /* Read errors can be reflected as a combination of SERR/DERR/parity 162 * errors. Therefore, we define one event for all read error types. 163 * LKD will perform further proccessing. 164 */ 165 HBM_SEI_READ_ERR, 166 HBM_SEI_WRITE_DATA_PARITY_ERR, 167 HBM_SEI_CATTRIP, 168 HBM_SEI_MEM_BIST_FAIL, 169 HBM_SEI_DFI, 170 HBM_SEI_INV_TEMP_READ_OUT, 171 HBM_SEI_BIST_FAIL, 172 }; 173 174 /* Masks for parsing hl_hbm_sei_headr fields */ 175 #define HBM_ECC_SERR_CNTR_MASK 0xFF 176 #define HBM_ECC_DERR_CNTR_MASK 0xFF00 177 #define HBM_RD_PARITY_CNTR_MASK 0xFF0000 178 179 /* HBM index and MC index are known by the event_id */ 180 struct hl_hbm_sei_header { 181 union { 182 /* relevant only in case of HBM read error */ 183 struct { 184 __u8 ecc_serr_cnt; 185 __u8 ecc_derr_cnt; 186 __u8 read_par_cnt; 187 __u8 reserved; 188 }; 189 /* All other cases */ 190 __le32 cnt; 191 }; 192 __u8 sei_cause; /* enum hl_hbm_sei_cause */ 193 __u8 mc_channel; /* range: 0-3 */ 194 __u8 mc_pseudo_channel; /* range: 0-7 */ 195 __u8 is_critical; 196 }; 197 198 #define HBM_RD_ADDR_SID_SHIFT 0 199 #define HBM_RD_ADDR_SID_MASK 0x1 200 #define HBM_RD_ADDR_BG_SHIFT 1 201 #define HBM_RD_ADDR_BG_MASK 0x6 202 #define HBM_RD_ADDR_BA_SHIFT 3 203 #define HBM_RD_ADDR_BA_MASK 0x18 204 #define HBM_RD_ADDR_COL_SHIFT 5 205 #define HBM_RD_ADDR_COL_MASK 0x7E0 206 #define HBM_RD_ADDR_ROW_SHIFT 11 207 #define HBM_RD_ADDR_ROW_MASK 0x3FFF800 208 209 struct hbm_rd_addr { 210 union { 211 /* bit fields are only for FW use */ 212 struct { 213 u32 dbg_rd_err_addr_sid:1; 214 u32 dbg_rd_err_addr_bg:2; 215 u32 dbg_rd_err_addr_ba:2; 216 u32 dbg_rd_err_addr_col:6; 217 u32 dbg_rd_err_addr_row:15; 218 u32 reserved:6; 219 }; 220 __le32 rd_addr_val; 221 }; 222 }; 223 224 #define HBM_RD_ERR_BEAT_SHIFT 2 225 /* dbg_rd_err_misc fields: */ 226 /* Read parity is calculated per DW on every beat */ 227 #define HBM_RD_ERR_PAR_ERR_BEAT0_SHIFT 0 228 #define HBM_RD_ERR_PAR_ERR_BEAT0_MASK 0x3 229 #define HBM_RD_ERR_PAR_DATA_BEAT0_SHIFT 8 230 #define HBM_RD_ERR_PAR_DATA_BEAT0_MASK 0x300 231 /* ECC is calculated per PC on every beat */ 232 #define HBM_RD_ERR_SERR_BEAT0_SHIFT 16 233 #define HBM_RD_ERR_SERR_BEAT0_MASK 0x10000 234 #define HBM_RD_ERR_DERR_BEAT0_SHIFT 24 235 #define HBM_RD_ERR_DERR_BEAT0_MASK 0x100000 236 237 struct hl_eq_hbm_sei_read_err_intr_info { 238 /* DFI_RD_ERR_REP_ADDR */ 239 struct hbm_rd_addr dbg_rd_err_addr; 240 /* DFI_RD_ERR_REP_ERR */ 241 union { 242 struct { 243 /* bit fields are only for FW use */ 244 u32 dbg_rd_err_par:8; 245 u32 dbg_rd_err_par_data:8; 246 u32 dbg_rd_err_serr:4; 247 u32 dbg_rd_err_derr:4; 248 u32 reserved:8; 249 }; 250 __le32 dbg_rd_err_misc; 251 }; 252 /* DFI_RD_ERR_REP_DM */ 253 __le32 dbg_rd_err_dm; 254 /* DFI_RD_ERR_REP_SYNDROME */ 255 __le32 dbg_rd_err_syndrome; 256 /* DFI_RD_ERR_REP_DATA */ 257 __le32 dbg_rd_err_data[HBM_RD_ERR_DATA_LIFO_LEN]; 258 }; 259 260 struct hl_eq_hbm_sei_ca_par_intr_info { 261 /* 14 LSBs */ 262 __le16 dbg_row[HBM_CA_ERR_CMD_LIFO_LEN]; 263 /* 18 LSBs */ 264 __le32 dbg_col[HBM_CA_ERR_CMD_LIFO_LEN]; 265 }; 266 267 #define WR_PAR_LAST_CMD_COL_SHIFT 0 268 #define WR_PAR_LAST_CMD_COL_MASK 0x3F 269 #define WR_PAR_LAST_CMD_BG_SHIFT 6 270 #define WR_PAR_LAST_CMD_BG_MASK 0xC0 271 #define WR_PAR_LAST_CMD_BA_SHIFT 8 272 #define WR_PAR_LAST_CMD_BA_MASK 0x300 273 #define WR_PAR_LAST_CMD_SID_SHIFT 10 274 #define WR_PAR_LAST_CMD_SID_MASK 0x400 275 276 /* Row address isn't latched */ 277 struct hbm_sei_wr_cmd_address { 278 /* DFI_DERR_LAST_CMD */ 279 union { 280 struct { 281 /* bit fields are only for FW use */ 282 u32 col:6; 283 u32 bg:2; 284 u32 ba:2; 285 u32 sid:1; 286 u32 reserved:21; 287 }; 288 __le32 dbg_wr_cmd_addr; 289 }; 290 }; 291 292 struct hl_eq_hbm_sei_wr_par_intr_info { 293 /* entry 0: WR command address from the 1st cycle prior to the error 294 * entry 1: WR command address from the 2nd cycle prior to the error 295 * and so on... 296 */ 297 struct hbm_sei_wr_cmd_address dbg_last_wr_cmds[HBM_WR_PAR_CMD_LIFO_LEN]; 298 /* derr[0:1] - 1st HBM cycle DERR output 299 * derr[2:3] - 2nd HBM cycle DERR output 300 */ 301 __u8 dbg_derr; 302 /* extend to reach 8B */ 303 __u8 pad[3]; 304 }; 305 306 /* 307 * this struct represents the following sei causes: 308 * command parity, ECC double error, ECC single error, dfi error, cattrip, 309 * temperature read-out, read parity error and write parity error. 310 * some only use the header while some have extra data. 311 */ 312 struct hl_eq_hbm_sei_data { 313 struct hl_hbm_sei_header hdr; 314 union { 315 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_even_info; 316 struct hl_eq_hbm_sei_ca_par_intr_info ca_parity_odd_info; 317 struct hl_eq_hbm_sei_read_err_intr_info read_err_info; 318 struct hl_eq_hbm_sei_wr_par_intr_info wr_parity_info; 319 }; 320 }; 321 322 /* Engine/farm arc interrupt type */ 323 enum hl_engine_arc_interrupt_type { 324 /* Qman/farm ARC DCCM QUEUE FULL interrupt type */ 325 ENGINE_ARC_DCCM_QUEUE_FULL_IRQ = 1 326 }; 327 328 /* Data structure specifies details of payload of DCCM QUEUE FULL interrupt */ 329 struct hl_engine_arc_dccm_queue_full_irq { 330 /* Queue index value which caused DCCM QUEUE FULL */ 331 __le32 queue_index; 332 __le32 pad; 333 }; 334 335 /* Data structure specifies details of QM/FARM ARC interrupt */ 336 struct hl_eq_engine_arc_intr_data { 337 /* ARC engine id e.g. DCORE0_TPC0_QM_ARC, DCORE0_TCP1_QM_ARC */ 338 __le32 engine_id; 339 __le32 intr_type; /* enum hl_engine_arc_interrupt_type */ 340 /* More info related to the interrupt e.g. queue index 341 * incase of DCCM_QUEUE_FULL interrupt. 342 */ 343 __le64 payload; 344 __le64 pad[5]; 345 }; 346 347 #define ADDR_DEC_ADDRESS_COUNT_MAX 4 348 349 /* Data structure specifies details of ADDR_DEC interrupt */ 350 struct hl_eq_addr_dec_intr_data { 351 struct hl_eq_intr_cause intr_cause; 352 __le64 addr[ADDR_DEC_ADDRESS_COUNT_MAX]; 353 __u8 addr_cnt; 354 __u8 pad[7]; 355 }; 356 357 struct hl_eq_entry { 358 struct hl_eq_header hdr; 359 union { 360 struct hl_eq_ecc_data ecc_data; 361 struct hl_eq_hbm_ecc_data hbm_ecc_data; /* Gaudi1 HBM */ 362 struct hl_eq_sm_sei_data sm_sei_data; 363 struct cpucp_pkt_sync_err pkt_sync_err; 364 struct hl_eq_fw_alive fw_alive; 365 struct hl_eq_intr_cause intr_cause; 366 struct hl_eq_pcie_drain_ind_data pcie_drain_ind_data; 367 struct hl_eq_razwi_info razwi_info; 368 struct hl_eq_razwi_with_intr_cause razwi_with_intr_cause; 369 struct hl_eq_hbm_sei_data sei_data; /* Gaudi2 HBM */ 370 struct hl_eq_engine_arc_intr_data arc_data; 371 struct hl_eq_addr_dec_intr_data addr_dec; 372 __le64 data[7]; 373 }; 374 }; 375 376 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry) 377 378 #define EQ_CTL_READY_SHIFT 31 379 #define EQ_CTL_READY_MASK 0x80000000 380 381 #define EQ_CTL_EVENT_TYPE_SHIFT 16 382 #define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000 383 384 #define EQ_CTL_INDEX_SHIFT 0 385 #define EQ_CTL_INDEX_MASK 0x0000FFFF 386 387 enum pq_init_status { 388 PQ_INIT_STATUS_NA = 0, 389 PQ_INIT_STATUS_READY_FOR_CP, 390 PQ_INIT_STATUS_READY_FOR_HOST, 391 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI, 392 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR, 393 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR 394 }; 395 396 /* 397 * CpuCP Primary Queue Packets 398 * 399 * During normal operation, the host's kernel driver needs to send various 400 * messages to CpuCP, usually either to SET some value into a H/W periphery or 401 * to GET the current value of some H/W periphery. For example, SET the 402 * frequency of MME/TPC and GET the value of the thermal sensor. 403 * 404 * These messages can be initiated either by the User application or by the 405 * host's driver itself, e.g. power management code. In either case, the 406 * communication from the host's driver to CpuCP will *always* be in 407 * synchronous mode, meaning that the host will send a single message and poll 408 * until the message was acknowledged and the results are ready (if results are 409 * needed). 410 * 411 * This means that only a single message can be sent at a time and the host's 412 * driver must wait for its result before sending the next message. Having said 413 * that, because these are control messages which are sent in a relatively low 414 * frequency, this limitation seems acceptable. It's important to note that 415 * in case of multiple devices, messages to different devices *can* be sent 416 * at the same time. 417 * 418 * The message, inputs/outputs (if relevant) and fence object will be located 419 * on the device DDR at an address that will be determined by the host's driver. 420 * During device initialization phase, the host will pass to CpuCP that address. 421 * Most of the message types will contain inputs/outputs inside the message 422 * itself. The common part of each message will contain the opcode of the 423 * message (its type) and a field representing a fence object. 424 * 425 * When the host's driver wishes to send a message to CPU CP, it will write the 426 * message contents to the device DDR, clear the fence object and then write to 427 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU. 428 * 429 * Upon receiving the interrupt (#121), CpuCP will read the message from the 430 * DDR. In case the message is a SET operation, CpuCP will first perform the 431 * operation and then write to the fence object on the device DDR. In case the 432 * message is a GET operation, CpuCP will first fill the results section on the 433 * device DDR and then write to the fence object. If an error occurred, CpuCP 434 * will fill the rc field with the right error code. 435 * 436 * In the meantime, the host's driver will poll on the fence object. Once the 437 * host sees that the fence object is signaled, it will read the results from 438 * the device DDR (if relevant) and resume the code execution in the host's 439 * driver. 440 * 441 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8 442 * so the value being put by the host's driver matches the value read by CpuCP 443 * 444 * Non-QMAN packets should be limited to values 1 through (2^8 - 1) 445 * 446 * Detailed description: 447 * 448 * CPUCP_PACKET_DISABLE_PCI_ACCESS - 449 * After receiving this packet the embedded CPU must NOT issue PCI 450 * transactions (read/write) towards the Host CPU. This also include 451 * sending MSI-X interrupts. 452 * This packet is usually sent before the device is moved to D3Hot state. 453 * 454 * CPUCP_PACKET_ENABLE_PCI_ACCESS - 455 * After receiving this packet the embedded CPU is allowed to issue PCI 456 * transactions towards the Host CPU, including sending MSI-X interrupts. 457 * This packet is usually send after the device is moved to D0 state. 458 * 459 * CPUCP_PACKET_TEMPERATURE_GET - 460 * Fetch the current temperature / Max / Max Hyst / Critical / 461 * Critical Hyst of a specified thermal sensor. The packet's 462 * arguments specify the desired sensor and the field to get. 463 * 464 * CPUCP_PACKET_VOLTAGE_GET - 465 * Fetch the voltage / Max / Min of a specified sensor. The packet's 466 * arguments specify the sensor and type. 467 * 468 * CPUCP_PACKET_CURRENT_GET - 469 * Fetch the current / Max / Min of a specified sensor. The packet's 470 * arguments specify the sensor and type. 471 * 472 * CPUCP_PACKET_FAN_SPEED_GET - 473 * Fetch the speed / Max / Min of a specified fan. The packet's 474 * arguments specify the sensor and type. 475 * 476 * CPUCP_PACKET_PWM_GET - 477 * Fetch the pwm value / mode of a specified pwm. The packet's 478 * arguments specify the sensor and type. 479 * 480 * CPUCP_PACKET_PWM_SET - 481 * Set the pwm value / mode of a specified pwm. The packet's 482 * arguments specify the sensor, type and value. 483 * 484 * CPUCP_PACKET_FREQUENCY_SET - 485 * Set the frequency of a specified PLL. The packet's arguments specify 486 * the PLL and the desired frequency. The actual frequency in the device 487 * might differ from the requested frequency. 488 * 489 * CPUCP_PACKET_FREQUENCY_GET - 490 * Fetch the frequency of a specified PLL. The packet's arguments specify 491 * the PLL. 492 * 493 * CPUCP_PACKET_LED_SET - 494 * Set the state of a specified led. The packet's arguments 495 * specify the led and the desired state. 496 * 497 * CPUCP_PACKET_I2C_WR - 498 * Write 32-bit value to I2C device. The packet's arguments specify the 499 * I2C bus, address and value. 500 * 501 * CPUCP_PACKET_I2C_RD - 502 * Read 32-bit value from I2C device. The packet's arguments specify the 503 * I2C bus and address. 504 * 505 * CPUCP_PACKET_INFO_GET - 506 * Fetch information from the device as specified in the packet's 507 * structure. The host's driver passes the max size it allows the CpuCP to 508 * write to the structure, to prevent data corruption in case of 509 * mismatched driver/FW versions. 510 * 511 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed 512 * 513 * CPUCP_PACKET_UNMASK_RAZWI_IRQ - 514 * Unmask the given IRQ. The IRQ number is specified in the value field. 515 * The packet is sent after receiving an interrupt and printing its 516 * relevant information. 517 * 518 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY - 519 * Unmask the given IRQs. The IRQs numbers are specified in an array right 520 * after the cpucp_packet structure, where its first element is the array 521 * length. The packet is sent after a soft reset was done in order to 522 * handle any interrupts that were sent during the reset process. 523 * 524 * CPUCP_PACKET_TEST - 525 * Test packet for CpuCP connectivity. The CPU will put the fence value 526 * in the result field. 527 * 528 * CPUCP_PACKET_FREQUENCY_CURR_GET - 529 * Fetch the current frequency of a specified PLL. The packet's arguments 530 * specify the PLL. 531 * 532 * CPUCP_PACKET_MAX_POWER_GET - 533 * Fetch the maximal power of the device. 534 * 535 * CPUCP_PACKET_MAX_POWER_SET - 536 * Set the maximal power of the device. The packet's arguments specify 537 * the power. 538 * 539 * CPUCP_PACKET_EEPROM_DATA_GET - 540 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the 541 * addr field. The CPU will put the returned data size in the result 542 * field. In addition, the host's driver passes the max size it allows the 543 * CpuCP to write to the structure, to prevent data corruption in case of 544 * mismatched driver/FW versions. 545 * 546 * CPUCP_PACKET_NIC_INFO_GET - 547 * Fetch information from the device regarding the NIC. the host's driver 548 * passes the max size it allows the CpuCP to write to the structure, to 549 * prevent data corruption in case of mismatched driver/FW versions. 550 * 551 * CPUCP_PACKET_TEMPERATURE_SET - 552 * Set the value of the offset property of a specified thermal sensor. 553 * The packet's arguments specify the desired sensor and the field to 554 * set. 555 * 556 * CPUCP_PACKET_VOLTAGE_SET - 557 * Trigger the reset_history property of a specified voltage sensor. 558 * The packet's arguments specify the desired sensor and the field to 559 * set. 560 * 561 * CPUCP_PACKET_CURRENT_SET - 562 * Trigger the reset_history property of a specified current sensor. 563 * The packet's arguments specify the desired sensor and the field to 564 * set. 565 * 566 * CPUCP_PACKET_PCIE_THROUGHPUT_GET - 567 * Get throughput of PCIe. 568 * The packet's arguments specify the transaction direction (TX/RX). 569 * The window measurement is 10[msec], and the return value is in KB/sec. 570 * 571 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET 572 * Replay count measures number of "replay" events, which is basicly 573 * number of retries done by PCIe. 574 * 575 * CPUCP_PACKET_TOTAL_ENERGY_GET - 576 * Total Energy is measurement of energy from the time FW Linux 577 * is loaded. It is calculated by multiplying the average power 578 * by time (passed from armcp start). The units are in MilliJouls. 579 * 580 * CPUCP_PACKET_PLL_INFO_GET - 581 * Fetch frequencies of PLL from the required PLL IP. 582 * The packet's arguments specify the device PLL type 583 * Pll type is the PLL from device pll_index enum. 584 * The result is composed of 4 outputs, each is 16-bit 585 * frequency in MHz. 586 * 587 * CPUCP_PACKET_POWER_GET - 588 * Fetch the present power consumption of the device (Current * Voltage). 589 * 590 * CPUCP_PACKET_NIC_PFC_SET - 591 * Enable/Disable the NIC PFC feature. The packet's arguments specify the 592 * NIC port, relevant lanes to configure and one bit indication for 593 * enable/disable. 594 * 595 * CPUCP_PACKET_NIC_FAULT_GET - 596 * Fetch the current indication for local/remote faults from the NIC MAC. 597 * The result is 32-bit value of the relevant register. 598 * 599 * CPUCP_PACKET_NIC_LPBK_SET - 600 * Enable/Disable the MAC loopback feature. The packet's arguments specify 601 * the NIC port, relevant lanes to configure and one bit indication for 602 * enable/disable. 603 * 604 * CPUCP_PACKET_NIC_MAC_INIT - 605 * Configure the NIC MAC channels. The packet's arguments specify the 606 * NIC port and the speed. 607 * 608 * CPUCP_PACKET_MSI_INFO_SET - 609 * set the index number for each supported msi type going from 610 * host to device 611 * 612 * CPUCP_PACKET_NIC_XPCS91_REGS_GET - 613 * Fetch the un/correctable counters values from the NIC MAC. 614 * 615 * CPUCP_PACKET_NIC_STAT_REGS_GET - 616 * Fetch various NIC MAC counters from the NIC STAT. 617 * 618 * CPUCP_PACKET_NIC_STAT_REGS_CLR - 619 * Clear the various NIC MAC counters in the NIC STAT. 620 * 621 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET - 622 * Fetch all NIC MAC counters from the NIC STAT. 623 * 624 * CPUCP_PACKET_IS_IDLE_CHECK - 625 * Check if the device is IDLE in regard to the DMA/compute engines 626 * and QMANs. The f/w will return a bitmask where each bit represents 627 * a different engine or QMAN according to enum cpucp_idle_mask. 628 * The bit will be 1 if the engine is NOT idle. 629 * 630 * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET - 631 * Fetch all HBM replaced-rows and prending to be replaced rows data. 632 * 633 * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS - 634 * Fetch status of HBM rows pending replacement and need a reboot to 635 * be replaced. 636 * 637 * CPUCP_PACKET_POWER_SET - 638 * Resets power history of device to 0 639 * 640 * CPUCP_PACKET_ENGINE_CORE_ASID_SET - 641 * Packet to perform engine core ASID configuration 642 * 643 * CPUCP_PACKET_SEC_ATTEST_GET - 644 * Get the attestaion data that is collected during various stages of the 645 * boot sequence. the attestation data is also hashed with some unique 646 * number (nonce) provided by the host to prevent replay attacks. 647 * public key and certificate also provided as part of the FW response. 648 * 649 * CPUCP_PACKET_MONITOR_DUMP_GET - 650 * Get monitors registers dump from the CpuCP kernel. 651 * The CPU will put the registers dump in the a buffer allocated by the driver 652 * which address is passed via the CpuCp packet. In addition, the host's driver 653 * passes the max size it allows the CpuCP to write to the structure, to prevent 654 * data corruption in case of mismatched driver/FW versions. 655 * Relevant only to Gaudi. 656 * 657 * CPUCP_PACKET_GENERIC_PASSTHROUGH - 658 * Generic opcode for all firmware info that is only passed to host 659 * through the LKD, without getting parsed there. 660 * 661 * CPUCP_PACKET_ACTIVE_STATUS_SET - 662 * LKD sends FW indication whether device is free or in use, this indication is reported 663 * also to the BMC. 664 */ 665 666 enum cpucp_packet_id { 667 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */ 668 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */ 669 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */ 670 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */ 671 CPUCP_PACKET_CURRENT_GET, /* sysfs */ 672 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */ 673 CPUCP_PACKET_PWM_GET, /* sysfs */ 674 CPUCP_PACKET_PWM_SET, /* sysfs */ 675 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */ 676 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */ 677 CPUCP_PACKET_LED_SET, /* debugfs */ 678 CPUCP_PACKET_I2C_WR, /* debugfs */ 679 CPUCP_PACKET_I2C_RD, /* debugfs */ 680 CPUCP_PACKET_INFO_GET, /* IOCTL */ 681 CPUCP_PACKET_FLASH_PROGRAM_REMOVED, 682 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */ 683 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */ 684 CPUCP_PACKET_TEST, /* internal */ 685 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */ 686 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */ 687 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */ 688 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */ 689 CPUCP_PACKET_NIC_INFO_GET, /* internal */ 690 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */ 691 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */ 692 CPUCP_PACKET_CURRENT_SET, /* sysfs */ 693 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */ 694 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */ 695 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */ 696 CPUCP_PACKET_PLL_INFO_GET, /* internal */ 697 CPUCP_PACKET_NIC_STATUS, /* internal */ 698 CPUCP_PACKET_POWER_GET, /* internal */ 699 CPUCP_PACKET_NIC_PFC_SET, /* internal */ 700 CPUCP_PACKET_NIC_FAULT_GET, /* internal */ 701 CPUCP_PACKET_NIC_LPBK_SET, /* internal */ 702 CPUCP_PACKET_NIC_MAC_CFG, /* internal */ 703 CPUCP_PACKET_MSI_INFO_SET, /* internal */ 704 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */ 705 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */ 706 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */ 707 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */ 708 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */ 709 CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */ 710 CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */ 711 CPUCP_PACKET_POWER_SET, /* internal */ 712 CPUCP_PACKET_RESERVED, /* not used */ 713 CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */ 714 CPUCP_PACKET_RESERVED2, /* not used */ 715 CPUCP_PACKET_SEC_ATTEST_GET, /* internal */ 716 CPUCP_PACKET_RESERVED3, /* not used */ 717 CPUCP_PACKET_RESERVED4, /* not used */ 718 CPUCP_PACKET_MONITOR_DUMP_GET, /* debugfs */ 719 CPUCP_PACKET_RESERVED5, /* not used */ 720 CPUCP_PACKET_RESERVED6, /* not used */ 721 CPUCP_PACKET_RESERVED7, /* not used */ 722 CPUCP_PACKET_GENERIC_PASSTHROUGH, /* IOCTL */ 723 CPUCP_PACKET_RESERVED8, /* not used */ 724 CPUCP_PACKET_ACTIVE_STATUS_SET, /* internal */ 725 CPUCP_PACKET_RESERVED9, /* not used */ 726 CPUCP_PACKET_RESERVED10, /* not used */ 727 CPUCP_PACKET_RESERVED11, /* not used */ 728 CPUCP_PACKET_ID_MAX /* must be last */ 729 }; 730 731 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5 732 733 #define CPUCP_PKT_CTL_RC_SHIFT 12 734 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000 735 736 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16 737 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000 738 739 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0 740 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull 741 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16 742 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull 743 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32 744 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull 745 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48 746 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull 747 748 #define CPUCP_PKT_RES_EEPROM_OUT0_SHIFT 0 749 #define CPUCP_PKT_RES_EEPROM_OUT0_MASK 0x000000000000FFFFull 750 #define CPUCP_PKT_RES_EEPROM_OUT1_SHIFT 16 751 #define CPUCP_PKT_RES_EEPROM_OUT1_MASK 0x0000000000FF0000ull 752 753 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0 754 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull 755 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1 756 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull 757 758 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0 759 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull 760 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1 761 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull 762 763 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0 764 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull 765 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1 766 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull 767 768 /* heartbeat status bits */ 769 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0 770 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001 771 772 struct cpucp_packet { 773 union { 774 __le64 value; /* For SET packets */ 775 __le64 result; /* For GET packets */ 776 __le64 addr; /* For PQ */ 777 }; 778 779 __le32 ctl; 780 781 __le32 fence; /* Signal to host that message is completed */ 782 783 union { 784 struct {/* For temperature/current/voltage/fan/pwm get/set */ 785 __le16 sensor_index; 786 __le16 type; 787 }; 788 789 struct { /* For I2C read/write */ 790 __u8 i2c_bus; 791 __u8 i2c_addr; 792 __u8 i2c_reg; 793 /* 794 * In legacy implemetations, i2c_len was not present, 795 * was unused and just added as pad. 796 * So if i2c_len is 0, it is treated as legacy 797 * and r/w 1 Byte, else if i2c_len is specified, 798 * its treated as new multibyte r/w support. 799 */ 800 __u8 i2c_len; 801 }; 802 803 struct {/* For PLL info fetch */ 804 __le16 pll_type; 805 /* TODO pll_reg is kept temporary before removal */ 806 __le16 pll_reg; 807 }; 808 809 /* For any general request */ 810 __le32 index; 811 812 /* For frequency get/set */ 813 __le32 pll_index; 814 815 /* For led set */ 816 __le32 led_index; 817 818 /* For get CpuCP info/EEPROM data/NIC info */ 819 __le32 data_max_size; 820 821 /* 822 * For any general status bitmask. Shall be used whenever the 823 * result cannot be used to hold general purpose data. 824 */ 825 __le32 status_mask; 826 827 /* random, used once number, for security packets */ 828 __le32 nonce; 829 }; 830 831 union { 832 /* For NIC requests */ 833 __le32 port_index; 834 835 /* For Generic packet sub index */ 836 __le32 pkt_subidx; 837 }; 838 }; 839 840 struct cpucp_unmask_irq_arr_packet { 841 struct cpucp_packet cpucp_pkt; 842 __le32 length; 843 __le32 irqs[]; 844 }; 845 846 struct cpucp_nic_status_packet { 847 struct cpucp_packet cpucp_pkt; 848 __le32 length; 849 __le32 data[]; 850 }; 851 852 struct cpucp_array_data_packet { 853 struct cpucp_packet cpucp_pkt; 854 __le32 length; 855 __le32 data[]; 856 }; 857 858 enum cpucp_led_index { 859 CPUCP_LED0_INDEX = 0, 860 CPUCP_LED1_INDEX, 861 CPUCP_LED2_INDEX 862 }; 863 864 /* 865 * enum cpucp_packet_rc - Error return code 866 * @cpucp_packet_success -> in case of success. 867 * @cpucp_packet_invalid -> this is to support Goya and Gaudi platform. 868 * @cpucp_packet_fault -> in case of processing error like failing to 869 * get device binding or semaphore etc. 870 * @cpucp_packet_invalid_pkt -> when cpucp packet is un-supported. This is 871 * supported Greco onwards. 872 * @cpucp_packet_invalid_params -> when checking parameter like length of buffer 873 * or attribute value etc. Supported Greco onwards. 874 * @cpucp_packet_rc_max -> It indicates size of enum so should be at last. 875 */ 876 enum cpucp_packet_rc { 877 cpucp_packet_success, 878 cpucp_packet_invalid, 879 cpucp_packet_fault, 880 cpucp_packet_invalid_pkt, 881 cpucp_packet_invalid_params, 882 cpucp_packet_rc_max 883 }; 884 885 /* 886 * cpucp_temp_type should adhere to hwmon_temp_attributes 887 * defined in Linux kernel hwmon.h file 888 */ 889 enum cpucp_temp_type { 890 cpucp_temp_input, 891 cpucp_temp_min = 4, 892 cpucp_temp_min_hyst, 893 cpucp_temp_max = 6, 894 cpucp_temp_max_hyst, 895 cpucp_temp_crit, 896 cpucp_temp_crit_hyst, 897 cpucp_temp_offset = 19, 898 cpucp_temp_lowest = 21, 899 cpucp_temp_highest = 22, 900 cpucp_temp_reset_history = 23, 901 cpucp_temp_warn = 24, 902 cpucp_temp_max_crit = 25, 903 cpucp_temp_max_warn = 26, 904 }; 905 906 enum cpucp_in_attributes { 907 cpucp_in_input, 908 cpucp_in_min, 909 cpucp_in_max, 910 cpucp_in_lowest = 6, 911 cpucp_in_highest = 7, 912 cpucp_in_reset_history, 913 cpucp_in_intr_alarm_a, 914 cpucp_in_intr_alarm_b, 915 }; 916 917 enum cpucp_curr_attributes { 918 cpucp_curr_input, 919 cpucp_curr_min, 920 cpucp_curr_max, 921 cpucp_curr_lowest = 6, 922 cpucp_curr_highest = 7, 923 cpucp_curr_reset_history 924 }; 925 926 enum cpucp_fan_attributes { 927 cpucp_fan_input, 928 cpucp_fan_min = 2, 929 cpucp_fan_max 930 }; 931 932 enum cpucp_pwm_attributes { 933 cpucp_pwm_input, 934 cpucp_pwm_enable 935 }; 936 937 enum cpucp_pcie_throughput_attributes { 938 cpucp_pcie_throughput_tx, 939 cpucp_pcie_throughput_rx 940 }; 941 942 /* TODO temporary kept before removal */ 943 enum cpucp_pll_reg_attributes { 944 cpucp_pll_nr_reg, 945 cpucp_pll_nf_reg, 946 cpucp_pll_od_reg, 947 cpucp_pll_div_factor_reg, 948 cpucp_pll_div_sel_reg 949 }; 950 951 /* TODO temporary kept before removal */ 952 enum cpucp_pll_type_attributes { 953 cpucp_pll_cpu, 954 cpucp_pll_pci, 955 }; 956 957 /* 958 * cpucp_power_type aligns with hwmon_power_attributes 959 * defined in Linux kernel hwmon.h file 960 */ 961 enum cpucp_power_type { 962 CPUCP_POWER_INPUT = 8, 963 CPUCP_POWER_INPUT_HIGHEST = 9, 964 CPUCP_POWER_RESET_INPUT_HISTORY = 11 965 }; 966 967 /* 968 * MSI type enumeration table for all ASICs and future SW versions. 969 * For future ASIC-LKD compatibility, we can only add new enumerations. 970 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES). 971 * Changing the order of entries or removing entries is not allowed. 972 */ 973 enum cpucp_msi_type { 974 CPUCP_EVENT_QUEUE_MSI_TYPE, 975 CPUCP_NIC_PORT1_MSI_TYPE, 976 CPUCP_NIC_PORT3_MSI_TYPE, 977 CPUCP_NIC_PORT5_MSI_TYPE, 978 CPUCP_NIC_PORT7_MSI_TYPE, 979 CPUCP_NIC_PORT9_MSI_TYPE, 980 CPUCP_NUM_OF_MSI_TYPES 981 }; 982 983 /* 984 * PLL enumeration table used for all ASICs and future SW versions. 985 * For future ASIC-LKD compatibility, we can only add new enumerations. 986 * at the end of the table. 987 * Changing the order of entries or removing entries is not allowed. 988 */ 989 enum pll_index { 990 CPU_PLL = 0, 991 PCI_PLL = 1, 992 NIC_PLL = 2, 993 DMA_PLL = 3, 994 MESH_PLL = 4, 995 MME_PLL = 5, 996 TPC_PLL = 6, 997 IF_PLL = 7, 998 SRAM_PLL = 8, 999 NS_PLL = 9, 1000 HBM_PLL = 10, 1001 MSS_PLL = 11, 1002 DDR_PLL = 12, 1003 VID_PLL = 13, 1004 BANK_PLL = 14, 1005 MMU_PLL = 15, 1006 IC_PLL = 16, 1007 MC_PLL = 17, 1008 EMMC_PLL = 18, 1009 D2D_PLL = 19, 1010 CS_PLL = 20, 1011 C2C_PLL = 21, 1012 NCH_PLL = 22, 1013 C2M_PLL = 23, 1014 PLL_MAX 1015 }; 1016 1017 enum rl_index { 1018 TPC_RL = 0, 1019 MME_RL, 1020 EDMA_RL, 1021 }; 1022 1023 enum pvt_index { 1024 PVT_SW, 1025 PVT_SE, 1026 PVT_NW, 1027 PVT_NE 1028 }; 1029 1030 /* Event Queue Packets */ 1031 1032 struct eq_generic_event { 1033 __le64 data[7]; 1034 }; 1035 1036 /* 1037 * CpuCP info 1038 */ 1039 1040 #define CARD_NAME_MAX_LEN 16 1041 #define CPUCP_MAX_SENSORS 128 1042 #define CPUCP_MAX_NICS 128 1043 #define CPUCP_LANES_PER_NIC 4 1044 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024 1045 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC) 1046 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64) 1047 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64) 1048 #define CPUCP_HBM_ROW_REPLACE_MAX 32 1049 1050 struct cpucp_sensor { 1051 __le32 type; 1052 __le32 flags; 1053 }; 1054 1055 /** 1056 * struct cpucp_card_types - ASIC card type. 1057 * @cpucp_card_type_pci: PCI card. 1058 * @cpucp_card_type_pmc: PCI Mezzanine Card. 1059 */ 1060 enum cpucp_card_types { 1061 cpucp_card_type_pci, 1062 cpucp_card_type_pmc 1063 }; 1064 1065 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0 1066 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001 1067 1068 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1 1069 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002 1070 1071 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2 1072 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004 1073 1074 /** 1075 * struct cpucp_security_info - Security information. 1076 * @config: configuration bit field 1077 * @keys_num: number of stored keys 1078 * @revoked_keys: revoked keys bit field 1079 * @min_svn: minimal security version 1080 */ 1081 struct cpucp_security_info { 1082 __u8 config; 1083 __u8 keys_num; 1084 __u8 revoked_keys; 1085 __u8 min_svn; 1086 }; 1087 1088 /** 1089 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver 1090 * @sensors: available sensors description. 1091 * @kernel_version: CpuCP linux kernel version. 1092 * @reserved: reserved field. 1093 * @card_type: card configuration type. 1094 * @card_location: in a server, each card has different connections topology 1095 * depending on its location (relevant for PMC card type) 1096 * @cpld_version: CPLD programmed F/W version. 1097 * @infineon_version: Infineon main DC-DC version. 1098 * @fuse_version: silicon production FUSE information. 1099 * @thermal_version: thermald S/W version. 1100 * @cpucp_version: CpuCP S/W version. 1101 * @infineon_second_stage_version: Infineon 2nd stage DC-DC version. 1102 * @dram_size: available DRAM size. 1103 * @card_name: card name that will be displayed in HWMON subsystem on the host 1104 * @tpc_binning_mask: TPC binning mask, 1 bit per TPC instance 1105 * (0 = functional, 1 = binned) 1106 * @decoder_binning_mask: Decoder binning mask, 1 bit per decoder instance 1107 * (0 = functional, 1 = binned), maximum 1 per dcore 1108 * @sram_binning: Categorize SRAM functionality 1109 * (0 = fully functional, 1 = lower-half is not functional, 1110 * 2 = upper-half is not functional) 1111 * @sec_info: security information 1112 * @pll_map: Bit map of supported PLLs for current ASIC version. 1113 * @mme_binning_mask: MME binning mask, 1114 * bits [0:6] <==> dcore0 mme fma 1115 * bits [7:13] <==> dcore1 mme fma 1116 * bits [14:20] <==> dcore0 mme ima 1117 * bits [21:27] <==> dcore1 mme ima 1118 * For each group, if the 6th bit is set then first 5 bits 1119 * represent the col's idx [0-31], otherwise these bits are 1120 * ignored, and col idx 32 is binned. 7th bit is don't care. 1121 * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance 1122 * (0 = functional 1 = binned) 1123 * @memory_repair_flag: eFuse flag indicating memory repair 1124 * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance 1125 * (0 = functional 1 = binned) 1126 * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance 1127 * (0 = functional 1 = binned) 1128 * @interposer_version: Interposer version programmed in eFuse 1129 * @substrate_version: Substrate version programmed in eFuse 1130 * @fw_os_version: Firmware OS Version 1131 */ 1132 struct cpucp_info { 1133 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS]; 1134 __u8 kernel_version[VERSION_MAX_LEN]; 1135 __le32 reserved; 1136 __le32 card_type; 1137 __le32 card_location; 1138 __le32 cpld_version; 1139 __le32 infineon_version; 1140 __u8 fuse_version[VERSION_MAX_LEN]; 1141 __u8 thermal_version[VERSION_MAX_LEN]; 1142 __u8 cpucp_version[VERSION_MAX_LEN]; 1143 __le32 infineon_second_stage_version; 1144 __le64 dram_size; 1145 char card_name[CARD_NAME_MAX_LEN]; 1146 __le64 tpc_binning_mask; 1147 __le64 decoder_binning_mask; 1148 __u8 sram_binning; 1149 __u8 dram_binning_mask; 1150 __u8 memory_repair_flag; 1151 __u8 edma_binning_mask; 1152 __u8 xbar_binning_mask; 1153 __u8 interposer_version; 1154 __u8 substrate_version; 1155 __u8 reserved2; 1156 struct cpucp_security_info sec_info; 1157 __le32 reserved3; 1158 __u8 pll_map[PLL_MAP_LEN]; 1159 __le64 mme_binning_mask; 1160 __u8 fw_os_version[VERSION_MAX_LEN]; 1161 }; 1162 1163 struct cpucp_mac_addr { 1164 __u8 mac_addr[ETH_ALEN]; 1165 }; 1166 1167 enum cpucp_serdes_type { 1168 TYPE_1_SERDES_TYPE, 1169 TYPE_2_SERDES_TYPE, 1170 HLS1_SERDES_TYPE, 1171 HLS1H_SERDES_TYPE, 1172 HLS2_SERDES_TYPE, 1173 HLS2_TYPE_1_SERDES_TYPE, 1174 MAX_NUM_SERDES_TYPE, /* number of types */ 1175 UNKNOWN_SERDES_TYPE = 0xFFFF /* serdes_type is u16 */ 1176 }; 1177 1178 struct cpucp_nic_info { 1179 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS]; 1180 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN]; 1181 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1182 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN]; 1183 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN]; 1184 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN]; 1185 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN]; 1186 __le16 serdes_type; /* enum cpucp_serdes_type */ 1187 __le16 tx_swap_map[CPUCP_MAX_NICS]; 1188 __u8 reserved[6]; 1189 }; 1190 1191 #define PAGE_DISCARD_MAX 64 1192 1193 struct page_discard_info { 1194 __u8 num_entries; 1195 __u8 reserved[7]; 1196 __le32 mmu_page_idx[PAGE_DISCARD_MAX]; 1197 }; 1198 1199 /* 1200 * struct frac_val - fracture value represented by "integer.frac". 1201 * @integer: the integer part of the fracture value; 1202 * @frac: the fracture part of the fracture value. 1203 */ 1204 struct frac_val { 1205 union { 1206 struct { 1207 __le16 integer; 1208 __le16 frac; 1209 }; 1210 __le32 val; 1211 }; 1212 }; 1213 1214 /* 1215 * struct ser_val - the SER (symbol error rate) value is represented by "integer * 10 ^ -exp". 1216 * @integer: the integer part of the SER value; 1217 * @exp: the exponent part of the SER value. 1218 */ 1219 struct ser_val { 1220 __le16 integer; 1221 __le16 exp; 1222 }; 1223 1224 /* 1225 * struct cpucp_nic_status - describes the status of a NIC port. 1226 * @port: NIC port index. 1227 * @bad_format_cnt: e.g. CRC. 1228 * @responder_out_of_sequence_psn_cnt: e.g NAK. 1229 * @high_ber_reinit_cnt: link reinit due to high BER. 1230 * @correctable_err_cnt: e.g. bit-flip. 1231 * @uncorrectable_err_cnt: e.g. MAC errors. 1232 * @retraining_cnt: re-training counter. 1233 * @up: is port up. 1234 * @pcs_link: has PCS link. 1235 * @phy_ready: is PHY ready. 1236 * @auto_neg: is Autoneg enabled. 1237 * @timeout_retransmission_cnt: timeout retransmission events. 1238 * @high_ber_cnt: high ber events. 1239 * @pre_fec_ser: pre FEC SER value. 1240 * @post_fec_ser: post FEC SER value. 1241 * @throughput: measured throughput. 1242 * @latency: measured latency. 1243 */ 1244 struct cpucp_nic_status { 1245 __le32 port; 1246 __le32 bad_format_cnt; 1247 __le32 responder_out_of_sequence_psn_cnt; 1248 __le32 high_ber_reinit; 1249 __le32 correctable_err_cnt; 1250 __le32 uncorrectable_err_cnt; 1251 __le32 retraining_cnt; 1252 __u8 up; 1253 __u8 pcs_link; 1254 __u8 phy_ready; 1255 __u8 auto_neg; 1256 __le32 timeout_retransmission_cnt; 1257 __le32 high_ber_cnt; 1258 struct ser_val pre_fec_ser; 1259 struct ser_val post_fec_ser; 1260 struct frac_val bandwidth; 1261 struct frac_val lat; 1262 }; 1263 1264 enum cpucp_hbm_row_replace_cause { 1265 REPLACE_CAUSE_DOUBLE_ECC_ERR, 1266 REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR, 1267 }; 1268 1269 struct cpucp_hbm_row_info { 1270 __u8 hbm_idx; 1271 __u8 pc; 1272 __u8 sid; 1273 __u8 bank_idx; 1274 __le16 row_addr; 1275 __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */ 1276 __u8 pad; 1277 }; 1278 1279 struct cpucp_hbm_row_replaced_rows_info { 1280 __le16 num_replaced_rows; 1281 __u8 pad[6]; 1282 struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX]; 1283 }; 1284 1285 enum cpu_reset_status { 1286 CPU_RST_STATUS_NA = 0, 1287 CPU_RST_STATUS_SOFT_RST_DONE = 1, 1288 }; 1289 1290 #define SEC_PCR_DATA_BUF_SZ 256 1291 #define SEC_PCR_QUOTE_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1292 #define SEC_SIGNATURE_BUF_SZ 255 /* (256 - 1) 1 byte used for size */ 1293 #define SEC_PUB_DATA_BUF_SZ 510 /* (512 - 2) 2 bytes used for size */ 1294 #define SEC_CERTIFICATE_BUF_SZ 2046 /* (2048 - 2) 2 bytes used for size */ 1295 1296 /* 1297 * struct cpucp_sec_attest_info - attestation report of the boot 1298 * @pcr_data: raw values of the PCR registers 1299 * @pcr_num_reg: number of PCR registers in the pcr_data array 1300 * @pcr_reg_len: length of each PCR register in the pcr_data array (bytes) 1301 * @nonce: number only used once. random number provided by host. this also 1302 * passed to the quote command as a qualifying data. 1303 * @pcr_quote_len: length of the attestation quote data (bytes) 1304 * @pcr_quote: attestation report data structure 1305 * @quote_sig_len: length of the attestation report signature (bytes) 1306 * @quote_sig: signature structure of the attestation report 1307 * @pub_data_len: length of the public data (bytes) 1308 * @public_data: public key for the signed attestation 1309 * (outPublic + name + qualifiedName) 1310 * @certificate_len: length of the certificate (bytes) 1311 * @certificate: certificate for the attestation signing key 1312 */ 1313 struct cpucp_sec_attest_info { 1314 __u8 pcr_data[SEC_PCR_DATA_BUF_SZ]; 1315 __u8 pcr_num_reg; 1316 __u8 pcr_reg_len; 1317 __le16 pad0; 1318 __le32 nonce; 1319 __le16 pcr_quote_len; 1320 __u8 pcr_quote[SEC_PCR_QUOTE_BUF_SZ]; 1321 __u8 quote_sig_len; 1322 __u8 quote_sig[SEC_SIGNATURE_BUF_SZ]; 1323 __le16 pub_data_len; 1324 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1325 __le16 certificate_len; 1326 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1327 }; 1328 1329 /* 1330 * struct cpucp_dev_info_signed - device information signed by a secured device 1331 * @info: device information structure as defined above 1332 * @nonce: number only used once. random number provided by host. this number is 1333 * hashed and signed along with the device information. 1334 * @info_sig_len: length of the attestation signature (bytes) 1335 * @info_sig: signature of the info + nonce data. 1336 * @pub_data_len: length of the public data (bytes) 1337 * @public_data: public key info signed info data 1338 * (outPublic + name + qualifiedName) 1339 * @certificate_len: length of the certificate (bytes) 1340 * @certificate: certificate for the signing key 1341 */ 1342 struct cpucp_dev_info_signed { 1343 struct cpucp_info info; /* assumed to be 64bit aligned */ 1344 __le32 nonce; 1345 __le32 pad0; 1346 __u8 info_sig_len; 1347 __u8 info_sig[SEC_SIGNATURE_BUF_SZ]; 1348 __le16 pub_data_len; 1349 __u8 public_data[SEC_PUB_DATA_BUF_SZ]; 1350 __le16 certificate_len; 1351 __u8 certificate[SEC_CERTIFICATE_BUF_SZ]; 1352 }; 1353 1354 #define DCORE_MON_REGS_SZ 512 1355 /* 1356 * struct dcore_monitor_regs_data - DCORE monitor regs data. 1357 * the structure follows sync manager block layout. relevant only to Gaudi. 1358 * @mon_pay_addrl: array of payload address low bits. 1359 * @mon_pay_addrh: array of payload address high bits. 1360 * @mon_pay_data: array of payload data. 1361 * @mon_arm: array of monitor arm. 1362 * @mon_status: array of monitor status. 1363 */ 1364 struct dcore_monitor_regs_data { 1365 __le32 mon_pay_addrl[DCORE_MON_REGS_SZ]; 1366 __le32 mon_pay_addrh[DCORE_MON_REGS_SZ]; 1367 __le32 mon_pay_data[DCORE_MON_REGS_SZ]; 1368 __le32 mon_arm[DCORE_MON_REGS_SZ]; 1369 __le32 mon_status[DCORE_MON_REGS_SZ]; 1370 }; 1371 1372 /* contains SM data for each SYNC_MNGR (relevant only to Gaudi) */ 1373 struct cpucp_monitor_dump { 1374 struct dcore_monitor_regs_data sync_mngr_w_s; 1375 struct dcore_monitor_regs_data sync_mngr_e_s; 1376 struct dcore_monitor_regs_data sync_mngr_w_n; 1377 struct dcore_monitor_regs_data sync_mngr_e_n; 1378 }; 1379 1380 /* 1381 * The Type of the generic request (and other input arguments) will be fetched from user by reading 1382 * from "pkt_subidx" field in struct cpucp_packet. 1383 * 1384 * HL_PASSTHROUGHT_VERSIONS - Fetch all firmware versions. 1385 */ 1386 enum hl_passthrough_type { 1387 HL_PASSTHROUGH_VERSIONS, 1388 }; 1389 1390 #endif /* CPUCP_IF_H */ 1391