1 // SPDX-License-Identifier: GPL-2.0 2 3 /* 4 * Copyright 2020-2022 HabanaLabs, Ltd. 5 * All Rights Reserved. 6 */ 7 8 #include "gaudi2P.h" 9 #include "../include/gaudi2/asic_reg/gaudi2_regs.h" 10 11 #define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32))) 12 13 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 14 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 15 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 16 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 17 #define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 18 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \ 19 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 20 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \ 21 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 22 #define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \ 23 PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 24 25 /* LBW RR */ 26 #define SFT_NUM_OF_LBW_RTR 1 27 #define SFT_LBW_RTR_OFFSET 0 28 #define RR_LBW_LONG_MASK 0x7FFFFFFull 29 #define RR_LBW_SHORT_MASK 0x7FFF000ull 30 31 /* HBW RR */ 32 #define SFT_NUM_OF_HBW_RTR 2 33 #define RR_HBW_SHORT_LO_MASK 0xFFFFFFFF000ull 34 #define RR_HBW_SHORT_HI_MASK 0xF00000000000ull 35 #define RR_HBW_LONG_LO_MASK 0xFFFFFFFF000ull 36 #define RR_HBW_LONG_HI_MASK 0xFFFFF00000000000ull 37 38 struct rr_config { 39 u64 min; 40 u64 max; 41 u32 index; 42 u8 type; 43 }; 44 45 struct gaudi2_atypical_bp_blocks { 46 u32 mm_block_base_addr; 47 u32 block_size; 48 u32 glbl_sec_offset; 49 u32 glbl_sec_length; 50 }; 51 52 static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = { 53 mmDCORE0_SYNC_MNGR_OBJS_BASE, 54 128 * 1024, 55 SM_OBJS_PROT_BITS_OFFS, 56 640 57 }; 58 59 static const u32 gaudi2_pb_sft0[] = { 60 mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE, 61 mmSFT0_HBW_RTR_IF0_RTR_H3_BASE, 62 mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE, 63 mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE, 64 mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE, 65 mmSFT0_HBW_RTR_IF1_RTR_H3_BASE, 66 mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE, 67 mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE, 68 mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE, 69 mmSFT0_LBW_RTR_IF_RTR_H3_BASE, 70 mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE, 71 mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE, 72 mmSFT0_BASE, 73 }; 74 75 static const u32 gaudi2_pb_dcr0_hif[] = { 76 mmDCORE0_HIF0_BASE, 77 }; 78 79 static const u32 gaudi2_pb_dcr0_rtr0[] = { 80 mmDCORE0_RTR0_CTRL_BASE, 81 mmDCORE0_RTR0_H3_BASE, 82 mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE, 83 mmDCORE0_RTR0_ADD_DEC_HBW_BASE, 84 mmDCORE0_RTR0_BASE, 85 mmDCORE0_RTR0_DBG_ADDR_BASE, 86 }; 87 88 static const u32 gaudi2_pb_dcr0_hmmu0[] = { 89 mmDCORE0_HMMU0_MMU_BASE, 90 mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE, 91 mmDCORE0_HMMU0_SCRAMB_OUT_BASE, 92 mmDCORE0_HMMU0_STLB_BASE, 93 }; 94 95 static const u32 gaudi2_pb_cpu_if[] = { 96 mmCPU_IF_BASE, 97 }; 98 99 static const u32 gaudi2_pb_cpu[] = { 100 mmCPU_CA53_CFG_BASE, 101 mmCPU_MSTR_IF_RR_SHRD_HBW_BASE, 102 }; 103 104 static const u32 gaudi2_pb_kdma[] = { 105 mmARC_FARM_KDMA_BASE, 106 mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE, 107 }; 108 109 static const u32 gaudi2_pb_pdma0[] = { 110 mmPDMA0_CORE_BASE, 111 mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE, 112 mmPDMA0_QM_BASE, 113 }; 114 115 static const u32 gaudi2_pb_pdma0_arc[] = { 116 mmPDMA0_QM_ARC_AUX_BASE, 117 }; 118 119 static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = { 120 {mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK}, 121 {mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT}, 122 {mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7}, 123 {mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, 124 {mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, 125 {mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, 126 {mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, 127 {mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, 128 {mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, 129 }; 130 131 static const u32 gaudi2_pb_pdma0_unsecured_regs[] = { 132 mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION, 133 mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI, 134 mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO, 135 mmPDMA0_CORE_CTX_WR_COMP_WDATA, 136 mmPDMA0_CORE_CTX_SRC_BASE_LO, 137 mmPDMA0_CORE_CTX_SRC_BASE_HI, 138 mmPDMA0_CORE_CTX_DST_BASE_LO, 139 mmPDMA0_CORE_CTX_DST_BASE_HI, 140 mmPDMA0_CORE_CTX_SRC_TSIZE_0, 141 mmPDMA0_CORE_CTX_SRC_TSIZE_1, 142 mmPDMA0_CORE_CTX_SRC_TSIZE_2, 143 mmPDMA0_CORE_CTX_SRC_TSIZE_3, 144 mmPDMA0_CORE_CTX_SRC_TSIZE_4, 145 mmPDMA0_CORE_CTX_SRC_STRIDE_1, 146 mmPDMA0_CORE_CTX_SRC_STRIDE_2, 147 mmPDMA0_CORE_CTX_SRC_STRIDE_3, 148 mmPDMA0_CORE_CTX_SRC_STRIDE_4, 149 mmPDMA0_CORE_CTX_SRC_OFFSET_LO, 150 mmPDMA0_CORE_CTX_SRC_OFFSET_HI, 151 mmPDMA0_CORE_CTX_DST_TSIZE_0, 152 mmPDMA0_CORE_CTX_DST_TSIZE_1, 153 mmPDMA0_CORE_CTX_DST_TSIZE_2, 154 mmPDMA0_CORE_CTX_DST_TSIZE_3, 155 mmPDMA0_CORE_CTX_DST_TSIZE_4, 156 mmPDMA0_CORE_CTX_DST_STRIDE_1, 157 mmPDMA0_CORE_CTX_DST_STRIDE_2, 158 mmPDMA0_CORE_CTX_DST_STRIDE_3, 159 mmPDMA0_CORE_CTX_DST_STRIDE_4, 160 mmPDMA0_CORE_CTX_DST_OFFSET_LO, 161 mmPDMA0_CORE_CTX_DST_OFFSET_HI, 162 mmPDMA0_CORE_CTX_COMMIT, 163 mmPDMA0_CORE_CTX_CTRL, 164 mmPDMA0_CORE_CTX_TE_NUMROWS, 165 mmPDMA0_CORE_CTX_IDX, 166 mmPDMA0_CORE_CTX_IDX_INC, 167 mmPDMA0_QM_CQ_CFG0_0, 168 mmPDMA0_QM_CQ_CFG0_1, 169 mmPDMA0_QM_CQ_CFG0_2, 170 mmPDMA0_QM_CQ_CFG0_3, 171 mmPDMA0_QM_CQ_CFG0_4, 172 mmPDMA0_QM_CP_FENCE0_RDATA_0, 173 mmPDMA0_QM_CP_FENCE0_RDATA_1, 174 mmPDMA0_QM_CP_FENCE0_RDATA_2, 175 mmPDMA0_QM_CP_FENCE0_RDATA_3, 176 mmPDMA0_QM_CP_FENCE0_RDATA_4, 177 mmPDMA0_QM_CP_FENCE1_RDATA_0, 178 mmPDMA0_QM_CP_FENCE1_RDATA_1, 179 mmPDMA0_QM_CP_FENCE1_RDATA_2, 180 mmPDMA0_QM_CP_FENCE1_RDATA_3, 181 mmPDMA0_QM_CP_FENCE1_RDATA_4, 182 mmPDMA0_QM_CP_FENCE2_RDATA_0, 183 mmPDMA0_QM_CP_FENCE2_RDATA_1, 184 mmPDMA0_QM_CP_FENCE2_RDATA_2, 185 mmPDMA0_QM_CP_FENCE2_RDATA_3, 186 mmPDMA0_QM_CP_FENCE2_RDATA_4, 187 mmPDMA0_QM_CP_FENCE3_RDATA_0, 188 mmPDMA0_QM_CP_FENCE3_RDATA_1, 189 mmPDMA0_QM_CP_FENCE3_RDATA_2, 190 mmPDMA0_QM_CP_FENCE3_RDATA_3, 191 mmPDMA0_QM_CP_FENCE3_RDATA_4, 192 mmPDMA0_QM_CP_FENCE0_CNT_0, 193 mmPDMA0_QM_CP_FENCE0_CNT_1, 194 mmPDMA0_QM_CP_FENCE0_CNT_2, 195 mmPDMA0_QM_CP_FENCE0_CNT_3, 196 mmPDMA0_QM_CP_FENCE0_CNT_4, 197 mmPDMA0_QM_CP_FENCE1_CNT_0, 198 mmPDMA0_QM_CP_FENCE1_CNT_1, 199 mmPDMA0_QM_CP_FENCE1_CNT_2, 200 mmPDMA0_QM_CP_FENCE1_CNT_3, 201 mmPDMA0_QM_CP_FENCE1_CNT_4, 202 mmPDMA0_QM_CP_FENCE2_CNT_0, 203 mmPDMA0_QM_CP_FENCE2_CNT_1, 204 mmPDMA0_QM_CP_FENCE2_CNT_2, 205 mmPDMA0_QM_CP_FENCE2_CNT_3, 206 mmPDMA0_QM_CP_FENCE2_CNT_4, 207 mmPDMA0_QM_CP_FENCE3_CNT_0, 208 mmPDMA0_QM_CP_FENCE3_CNT_1, 209 mmPDMA0_QM_CP_FENCE3_CNT_2, 210 mmPDMA0_QM_CP_FENCE3_CNT_3, 211 mmPDMA0_QM_CP_FENCE3_CNT_4, 212 mmPDMA0_QM_CQ_PTR_LO_0, 213 mmPDMA0_QM_CQ_PTR_HI_0, 214 mmPDMA0_QM_CQ_TSIZE_0, 215 mmPDMA0_QM_CQ_CTL_0, 216 mmPDMA0_QM_CQ_PTR_LO_1, 217 mmPDMA0_QM_CQ_PTR_HI_1, 218 mmPDMA0_QM_CQ_TSIZE_1, 219 mmPDMA0_QM_CQ_CTL_1, 220 mmPDMA0_QM_CQ_PTR_LO_2, 221 mmPDMA0_QM_CQ_PTR_HI_2, 222 mmPDMA0_QM_CQ_TSIZE_2, 223 mmPDMA0_QM_CQ_CTL_2, 224 mmPDMA0_QM_CQ_PTR_LO_3, 225 mmPDMA0_QM_CQ_PTR_HI_3, 226 mmPDMA0_QM_CQ_TSIZE_3, 227 mmPDMA0_QM_CQ_CTL_3, 228 mmPDMA0_QM_CQ_PTR_LO_4, 229 mmPDMA0_QM_CQ_PTR_HI_4, 230 mmPDMA0_QM_CQ_TSIZE_4, 231 mmPDMA0_QM_CQ_CTL_4, 232 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE, 233 mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, 234 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE, 235 mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, 236 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE, 237 mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, 238 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE, 239 mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, 240 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE, 241 mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, 242 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE, 243 mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, 244 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE, 245 mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, 246 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE, 247 mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, 248 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE, 249 mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, 250 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE, 251 mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, 252 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE, 253 mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, 254 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE, 255 mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, 256 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE, 257 mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, 258 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE, 259 mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, 260 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE, 261 mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, 262 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE, 263 mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, 264 mmPDMA0_QM_ARC_CQ_PTR_LO, 265 mmPDMA0_QM_ARC_CQ_PTR_LO_STS, 266 mmPDMA0_QM_ARC_CQ_PTR_HI, 267 mmPDMA0_QM_ARC_CQ_PTR_HI_STS, 268 mmPDMA0_QM_ARB_CFG_0, 269 mmPDMA0_QM_ARB_MST_QUIET_PER, 270 mmPDMA0_QM_ARB_CHOICE_Q_PUSH, 271 mmPDMA0_QM_ARB_WRR_WEIGHT_0, 272 mmPDMA0_QM_ARB_WRR_WEIGHT_1, 273 mmPDMA0_QM_ARB_WRR_WEIGHT_2, 274 mmPDMA0_QM_ARB_WRR_WEIGHT_3, 275 mmPDMA0_QM_ARB_BASE_LO, 276 mmPDMA0_QM_ARB_BASE_HI, 277 mmPDMA0_QM_ARB_MST_SLAVE_EN, 278 mmPDMA0_QM_ARB_MST_SLAVE_EN_1, 279 mmPDMA0_QM_ARB_MST_CRED_INC, 280 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0, 281 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1, 282 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2, 283 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3, 284 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4, 285 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5, 286 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6, 287 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7, 288 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8, 289 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9, 290 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10, 291 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11, 292 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12, 293 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13, 294 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14, 295 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15, 296 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16, 297 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17, 298 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18, 299 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19, 300 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20, 301 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21, 302 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22, 303 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23, 304 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24, 305 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25, 306 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26, 307 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27, 308 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28, 309 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29, 310 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30, 311 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31, 312 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32, 313 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33, 314 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34, 315 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35, 316 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36, 317 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37, 318 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38, 319 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39, 320 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40, 321 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41, 322 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42, 323 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43, 324 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44, 325 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45, 326 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46, 327 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47, 328 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48, 329 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49, 330 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50, 331 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51, 332 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52, 333 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53, 334 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54, 335 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55, 336 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56, 337 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57, 338 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58, 339 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59, 340 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60, 341 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61, 342 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62, 343 mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63, 344 mmPDMA0_QM_ARB_SLV_ID, 345 mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST, 346 mmPDMA0_QM_ARC_CQ_CFG0, 347 mmPDMA0_QM_CQ_IFIFO_CI_0, 348 mmPDMA0_QM_CQ_IFIFO_CI_1, 349 mmPDMA0_QM_CQ_IFIFO_CI_2, 350 mmPDMA0_QM_CQ_IFIFO_CI_3, 351 mmPDMA0_QM_CQ_IFIFO_CI_4, 352 mmPDMA0_QM_ARC_CQ_IFIFO_CI, 353 mmPDMA0_QM_CQ_CTL_CI_0, 354 mmPDMA0_QM_CQ_CTL_CI_1, 355 mmPDMA0_QM_CQ_CTL_CI_2, 356 mmPDMA0_QM_CQ_CTL_CI_3, 357 mmPDMA0_QM_CQ_CTL_CI_4, 358 mmPDMA0_QM_ARC_CQ_CTL_CI, 359 mmPDMA0_QM_ARC_CQ_TSIZE, 360 mmPDMA0_QM_ARC_CQ_CTL, 361 mmPDMA0_QM_CP_SWITCH_WD_SET, 362 mmPDMA0_QM_CP_EXT_SWITCH, 363 mmPDMA0_QM_CP_PRED_0, 364 mmPDMA0_QM_CP_PRED_1, 365 mmPDMA0_QM_CP_PRED_2, 366 mmPDMA0_QM_CP_PRED_3, 367 mmPDMA0_QM_CP_PRED_4, 368 mmPDMA0_QM_CP_PRED_UPEN_0, 369 mmPDMA0_QM_CP_PRED_UPEN_1, 370 mmPDMA0_QM_CP_PRED_UPEN_2, 371 mmPDMA0_QM_CP_PRED_UPEN_3, 372 mmPDMA0_QM_CP_PRED_UPEN_4, 373 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0, 374 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1, 375 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2, 376 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3, 377 mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4, 378 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0, 379 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1, 380 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2, 381 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3, 382 mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4, 383 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0, 384 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1, 385 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2, 386 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3, 387 mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4, 388 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0, 389 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1, 390 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2, 391 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3, 392 mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4, 393 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0, 394 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1, 395 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2, 396 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3, 397 mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4, 398 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0, 399 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1, 400 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2, 401 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3, 402 mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4, 403 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0, 404 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1, 405 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2, 406 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3, 407 mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4, 408 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0, 409 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1, 410 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2, 411 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3, 412 mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4, 413 mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, 414 mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO, 415 mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO, 416 mmPDMA0_QM_CQ_CTL_MSG_BASE_LO 417 }; 418 419 static const u32 gaudi2_pb_dcr0_edma0[] = { 420 mmDCORE0_EDMA0_CORE_BASE, 421 mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE, 422 mmDCORE0_EDMA0_QM_BASE, 423 }; 424 425 static const u32 gaudi2_pb_dcr0_edma0_arc[] = { 426 mmDCORE0_EDMA0_QM_ARC_AUX_BASE, 427 }; 428 429 static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = { 430 {mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK}, 431 {mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT}, 432 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7}, 433 {mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, 434 {mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, 435 mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, 436 {mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, 437 mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, 438 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, 439 mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, 440 {mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, 441 mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, 442 {mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, 443 mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, 444 }; 445 446 static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = { 447 mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION, 448 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI, 449 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO, 450 mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA, 451 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO, 452 mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI, 453 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO, 454 mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI, 455 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0, 456 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1, 457 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2, 458 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3, 459 mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4, 460 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1, 461 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2, 462 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3, 463 mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4, 464 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO, 465 mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI, 466 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0, 467 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1, 468 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2, 469 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3, 470 mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4, 471 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1, 472 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2, 473 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3, 474 mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4, 475 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO, 476 mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI, 477 mmDCORE0_EDMA0_CORE_CTX_COMMIT, 478 mmDCORE0_EDMA0_CORE_CTX_CTRL, 479 mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS, 480 mmDCORE0_EDMA0_CORE_CTX_IDX, 481 mmDCORE0_EDMA0_CORE_CTX_IDX_INC, 482 mmDCORE0_EDMA0_QM_CQ_CFG0_0, 483 mmDCORE0_EDMA0_QM_CQ_CFG0_1, 484 mmDCORE0_EDMA0_QM_CQ_CFG0_2, 485 mmDCORE0_EDMA0_QM_CQ_CFG0_3, 486 mmDCORE0_EDMA0_QM_CQ_CFG0_4, 487 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0, 488 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1, 489 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2, 490 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3, 491 mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4, 492 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0, 493 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1, 494 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2, 495 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3, 496 mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4, 497 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0, 498 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1, 499 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2, 500 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3, 501 mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4, 502 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0, 503 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1, 504 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2, 505 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3, 506 mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4, 507 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0, 508 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1, 509 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2, 510 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3, 511 mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4, 512 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0, 513 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1, 514 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2, 515 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3, 516 mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4, 517 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0, 518 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1, 519 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2, 520 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3, 521 mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4, 522 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0, 523 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1, 524 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2, 525 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3, 526 mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4, 527 mmDCORE0_EDMA0_QM_CQ_PTR_LO_0, 528 mmDCORE0_EDMA0_QM_CQ_PTR_HI_0, 529 mmDCORE0_EDMA0_QM_CQ_TSIZE_0, 530 mmDCORE0_EDMA0_QM_CQ_CTL_0, 531 mmDCORE0_EDMA0_QM_CQ_PTR_LO_1, 532 mmDCORE0_EDMA0_QM_CQ_PTR_HI_1, 533 mmDCORE0_EDMA0_QM_CQ_TSIZE_1, 534 mmDCORE0_EDMA0_QM_CQ_CTL_1, 535 mmDCORE0_EDMA0_QM_CQ_PTR_LO_2, 536 mmDCORE0_EDMA0_QM_CQ_PTR_HI_2, 537 mmDCORE0_EDMA0_QM_CQ_TSIZE_2, 538 mmDCORE0_EDMA0_QM_CQ_CTL_2, 539 mmDCORE0_EDMA0_QM_CQ_PTR_LO_3, 540 mmDCORE0_EDMA0_QM_CQ_PTR_HI_3, 541 mmDCORE0_EDMA0_QM_CQ_TSIZE_3, 542 mmDCORE0_EDMA0_QM_CQ_CTL_3, 543 mmDCORE0_EDMA0_QM_CQ_PTR_LO_4, 544 mmDCORE0_EDMA0_QM_CQ_PTR_HI_4, 545 mmDCORE0_EDMA0_QM_CQ_TSIZE_4, 546 mmDCORE0_EDMA0_QM_CQ_CTL_4, 547 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE, 548 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, 549 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE, 550 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, 551 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE, 552 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, 553 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE, 554 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, 555 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE, 556 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, 557 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE, 558 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, 559 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE, 560 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, 561 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE, 562 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, 563 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE, 564 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, 565 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE, 566 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, 567 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE, 568 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, 569 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE, 570 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, 571 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE, 572 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, 573 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE, 574 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, 575 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE, 576 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, 577 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE, 578 mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, 579 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO, 580 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS, 581 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI, 582 mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS, 583 mmDCORE0_EDMA0_QM_ARB_CFG_0, 584 mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER, 585 mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH, 586 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0, 587 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1, 588 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2, 589 mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3, 590 mmDCORE0_EDMA0_QM_ARB_BASE_LO, 591 mmDCORE0_EDMA0_QM_ARB_BASE_HI, 592 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN, 593 mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1, 594 mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC, 595 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0, 596 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1, 597 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2, 598 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3, 599 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4, 600 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5, 601 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6, 602 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7, 603 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8, 604 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9, 605 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10, 606 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11, 607 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12, 608 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13, 609 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14, 610 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15, 611 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16, 612 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17, 613 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18, 614 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19, 615 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20, 616 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21, 617 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22, 618 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23, 619 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24, 620 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25, 621 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26, 622 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27, 623 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28, 624 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29, 625 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30, 626 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31, 627 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32, 628 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33, 629 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34, 630 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35, 631 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36, 632 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37, 633 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38, 634 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39, 635 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40, 636 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41, 637 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42, 638 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43, 639 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44, 640 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45, 641 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46, 642 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47, 643 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48, 644 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49, 645 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50, 646 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51, 647 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52, 648 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53, 649 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54, 650 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55, 651 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56, 652 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57, 653 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58, 654 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59, 655 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60, 656 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61, 657 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62, 658 mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63, 659 mmDCORE0_EDMA0_QM_ARB_SLV_ID, 660 mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST, 661 mmDCORE0_EDMA0_QM_ARC_CQ_CFG0, 662 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0, 663 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1, 664 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2, 665 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3, 666 mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4, 667 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI, 668 mmDCORE0_EDMA0_QM_CQ_CTL_CI_0, 669 mmDCORE0_EDMA0_QM_CQ_CTL_CI_1, 670 mmDCORE0_EDMA0_QM_CQ_CTL_CI_2, 671 mmDCORE0_EDMA0_QM_CQ_CTL_CI_3, 672 mmDCORE0_EDMA0_QM_CQ_CTL_CI_4, 673 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI, 674 mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE, 675 mmDCORE0_EDMA0_QM_ARC_CQ_CTL, 676 mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET, 677 mmDCORE0_EDMA0_QM_CP_EXT_SWITCH, 678 mmDCORE0_EDMA0_QM_CP_PRED_0, 679 mmDCORE0_EDMA0_QM_CP_PRED_1, 680 mmDCORE0_EDMA0_QM_CP_PRED_2, 681 mmDCORE0_EDMA0_QM_CP_PRED_3, 682 mmDCORE0_EDMA0_QM_CP_PRED_4, 683 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0, 684 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1, 685 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2, 686 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3, 687 mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4, 688 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0, 689 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1, 690 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2, 691 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3, 692 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4, 693 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0, 694 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1, 695 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2, 696 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3, 697 mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4, 698 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0, 699 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1, 700 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2, 701 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3, 702 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4, 703 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0, 704 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1, 705 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2, 706 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3, 707 mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4, 708 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0, 709 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1, 710 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2, 711 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3, 712 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4, 713 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0, 714 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1, 715 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2, 716 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3, 717 mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4, 718 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0, 719 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1, 720 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2, 721 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3, 722 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4, 723 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0, 724 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1, 725 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2, 726 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3, 727 mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4, 728 mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, 729 mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO, 730 mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO, 731 mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO 732 }; 733 734 static const u32 gaudi2_pb_dcr0_mme_sbte[] = { 735 mmDCORE0_MME_SBTE0_BASE, 736 mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE, 737 }; 738 739 static const u32 gaudi2_pb_dcr0_mme_qm[] = { 740 mmDCORE0_MME_QM_BASE, 741 }; 742 743 static const u32 gaudi2_pb_dcr0_mme_eng[] = { 744 mmDCORE0_MME_ACC_BASE, 745 mmDCORE0_MME_CTRL_HI_BASE, 746 mmDCORE0_MME_CTRL_LO_BASE, 747 mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE, 748 mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE, 749 mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE, 750 }; 751 752 static const u32 gaudi2_pb_dcr0_mme_arc[] = { 753 mmDCORE0_MME_QM_ARC_AUX_BASE, 754 mmDCORE0_MME_QM_ARC_DUP_ENG_BASE, 755 }; 756 757 static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = { 758 {mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK}, 759 {mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT}, 760 {mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7}, 761 {mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, 762 {mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, 763 {mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, 764 {mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, 765 mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, 766 {mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, 767 mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, 768 {mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, 769 mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, 770 {mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0, 771 mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63}, 772 {mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER, 773 mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD}, 774 }; 775 776 static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = { 777 mmDCORE0_MME_QM_CQ_CFG0_0, 778 mmDCORE0_MME_QM_CQ_CFG0_1, 779 mmDCORE0_MME_QM_CQ_CFG0_2, 780 mmDCORE0_MME_QM_CQ_CFG0_3, 781 mmDCORE0_MME_QM_CQ_CFG0_4, 782 mmDCORE0_MME_QM_CP_FENCE0_RDATA_0, 783 mmDCORE0_MME_QM_CP_FENCE0_RDATA_1, 784 mmDCORE0_MME_QM_CP_FENCE0_RDATA_2, 785 mmDCORE0_MME_QM_CP_FENCE0_RDATA_3, 786 mmDCORE0_MME_QM_CP_FENCE0_RDATA_4, 787 mmDCORE0_MME_QM_CP_FENCE1_RDATA_0, 788 mmDCORE0_MME_QM_CP_FENCE1_RDATA_1, 789 mmDCORE0_MME_QM_CP_FENCE1_RDATA_2, 790 mmDCORE0_MME_QM_CP_FENCE1_RDATA_3, 791 mmDCORE0_MME_QM_CP_FENCE1_RDATA_4, 792 mmDCORE0_MME_QM_CP_FENCE2_RDATA_0, 793 mmDCORE0_MME_QM_CP_FENCE2_RDATA_1, 794 mmDCORE0_MME_QM_CP_FENCE2_RDATA_2, 795 mmDCORE0_MME_QM_CP_FENCE2_RDATA_3, 796 mmDCORE0_MME_QM_CP_FENCE2_RDATA_4, 797 mmDCORE0_MME_QM_CP_FENCE3_RDATA_0, 798 mmDCORE0_MME_QM_CP_FENCE3_RDATA_1, 799 mmDCORE0_MME_QM_CP_FENCE3_RDATA_2, 800 mmDCORE0_MME_QM_CP_FENCE3_RDATA_3, 801 mmDCORE0_MME_QM_CP_FENCE3_RDATA_4, 802 mmDCORE0_MME_QM_CP_FENCE0_CNT_0, 803 mmDCORE0_MME_QM_CP_FENCE0_CNT_1, 804 mmDCORE0_MME_QM_CP_FENCE0_CNT_2, 805 mmDCORE0_MME_QM_CP_FENCE0_CNT_3, 806 mmDCORE0_MME_QM_CP_FENCE0_CNT_4, 807 mmDCORE0_MME_QM_CP_FENCE1_CNT_0, 808 mmDCORE0_MME_QM_CP_FENCE1_CNT_1, 809 mmDCORE0_MME_QM_CP_FENCE1_CNT_2, 810 mmDCORE0_MME_QM_CP_FENCE1_CNT_3, 811 mmDCORE0_MME_QM_CP_FENCE1_CNT_4, 812 mmDCORE0_MME_QM_CP_FENCE2_CNT_0, 813 mmDCORE0_MME_QM_CP_FENCE2_CNT_1, 814 mmDCORE0_MME_QM_CP_FENCE2_CNT_2, 815 mmDCORE0_MME_QM_CP_FENCE2_CNT_3, 816 mmDCORE0_MME_QM_CP_FENCE2_CNT_4, 817 mmDCORE0_MME_QM_CP_FENCE3_CNT_0, 818 mmDCORE0_MME_QM_CP_FENCE3_CNT_1, 819 mmDCORE0_MME_QM_CP_FENCE3_CNT_2, 820 mmDCORE0_MME_QM_CP_FENCE3_CNT_3, 821 mmDCORE0_MME_QM_CP_FENCE3_CNT_4, 822 mmDCORE0_MME_QM_CQ_PTR_LO_0, 823 mmDCORE0_MME_QM_CQ_PTR_HI_0, 824 mmDCORE0_MME_QM_CQ_TSIZE_0, 825 mmDCORE0_MME_QM_CQ_CTL_0, 826 mmDCORE0_MME_QM_CQ_PTR_LO_1, 827 mmDCORE0_MME_QM_CQ_PTR_HI_1, 828 mmDCORE0_MME_QM_CQ_TSIZE_1, 829 mmDCORE0_MME_QM_CQ_CTL_1, 830 mmDCORE0_MME_QM_CQ_PTR_LO_2, 831 mmDCORE0_MME_QM_CQ_PTR_HI_2, 832 mmDCORE0_MME_QM_CQ_TSIZE_2, 833 mmDCORE0_MME_QM_CQ_CTL_2, 834 mmDCORE0_MME_QM_CQ_PTR_LO_3, 835 mmDCORE0_MME_QM_CQ_PTR_HI_3, 836 mmDCORE0_MME_QM_CQ_TSIZE_3, 837 mmDCORE0_MME_QM_CQ_CTL_3, 838 mmDCORE0_MME_QM_CQ_PTR_LO_4, 839 mmDCORE0_MME_QM_CQ_PTR_HI_4, 840 mmDCORE0_MME_QM_CQ_TSIZE_4, 841 mmDCORE0_MME_QM_CQ_CTL_4, 842 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE, 843 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, 844 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE, 845 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, 846 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE, 847 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, 848 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE, 849 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, 850 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE, 851 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, 852 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE, 853 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, 854 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE, 855 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, 856 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE, 857 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, 858 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE, 859 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, 860 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE, 861 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, 862 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE, 863 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, 864 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE, 865 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, 866 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE, 867 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, 868 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE, 869 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, 870 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE, 871 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, 872 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE, 873 mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, 874 mmDCORE0_MME_QM_ARC_CQ_PTR_LO, 875 mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS, 876 mmDCORE0_MME_QM_ARC_CQ_PTR_HI, 877 mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS, 878 mmDCORE0_MME_QM_ARB_CFG_0, 879 mmDCORE0_MME_QM_ARB_MST_QUIET_PER, 880 mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH, 881 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0, 882 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1, 883 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2, 884 mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3, 885 mmDCORE0_MME_QM_ARB_BASE_LO, 886 mmDCORE0_MME_QM_ARB_BASE_HI, 887 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN, 888 mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1, 889 mmDCORE0_MME_QM_ARB_MST_CRED_INC, 890 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0, 891 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1, 892 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2, 893 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3, 894 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4, 895 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5, 896 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6, 897 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7, 898 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8, 899 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9, 900 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10, 901 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11, 902 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12, 903 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13, 904 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14, 905 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15, 906 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16, 907 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17, 908 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18, 909 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19, 910 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20, 911 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21, 912 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22, 913 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23, 914 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24, 915 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25, 916 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26, 917 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27, 918 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28, 919 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29, 920 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30, 921 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31, 922 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32, 923 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33, 924 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34, 925 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35, 926 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36, 927 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37, 928 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38, 929 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39, 930 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40, 931 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41, 932 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42, 933 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43, 934 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44, 935 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45, 936 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46, 937 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47, 938 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48, 939 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49, 940 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50, 941 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51, 942 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52, 943 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53, 944 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54, 945 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55, 946 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56, 947 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57, 948 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58, 949 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59, 950 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60, 951 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61, 952 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62, 953 mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63, 954 mmDCORE0_MME_QM_ARB_SLV_ID, 955 mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST, 956 mmDCORE0_MME_QM_ARC_CQ_CFG0, 957 mmDCORE0_MME_QM_CQ_IFIFO_CI_0, 958 mmDCORE0_MME_QM_CQ_IFIFO_CI_1, 959 mmDCORE0_MME_QM_CQ_IFIFO_CI_2, 960 mmDCORE0_MME_QM_CQ_IFIFO_CI_3, 961 mmDCORE0_MME_QM_CQ_IFIFO_CI_4, 962 mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI, 963 mmDCORE0_MME_QM_CQ_CTL_CI_0, 964 mmDCORE0_MME_QM_CQ_CTL_CI_1, 965 mmDCORE0_MME_QM_CQ_CTL_CI_2, 966 mmDCORE0_MME_QM_CQ_CTL_CI_3, 967 mmDCORE0_MME_QM_CQ_CTL_CI_4, 968 mmDCORE0_MME_QM_ARC_CQ_CTL_CI, 969 mmDCORE0_MME_QM_ARC_CQ_TSIZE, 970 mmDCORE0_MME_QM_ARC_CQ_CTL, 971 mmDCORE0_MME_QM_CP_SWITCH_WD_SET, 972 mmDCORE0_MME_QM_CP_EXT_SWITCH, 973 mmDCORE0_MME_QM_CP_PRED_0, 974 mmDCORE0_MME_QM_CP_PRED_1, 975 mmDCORE0_MME_QM_CP_PRED_2, 976 mmDCORE0_MME_QM_CP_PRED_3, 977 mmDCORE0_MME_QM_CP_PRED_4, 978 mmDCORE0_MME_QM_CP_PRED_UPEN_0, 979 mmDCORE0_MME_QM_CP_PRED_UPEN_1, 980 mmDCORE0_MME_QM_CP_PRED_UPEN_2, 981 mmDCORE0_MME_QM_CP_PRED_UPEN_3, 982 mmDCORE0_MME_QM_CP_PRED_UPEN_4, 983 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0, 984 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1, 985 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2, 986 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3, 987 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4, 988 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0, 989 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1, 990 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2, 991 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3, 992 mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4, 993 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0, 994 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1, 995 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2, 996 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3, 997 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4, 998 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0, 999 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1, 1000 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2, 1001 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3, 1002 mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4, 1003 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0, 1004 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1, 1005 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2, 1006 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3, 1007 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4, 1008 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0, 1009 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1, 1010 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2, 1011 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3, 1012 mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4, 1013 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0, 1014 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1, 1015 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2, 1016 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3, 1017 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4, 1018 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0, 1019 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1, 1020 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2, 1021 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3, 1022 mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4, 1023 mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO, 1024 mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO, 1025 mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO, 1026 mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO 1027 }; 1028 1029 static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = { 1030 mmDCORE0_MME_CTRL_LO_CMD, 1031 mmDCORE0_MME_CTRL_LO_AGU, 1032 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0, 1033 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1, 1034 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2, 1035 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3, 1036 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4, 1037 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0, 1038 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1, 1039 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2, 1040 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3, 1041 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4, 1042 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW, 1043 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH, 1044 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW, 1045 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH, 1046 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER, 1047 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE, 1048 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1, 1049 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW, 1050 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH, 1051 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP, 1052 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1, 1053 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT, 1054 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS, 1055 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER, 1056 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA, 1057 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN, 1058 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT, 1059 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU, 1060 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR, 1061 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR, 1062 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP, 1063 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER, 1064 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER, 1065 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER, 1066 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER, 1067 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE, 1068 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE, 1069 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE, 1070 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE, 1071 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID, 1072 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0, 1073 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1, 1074 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2, 1075 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3, 1076 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4, 1077 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0, 1078 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1, 1079 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2, 1080 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3, 1081 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4, 1082 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0, 1083 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1, 1084 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2, 1085 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3, 1086 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4, 1087 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0, 1088 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1, 1089 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2, 1090 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3, 1091 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4, 1092 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0, 1093 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1, 1094 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2, 1095 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3, 1096 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4, 1097 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0, 1098 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1, 1099 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2, 1100 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3, 1101 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4, 1102 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0, 1103 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1, 1104 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2, 1105 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3, 1106 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4, 1107 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0, 1108 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1, 1109 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2, 1110 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3, 1111 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4, 1112 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0, 1113 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1, 1114 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2, 1115 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3, 1116 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0, 1117 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1, 1118 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2, 1119 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3, 1120 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0, 1121 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1, 1122 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2, 1123 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3, 1124 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0, 1125 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1, 1126 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2, 1127 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3, 1128 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4, 1129 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW, 1130 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH, 1131 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW, 1132 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH, 1133 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW, 1134 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH, 1135 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW, 1136 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH, 1137 mmDCORE0_MME_CTRL_LO_ARCH_STATUS, 1138 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0, 1139 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0, 1140 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0, 1141 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1, 1142 mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1, 1143 mmDCORE0_MME_CTRL_LO_ARCH_A_SS, 1144 mmDCORE0_MME_CTRL_LO_ARCH_B_SS, 1145 mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS, 1146 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0, 1147 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1, 1148 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2, 1149 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3, 1150 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4, 1151 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0, 1152 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1, 1153 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2, 1154 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3, 1155 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4, 1156 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0, 1157 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1, 1158 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2, 1159 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3, 1160 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4, 1161 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0, 1162 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1, 1163 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2, 1164 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3, 1165 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4, 1166 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0, 1167 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1, 1168 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2, 1169 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3, 1170 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0, 1171 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1, 1172 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2, 1173 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3, 1174 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0, 1175 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1, 1176 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2, 1177 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3, 1178 mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE, 1179 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE, 1180 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE, 1181 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE, 1182 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE, 1183 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE, 1184 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE, 1185 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE, 1186 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE, 1187 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE, 1188 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE, 1189 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE, 1190 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE, 1191 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE, 1192 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE, 1193 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE, 1194 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE, 1195 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE, 1196 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE, 1197 mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE, 1198 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0, 1199 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1, 1200 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2, 1201 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3, 1202 mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4, 1203 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0, 1204 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1, 1205 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2, 1206 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3, 1207 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4, 1208 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0, 1209 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1, 1210 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2, 1211 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3, 1212 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4, 1213 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0, 1214 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1, 1215 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2, 1216 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3, 1217 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4, 1218 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0, 1219 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1, 1220 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2, 1221 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3, 1222 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0, 1223 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1, 1224 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2, 1225 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3, 1226 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0, 1227 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1, 1228 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2, 1229 mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3, 1230 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0, 1231 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1, 1232 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2, 1233 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3, 1234 mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4, 1235 mmDCORE0_MME_ACC_AP_LFSR_POLY, 1236 mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA, 1237 mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL, 1238 mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA, 1239 mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY, 1240 mmDCORE0_MME_ACC_WBC_SRC_BP, 1241 }; 1242 1243 static const u32 gaudi2_pb_dcr0_tpc0[] = { 1244 mmDCORE0_TPC0_QM_BASE, 1245 mmDCORE0_TPC0_CFG_BASE, 1246 mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE, 1247 }; 1248 1249 static const u32 gaudi2_pb_dcr0_tpc0_arc[] = { 1250 mmDCORE0_TPC0_QM_ARC_AUX_BASE, 1251 }; 1252 1253 static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = { 1254 {mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK}, 1255 {mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT}, 1256 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7}, 1257 {mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, 1258 {mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, 1259 {mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, 1260 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, 1261 mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, 1262 {mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, 1263 mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, 1264 {mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, 1265 mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, 1266 }; 1267 1268 static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = { 1269 mmDCORE0_TPC0_QM_CQ_CFG0_0, 1270 mmDCORE0_TPC0_QM_CQ_CFG0_1, 1271 mmDCORE0_TPC0_QM_CQ_CFG0_2, 1272 mmDCORE0_TPC0_QM_CQ_CFG0_3, 1273 mmDCORE0_TPC0_QM_CQ_CFG0_4, 1274 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0, 1275 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1, 1276 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2, 1277 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3, 1278 mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4, 1279 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0, 1280 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1, 1281 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2, 1282 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3, 1283 mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4, 1284 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0, 1285 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1, 1286 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2, 1287 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3, 1288 mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4, 1289 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0, 1290 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1, 1291 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2, 1292 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3, 1293 mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4, 1294 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0, 1295 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1, 1296 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2, 1297 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3, 1298 mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4, 1299 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0, 1300 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1, 1301 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2, 1302 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3, 1303 mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4, 1304 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0, 1305 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1, 1306 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2, 1307 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3, 1308 mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4, 1309 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0, 1310 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1, 1311 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2, 1312 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3, 1313 mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4, 1314 mmDCORE0_TPC0_QM_CQ_PTR_LO_0, 1315 mmDCORE0_TPC0_QM_CQ_PTR_HI_0, 1316 mmDCORE0_TPC0_QM_CQ_TSIZE_0, 1317 mmDCORE0_TPC0_QM_CQ_CTL_0, 1318 mmDCORE0_TPC0_QM_CQ_PTR_LO_1, 1319 mmDCORE0_TPC0_QM_CQ_PTR_HI_1, 1320 mmDCORE0_TPC0_QM_CQ_TSIZE_1, 1321 mmDCORE0_TPC0_QM_CQ_CTL_1, 1322 mmDCORE0_TPC0_QM_CQ_PTR_LO_2, 1323 mmDCORE0_TPC0_QM_CQ_PTR_HI_2, 1324 mmDCORE0_TPC0_QM_CQ_TSIZE_2, 1325 mmDCORE0_TPC0_QM_CQ_CTL_2, 1326 mmDCORE0_TPC0_QM_CQ_PTR_LO_3, 1327 mmDCORE0_TPC0_QM_CQ_PTR_HI_3, 1328 mmDCORE0_TPC0_QM_CQ_TSIZE_3, 1329 mmDCORE0_TPC0_QM_CQ_CTL_3, 1330 mmDCORE0_TPC0_QM_CQ_PTR_LO_4, 1331 mmDCORE0_TPC0_QM_CQ_PTR_HI_4, 1332 mmDCORE0_TPC0_QM_CQ_TSIZE_4, 1333 mmDCORE0_TPC0_QM_CQ_CTL_4, 1334 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE, 1335 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, 1336 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE, 1337 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, 1338 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE, 1339 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, 1340 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE, 1341 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, 1342 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE, 1343 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, 1344 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE, 1345 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, 1346 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE, 1347 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, 1348 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE, 1349 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, 1350 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE, 1351 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, 1352 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE, 1353 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, 1354 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE, 1355 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, 1356 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE, 1357 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, 1358 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE, 1359 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, 1360 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE, 1361 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, 1362 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE, 1363 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, 1364 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE, 1365 mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, 1366 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO, 1367 mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS, 1368 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI, 1369 mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS, 1370 mmDCORE0_TPC0_QM_ARB_CFG_0, 1371 mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER, 1372 mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH, 1373 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0, 1374 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1, 1375 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2, 1376 mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3, 1377 mmDCORE0_TPC0_QM_ARB_BASE_LO, 1378 mmDCORE0_TPC0_QM_ARB_BASE_HI, 1379 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN, 1380 mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1, 1381 mmDCORE0_TPC0_QM_ARB_MST_CRED_INC, 1382 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0, 1383 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1, 1384 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2, 1385 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3, 1386 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4, 1387 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5, 1388 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6, 1389 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7, 1390 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8, 1391 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9, 1392 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10, 1393 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11, 1394 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12, 1395 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13, 1396 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14, 1397 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15, 1398 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16, 1399 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17, 1400 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18, 1401 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19, 1402 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20, 1403 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21, 1404 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22, 1405 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23, 1406 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24, 1407 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25, 1408 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26, 1409 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27, 1410 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28, 1411 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29, 1412 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30, 1413 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31, 1414 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32, 1415 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33, 1416 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34, 1417 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35, 1418 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36, 1419 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37, 1420 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38, 1421 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39, 1422 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40, 1423 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41, 1424 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42, 1425 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43, 1426 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44, 1427 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45, 1428 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46, 1429 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47, 1430 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48, 1431 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49, 1432 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50, 1433 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51, 1434 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52, 1435 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53, 1436 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54, 1437 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55, 1438 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56, 1439 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57, 1440 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58, 1441 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59, 1442 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60, 1443 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61, 1444 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62, 1445 mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63, 1446 mmDCORE0_TPC0_QM_ARB_SLV_ID, 1447 mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST, 1448 mmDCORE0_TPC0_QM_ARC_CQ_CFG0, 1449 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0, 1450 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1, 1451 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2, 1452 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3, 1453 mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4, 1454 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI, 1455 mmDCORE0_TPC0_QM_CQ_CTL_CI_0, 1456 mmDCORE0_TPC0_QM_CQ_CTL_CI_1, 1457 mmDCORE0_TPC0_QM_CQ_CTL_CI_2, 1458 mmDCORE0_TPC0_QM_CQ_CTL_CI_3, 1459 mmDCORE0_TPC0_QM_CQ_CTL_CI_4, 1460 mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI, 1461 mmDCORE0_TPC0_QM_ARC_CQ_TSIZE, 1462 mmDCORE0_TPC0_QM_ARC_CQ_CTL, 1463 mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET, 1464 mmDCORE0_TPC0_QM_CP_EXT_SWITCH, 1465 mmDCORE0_TPC0_QM_CP_PRED_0, 1466 mmDCORE0_TPC0_QM_CP_PRED_1, 1467 mmDCORE0_TPC0_QM_CP_PRED_2, 1468 mmDCORE0_TPC0_QM_CP_PRED_3, 1469 mmDCORE0_TPC0_QM_CP_PRED_4, 1470 mmDCORE0_TPC0_QM_CP_PRED_UPEN_0, 1471 mmDCORE0_TPC0_QM_CP_PRED_UPEN_1, 1472 mmDCORE0_TPC0_QM_CP_PRED_UPEN_2, 1473 mmDCORE0_TPC0_QM_CP_PRED_UPEN_3, 1474 mmDCORE0_TPC0_QM_CP_PRED_UPEN_4, 1475 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0, 1476 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1, 1477 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2, 1478 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3, 1479 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4, 1480 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0, 1481 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1, 1482 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2, 1483 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3, 1484 mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4, 1485 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0, 1486 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1, 1487 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2, 1488 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3, 1489 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4, 1490 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0, 1491 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1, 1492 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2, 1493 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3, 1494 mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4, 1495 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0, 1496 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1, 1497 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2, 1498 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3, 1499 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4, 1500 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0, 1501 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1, 1502 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2, 1503 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3, 1504 mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4, 1505 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0, 1506 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1, 1507 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2, 1508 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3, 1509 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4, 1510 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0, 1511 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1, 1512 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2, 1513 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3, 1514 mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4, 1515 mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, 1516 mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO, 1517 mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO, 1518 mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO, 1519 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE, 1520 mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR, 1521 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW, 1522 mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH, 1523 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0, 1524 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0, 1525 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1, 1526 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1, 1527 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2, 1528 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2, 1529 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3, 1530 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3, 1531 mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4, 1532 mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4, 1533 mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG, 1534 mmDCORE0_TPC0_CFG_QM_KERNEL_ID, 1535 mmDCORE0_TPC0_CFG_QM_POWER_LOOP, 1536 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO, 1537 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI, 1538 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO, 1539 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI, 1540 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO, 1541 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI, 1542 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO, 1543 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI, 1544 mmDCORE0_TPC0_CFG_ROUND_CSR, 1545 mmDCORE0_TPC0_CFG_CONV_ROUND_CSR, 1546 mmDCORE0_TPC0_CFG_SEMAPHORE, 1547 mmDCORE0_TPC0_CFG_LFSR_POLYNOM, 1548 mmDCORE0_TPC0_CFG_STATUS, 1549 mmDCORE0_TPC0_CFG_TPC_CMD, 1550 mmDCORE0_TPC0_CFG_TPC_EXECUTE, 1551 mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD, 1552 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW, 1553 mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH, 1554 mmDCORE0_TPC0_CFG_RD_RATE_LIMIT, 1555 mmDCORE0_TPC0_CFG_WR_RATE_LIMIT, 1556 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO, 1557 mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI, 1558 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO, 1559 mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI, 1560 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO, 1561 mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI, 1562 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO, 1563 mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI, 1564 mmDCORE0_TPC0_CFG_KERNEL_SRF_0, 1565 mmDCORE0_TPC0_CFG_KERNEL_SRF_1, 1566 mmDCORE0_TPC0_CFG_KERNEL_SRF_2, 1567 mmDCORE0_TPC0_CFG_KERNEL_SRF_3, 1568 mmDCORE0_TPC0_CFG_KERNEL_SRF_4, 1569 mmDCORE0_TPC0_CFG_KERNEL_SRF_5, 1570 mmDCORE0_TPC0_CFG_KERNEL_SRF_6, 1571 mmDCORE0_TPC0_CFG_KERNEL_SRF_7, 1572 mmDCORE0_TPC0_CFG_KERNEL_SRF_8, 1573 mmDCORE0_TPC0_CFG_KERNEL_SRF_9, 1574 mmDCORE0_TPC0_CFG_KERNEL_SRF_10, 1575 mmDCORE0_TPC0_CFG_KERNEL_SRF_11, 1576 mmDCORE0_TPC0_CFG_KERNEL_SRF_12, 1577 mmDCORE0_TPC0_CFG_KERNEL_SRF_13, 1578 mmDCORE0_TPC0_CFG_KERNEL_SRF_14, 1579 mmDCORE0_TPC0_CFG_KERNEL_SRF_15, 1580 mmDCORE0_TPC0_CFG_KERNEL_SRF_16, 1581 mmDCORE0_TPC0_CFG_KERNEL_SRF_17, 1582 mmDCORE0_TPC0_CFG_KERNEL_SRF_18, 1583 mmDCORE0_TPC0_CFG_KERNEL_SRF_19, 1584 mmDCORE0_TPC0_CFG_KERNEL_SRF_20, 1585 mmDCORE0_TPC0_CFG_KERNEL_SRF_21, 1586 mmDCORE0_TPC0_CFG_KERNEL_SRF_22, 1587 mmDCORE0_TPC0_CFG_KERNEL_SRF_23, 1588 mmDCORE0_TPC0_CFG_KERNEL_SRF_24, 1589 mmDCORE0_TPC0_CFG_KERNEL_SRF_25, 1590 mmDCORE0_TPC0_CFG_KERNEL_SRF_26, 1591 mmDCORE0_TPC0_CFG_KERNEL_SRF_27, 1592 mmDCORE0_TPC0_CFG_KERNEL_SRF_28, 1593 mmDCORE0_TPC0_CFG_KERNEL_SRF_29, 1594 mmDCORE0_TPC0_CFG_KERNEL_SRF_30, 1595 mmDCORE0_TPC0_CFG_KERNEL_SRF_31, 1596 mmDCORE0_TPC0_CFG_TPC_SB_L0CD, 1597 mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC, 1598 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0, 1599 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1, 1600 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2, 1601 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3, 1602 mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4, 1603 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0, 1604 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1, 1605 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2, 1606 mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3 1607 }; 1608 1609 static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = { 1610 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW, 1611 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH, 1612 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE, 1613 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG, 1614 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE, 1615 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE, 1616 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE, 1617 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE, 1618 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE, 1619 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE, 1620 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE, 1621 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE, 1622 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE, 1623 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE, 1624 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE, 1625 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH, 1626 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH, 1627 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH, 1628 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH, 1629 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH, 1630 }; 1631 1632 static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = { 1633 mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW, 1634 mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH, 1635 mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE, 1636 mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG, 1637 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE, 1638 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE, 1639 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE, 1640 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE, 1641 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE, 1642 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE, 1643 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE, 1644 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE, 1645 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE, 1646 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE, 1647 mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE, 1648 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH, 1649 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH, 1650 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH, 1651 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH, 1652 mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH, 1653 }; 1654 1655 static const u32 gaudi2_pb_dcr0_sram0[] = { 1656 mmDCORE0_SRAM0_BANK_BASE, 1657 mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE, 1658 mmDCORE0_SRAM0_RTR_BASE, 1659 }; 1660 1661 static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = { 1662 mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE, 1663 }; 1664 1665 static const u32 gaudi2_pb_dcr0_sm_glbl[] = { 1666 mmDCORE0_SYNC_MNGR_GLBL_BASE, 1667 }; 1668 1669 static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = { 1670 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63}, 1671 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63}, 1672 {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63}, 1673 {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63}, 1674 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63}, 1675 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63}, 1676 {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63}, 1677 {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63}, 1678 }; 1679 1680 static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = { 1681 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63}, 1682 {mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63}, 1683 {mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63}, 1684 {mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63}, 1685 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63}, 1686 {mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63}, 1687 {mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63}, 1688 {mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63}, 1689 }; 1690 1691 static const u32 gaudi2_pb_arc_sched[] = { 1692 mmARC_FARM_ARC0_AUX_BASE, 1693 mmARC_FARM_ARC0_DUP_ENG_BASE, 1694 mmARC_FARM_ARC0_ACP_ENG_BASE, 1695 }; 1696 1697 static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = { 1698 {mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK}, 1699 {mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT}, 1700 {mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7}, 1701 {mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT}, 1702 {mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN}, 1703 {mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN}, 1704 {mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG}, 1705 {mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI}, 1706 {mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN}, 1707 {mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63}, 1708 {mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD}, 1709 {mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG}, 1710 }; 1711 1712 static const u32 gaudi2_pb_xbar_mid[] = { 1713 mmXBAR_MID_0_BASE, 1714 }; 1715 1716 static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = { 1717 mmXBAR_MID_0_UPSCALE, 1718 mmXBAR_MID_0_DOWN_CONV, 1719 mmXBAR_MID_0_DOWN_CONV_LFSR_EN, 1720 mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD, 1721 mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE, 1722 mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY, 1723 }; 1724 1725 static const u32 gaudi2_pb_xbar_edge[] = { 1726 mmXBAR_EDGE_0_BASE, 1727 }; 1728 1729 static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = { 1730 mmXBAR_EDGE_0_UPSCALE, 1731 mmXBAR_EDGE_0_DOWN_CONV, 1732 mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN, 1733 mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD, 1734 mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE, 1735 mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY, 1736 }; 1737 1738 static const u32 gaudi2_pb_nic0[] = { 1739 mmNIC0_TMR_BASE, 1740 mmNIC0_RXB_CORE_BASE, 1741 mmNIC0_RXE0_BASE, 1742 mmNIC0_RXE1_BASE, 1743 mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE, 1744 mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE, 1745 mmNIC0_TXS0_BASE, 1746 mmNIC0_TXS1_BASE, 1747 mmNIC0_TXE0_BASE, 1748 mmNIC0_TXE1_BASE, 1749 mmNIC0_TXB_BASE, 1750 mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE, 1751 }; 1752 1753 static const u32 gaudi2_pb_nic0_qm_qpc[] = { 1754 mmNIC0_QM0_BASE, 1755 mmNIC0_QPC0_BASE, 1756 }; 1757 1758 static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = { 1759 mmNIC0_QM_ARC_AUX0_BASE, 1760 }; 1761 1762 static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = { 1763 {mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK}, 1764 {mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT}, 1765 {mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7}, 1766 {mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT}, 1767 {mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN}, 1768 {mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN}, 1769 {mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG}, 1770 {mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI}, 1771 {mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN}, 1772 }; 1773 1774 static const u32 gaudi2_pb_nic0_umr[] = { 1775 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE, 1776 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */ 1777 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */ 1778 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */ 1779 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */ 1780 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */ 1781 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */ 1782 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */ 1783 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */ 1784 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */ 1785 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */ 1786 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */ 1787 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */ 1788 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */ 1789 mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */ 1790 }; 1791 1792 static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = { 1793 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32, 1794 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX}, 1795 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */ 1796 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1}, 1797 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */ 1798 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2}, 1799 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */ 1800 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3}, 1801 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */ 1802 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4}, 1803 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */ 1804 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5}, 1805 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */ 1806 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6}, 1807 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */ 1808 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7}, 1809 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */ 1810 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8}, 1811 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */ 1812 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9}, 1813 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */ 1814 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10}, 1815 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */ 1816 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11}, 1817 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */ 1818 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12}, 1819 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */ 1820 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13}, 1821 {mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */ 1822 mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14}, 1823 }; 1824 1825 /* 1826 * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit 1827 * registers and since the user writes in bulks of 64 bits we need to un-secure 1828 * also the following 32 bits (that's why we added also the next 4 bytes to the 1829 * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes 1830 * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be 1831 * unsecured as well. 1832 */ 1833 #define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4) 1834 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4) 1835 #define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60 1836 1837 static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = { 1838 mmNIC0_QPC0_LINEAR_WQE_STATIC_0, 1839 mmNIC0_QPC0_LINEAR_WQE_STATIC_1, 1840 mmNIC0_QPC0_LINEAR_WQE_STATIC_2, 1841 mmNIC0_QPC0_LINEAR_WQE_STATIC_3, 1842 mmNIC0_QPC0_LINEAR_WQE_STATIC_4, 1843 mmNIC0_QPC0_LINEAR_WQE_STATIC_5, 1844 mmNIC0_QPC0_LINEAR_WQE_STATIC_6, 1845 mmNIC0_QPC0_LINEAR_WQE_STATIC_7, 1846 mmNIC0_QPC0_LINEAR_WQE_STATIC_8, 1847 mmNIC0_QPC0_LINEAR_WQE_STATIC_9, 1848 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0, 1849 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1, 1850 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2, 1851 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3, 1852 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4, 1853 mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5, 1854 mmNIC0_QPC0_LINEAR_WQE_QPN, 1855 mmNIC0_QPC0_LINEAR_WQE_RSV, 1856 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0, 1857 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1, 1858 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2, 1859 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3, 1860 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4, 1861 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5, 1862 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6, 1863 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7, 1864 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8, 1865 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9, 1866 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10, 1867 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11, 1868 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12, 1869 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13, 1870 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14, 1871 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15, 1872 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16, 1873 mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17, 1874 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0, 1875 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1, 1876 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2, 1877 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3, 1878 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4, 1879 mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5, 1880 mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN, 1881 mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV, 1882 mmNIC0_QPC0_QMAN_DOORBELL, 1883 mmNIC0_QPC0_QMAN_DOORBELL_QPN, 1884 mmNIC0_QPC0_SPECIAL_GLBL_SPARE, 1885 mmNIC0_QM0_CQ_CFG0_0, 1886 mmNIC0_QM0_CQ_CFG0_1, 1887 mmNIC0_QM0_CQ_CFG0_2, 1888 mmNIC0_QM0_CQ_CFG0_3, 1889 mmNIC0_QM0_CQ_CFG0_4, 1890 mmNIC0_QM0_CP_FENCE0_RDATA_0, 1891 mmNIC0_QM0_CP_FENCE0_RDATA_1, 1892 mmNIC0_QM0_CP_FENCE0_RDATA_2, 1893 mmNIC0_QM0_CP_FENCE0_RDATA_3, 1894 mmNIC0_QM0_CP_FENCE0_RDATA_4, 1895 mmNIC0_QM0_CP_FENCE1_RDATA_0, 1896 mmNIC0_QM0_CP_FENCE1_RDATA_1, 1897 mmNIC0_QM0_CP_FENCE1_RDATA_2, 1898 mmNIC0_QM0_CP_FENCE1_RDATA_3, 1899 mmNIC0_QM0_CP_FENCE1_RDATA_4, 1900 mmNIC0_QM0_CP_FENCE2_RDATA_0, 1901 mmNIC0_QM0_CP_FENCE2_RDATA_1, 1902 mmNIC0_QM0_CP_FENCE2_RDATA_2, 1903 mmNIC0_QM0_CP_FENCE2_RDATA_3, 1904 mmNIC0_QM0_CP_FENCE2_RDATA_4, 1905 mmNIC0_QM0_CP_FENCE3_RDATA_0, 1906 mmNIC0_QM0_CP_FENCE3_RDATA_1, 1907 mmNIC0_QM0_CP_FENCE3_RDATA_2, 1908 mmNIC0_QM0_CP_FENCE3_RDATA_3, 1909 mmNIC0_QM0_CP_FENCE3_RDATA_4, 1910 mmNIC0_QM0_CP_FENCE0_CNT_0, 1911 mmNIC0_QM0_CP_FENCE0_CNT_1, 1912 mmNIC0_QM0_CP_FENCE0_CNT_2, 1913 mmNIC0_QM0_CP_FENCE0_CNT_3, 1914 mmNIC0_QM0_CP_FENCE0_CNT_4, 1915 mmNIC0_QM0_CP_FENCE1_CNT_0, 1916 mmNIC0_QM0_CP_FENCE1_CNT_1, 1917 mmNIC0_QM0_CP_FENCE1_CNT_2, 1918 mmNIC0_QM0_CP_FENCE1_CNT_3, 1919 mmNIC0_QM0_CP_FENCE1_CNT_4, 1920 mmNIC0_QM0_CP_FENCE2_CNT_0, 1921 mmNIC0_QM0_CP_FENCE2_CNT_1, 1922 mmNIC0_QM0_CP_FENCE2_CNT_2, 1923 mmNIC0_QM0_CP_FENCE2_CNT_3, 1924 mmNIC0_QM0_CP_FENCE2_CNT_4, 1925 mmNIC0_QM0_CP_FENCE3_CNT_0, 1926 mmNIC0_QM0_CP_FENCE3_CNT_1, 1927 mmNIC0_QM0_CP_FENCE3_CNT_2, 1928 mmNIC0_QM0_CP_FENCE3_CNT_3, 1929 mmNIC0_QM0_CP_FENCE3_CNT_4, 1930 mmNIC0_QM0_CQ_PTR_LO_0, 1931 mmNIC0_QM0_CQ_PTR_HI_0, 1932 mmNIC0_QM0_CQ_TSIZE_0, 1933 mmNIC0_QM0_CQ_CTL_0, 1934 mmNIC0_QM0_CQ_PTR_LO_1, 1935 mmNIC0_QM0_CQ_PTR_HI_1, 1936 mmNIC0_QM0_CQ_TSIZE_1, 1937 mmNIC0_QM0_CQ_CTL_1, 1938 mmNIC0_QM0_CQ_PTR_LO_2, 1939 mmNIC0_QM0_CQ_PTR_HI_2, 1940 mmNIC0_QM0_CQ_TSIZE_2, 1941 mmNIC0_QM0_CQ_CTL_2, 1942 mmNIC0_QM0_CQ_PTR_LO_3, 1943 mmNIC0_QM0_CQ_PTR_HI_3, 1944 mmNIC0_QM0_CQ_TSIZE_3, 1945 mmNIC0_QM0_CQ_CTL_3, 1946 mmNIC0_QM0_CQ_PTR_LO_4, 1947 mmNIC0_QM0_CQ_PTR_HI_4, 1948 mmNIC0_QM0_CQ_TSIZE_4, 1949 mmNIC0_QM0_CQ_CTL_4, 1950 mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE, 1951 mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4, 1952 mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE, 1953 mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4, 1954 mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE, 1955 mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4, 1956 mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE, 1957 mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4, 1958 mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE, 1959 mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4, 1960 mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE, 1961 mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4, 1962 mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE, 1963 mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4, 1964 mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE, 1965 mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4, 1966 mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE, 1967 mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4, 1968 mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE, 1969 mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4, 1970 mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE, 1971 mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4, 1972 mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE, 1973 mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4, 1974 mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE, 1975 mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4, 1976 mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE, 1977 mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4, 1978 mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE, 1979 mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4, 1980 mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE, 1981 mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4, 1982 mmNIC0_QM0_ARC_CQ_PTR_LO, 1983 mmNIC0_QM0_ARC_CQ_PTR_LO_STS, 1984 mmNIC0_QM0_ARC_CQ_PTR_HI, 1985 mmNIC0_QM0_ARC_CQ_PTR_HI_STS, 1986 mmNIC0_QM0_ARB_CFG_0, 1987 mmNIC0_QM0_ARB_MST_QUIET_PER, 1988 mmNIC0_QM0_ARB_CHOICE_Q_PUSH, 1989 mmNIC0_QM0_ARB_WRR_WEIGHT_0, 1990 mmNIC0_QM0_ARB_WRR_WEIGHT_1, 1991 mmNIC0_QM0_ARB_WRR_WEIGHT_2, 1992 mmNIC0_QM0_ARB_WRR_WEIGHT_3, 1993 mmNIC0_QM0_ARB_BASE_LO, 1994 mmNIC0_QM0_ARB_BASE_HI, 1995 mmNIC0_QM0_ARB_MST_SLAVE_EN, 1996 mmNIC0_QM0_ARB_MST_SLAVE_EN_1, 1997 mmNIC0_QM0_ARB_MST_CRED_INC, 1998 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0, 1999 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1, 2000 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2, 2001 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3, 2002 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4, 2003 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5, 2004 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6, 2005 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7, 2006 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8, 2007 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9, 2008 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10, 2009 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11, 2010 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12, 2011 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13, 2012 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14, 2013 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15, 2014 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16, 2015 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17, 2016 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18, 2017 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19, 2018 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20, 2019 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21, 2020 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22, 2021 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23, 2022 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24, 2023 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25, 2024 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26, 2025 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27, 2026 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28, 2027 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29, 2028 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30, 2029 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31, 2030 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32, 2031 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33, 2032 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34, 2033 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35, 2034 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36, 2035 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37, 2036 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38, 2037 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39, 2038 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40, 2039 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41, 2040 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42, 2041 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43, 2042 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44, 2043 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45, 2044 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46, 2045 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47, 2046 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48, 2047 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49, 2048 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50, 2049 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51, 2050 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52, 2051 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53, 2052 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54, 2053 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55, 2054 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56, 2055 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57, 2056 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58, 2057 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59, 2058 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60, 2059 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61, 2060 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62, 2061 mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63, 2062 mmNIC0_QM0_ARB_SLV_ID, 2063 mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST, 2064 mmNIC0_QM0_ARC_CQ_CFG0, 2065 mmNIC0_QM0_CQ_IFIFO_CI_0, 2066 mmNIC0_QM0_CQ_IFIFO_CI_1, 2067 mmNIC0_QM0_CQ_IFIFO_CI_2, 2068 mmNIC0_QM0_CQ_IFIFO_CI_3, 2069 mmNIC0_QM0_CQ_IFIFO_CI_4, 2070 mmNIC0_QM0_ARC_CQ_IFIFO_CI, 2071 mmNIC0_QM0_CQ_CTL_CI_0, 2072 mmNIC0_QM0_CQ_CTL_CI_1, 2073 mmNIC0_QM0_CQ_CTL_CI_2, 2074 mmNIC0_QM0_CQ_CTL_CI_3, 2075 mmNIC0_QM0_CQ_CTL_CI_4, 2076 mmNIC0_QM0_ARC_CQ_CTL_CI, 2077 mmNIC0_QM0_ARC_CQ_TSIZE, 2078 mmNIC0_QM0_ARC_CQ_CTL, 2079 mmNIC0_QM0_CP_SWITCH_WD_SET, 2080 mmNIC0_QM0_CP_EXT_SWITCH, 2081 mmNIC0_QM0_CP_PRED_0, 2082 mmNIC0_QM0_CP_PRED_1, 2083 mmNIC0_QM0_CP_PRED_2, 2084 mmNIC0_QM0_CP_PRED_3, 2085 mmNIC0_QM0_CP_PRED_4, 2086 mmNIC0_QM0_CP_PRED_UPEN_0, 2087 mmNIC0_QM0_CP_PRED_UPEN_1, 2088 mmNIC0_QM0_CP_PRED_UPEN_2, 2089 mmNIC0_QM0_CP_PRED_UPEN_3, 2090 mmNIC0_QM0_CP_PRED_UPEN_4, 2091 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0, 2092 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1, 2093 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2, 2094 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3, 2095 mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4, 2096 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0, 2097 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1, 2098 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2, 2099 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3, 2100 mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4, 2101 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0, 2102 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1, 2103 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2, 2104 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3, 2105 mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4, 2106 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0, 2107 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1, 2108 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2, 2109 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3, 2110 mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4, 2111 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0, 2112 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1, 2113 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2, 2114 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3, 2115 mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4, 2116 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0, 2117 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1, 2118 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2, 2119 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3, 2120 mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4, 2121 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0, 2122 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1, 2123 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2, 2124 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3, 2125 mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4, 2126 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0, 2127 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1, 2128 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2, 2129 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3, 2130 mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4, 2131 mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO, 2132 mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO, 2133 mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO, 2134 mmNIC0_QM0_CQ_CTL_MSG_BASE_LO 2135 }; 2136 2137 static const u32 gaudi2_pb_rot0[] = { 2138 mmROT0_BASE, 2139 mmROT0_MSTR_IF_RR_SHRD_HBW_BASE, 2140 mmROT0_QM_BASE, 2141 }; 2142 2143 static const u32 gaudi2_pb_rot0_arc[] = { 2144 mmROT0_QM_ARC_AUX_BASE 2145 }; 2146 2147 static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = { 2148 {mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK}, 2149 {mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT}, 2150 {mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7}, 2151 {mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT}, 2152 {mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN}, 2153 {mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN}, 2154 {mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG}, 2155 {mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI}, 2156 {mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN}, 2157 }; 2158 2159 static const u32 gaudi2_pb_rot0_unsecured_regs[] = { 2160 mmROT0_QM_CQ_CFG0_0, 2161 mmROT0_QM_CQ_CFG0_1, 2162 mmROT0_QM_CQ_CFG0_2, 2163 mmROT0_QM_CQ_CFG0_3, 2164 mmROT0_QM_CQ_CFG0_4, 2165 mmROT0_QM_CP_FENCE0_RDATA_0, 2166 mmROT0_QM_CP_FENCE0_RDATA_1, 2167 mmROT0_QM_CP_FENCE0_RDATA_2, 2168 mmROT0_QM_CP_FENCE0_RDATA_3, 2169 mmROT0_QM_CP_FENCE0_RDATA_4, 2170 mmROT0_QM_CP_FENCE1_RDATA_0, 2171 mmROT0_QM_CP_FENCE1_RDATA_1, 2172 mmROT0_QM_CP_FENCE1_RDATA_2, 2173 mmROT0_QM_CP_FENCE1_RDATA_3, 2174 mmROT0_QM_CP_FENCE1_RDATA_4, 2175 mmROT0_QM_CP_FENCE2_RDATA_0, 2176 mmROT0_QM_CP_FENCE2_RDATA_1, 2177 mmROT0_QM_CP_FENCE2_RDATA_2, 2178 mmROT0_QM_CP_FENCE2_RDATA_3, 2179 mmROT0_QM_CP_FENCE2_RDATA_4, 2180 mmROT0_QM_CP_FENCE3_RDATA_0, 2181 mmROT0_QM_CP_FENCE3_RDATA_1, 2182 mmROT0_QM_CP_FENCE3_RDATA_2, 2183 mmROT0_QM_CP_FENCE3_RDATA_3, 2184 mmROT0_QM_CP_FENCE3_RDATA_4, 2185 mmROT0_QM_CP_FENCE0_CNT_0, 2186 mmROT0_QM_CP_FENCE0_CNT_1, 2187 mmROT0_QM_CP_FENCE0_CNT_2, 2188 mmROT0_QM_CP_FENCE0_CNT_3, 2189 mmROT0_QM_CP_FENCE0_CNT_4, 2190 mmROT0_QM_CP_FENCE1_CNT_0, 2191 mmROT0_QM_CP_FENCE1_CNT_1, 2192 mmROT0_QM_CP_FENCE1_CNT_2, 2193 mmROT0_QM_CP_FENCE1_CNT_3, 2194 mmROT0_QM_CP_FENCE1_CNT_4, 2195 mmROT0_QM_CP_FENCE2_CNT_0, 2196 mmROT0_QM_CP_FENCE2_CNT_1, 2197 mmROT0_QM_CP_FENCE2_CNT_2, 2198 mmROT0_QM_CP_FENCE2_CNT_3, 2199 mmROT0_QM_CP_FENCE2_CNT_4, 2200 mmROT0_QM_CP_FENCE3_CNT_0, 2201 mmROT0_QM_CP_FENCE3_CNT_1, 2202 mmROT0_QM_CP_FENCE3_CNT_2, 2203 mmROT0_QM_CP_FENCE3_CNT_3, 2204 mmROT0_QM_CP_FENCE3_CNT_4, 2205 mmROT0_QM_CQ_PTR_LO_0, 2206 mmROT0_QM_CQ_PTR_HI_0, 2207 mmROT0_QM_CQ_TSIZE_0, 2208 mmROT0_QM_CQ_CTL_0, 2209 mmROT0_QM_CQ_PTR_LO_1, 2210 mmROT0_QM_CQ_PTR_HI_1, 2211 mmROT0_QM_CQ_TSIZE_1, 2212 mmROT0_QM_CQ_CTL_1, 2213 mmROT0_QM_CQ_PTR_LO_2, 2214 mmROT0_QM_CQ_PTR_HI_2, 2215 mmROT0_QM_CQ_TSIZE_2, 2216 mmROT0_QM_CQ_CTL_2, 2217 mmROT0_QM_CQ_PTR_LO_3, 2218 mmROT0_QM_CQ_PTR_HI_3, 2219 mmROT0_QM_CQ_TSIZE_3, 2220 mmROT0_QM_CQ_CTL_3, 2221 mmROT0_QM_CQ_PTR_LO_4, 2222 mmROT0_QM_CQ_PTR_HI_4, 2223 mmROT0_QM_CQ_TSIZE_4, 2224 mmROT0_QM_CQ_CTL_4, 2225 mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE, 2226 mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4, 2227 mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE, 2228 mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4, 2229 mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE, 2230 mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4, 2231 mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE, 2232 mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4, 2233 mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE, 2234 mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4, 2235 mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE, 2236 mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4, 2237 mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE, 2238 mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4, 2239 mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE, 2240 mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4, 2241 mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE, 2242 mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4, 2243 mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE, 2244 mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4, 2245 mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE, 2246 mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4, 2247 mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE, 2248 mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4, 2249 mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE, 2250 mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4, 2251 mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE, 2252 mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4, 2253 mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE, 2254 mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4, 2255 mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE, 2256 mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4, 2257 mmROT0_QM_ARC_CQ_PTR_LO, 2258 mmROT0_QM_ARC_CQ_PTR_LO_STS, 2259 mmROT0_QM_ARC_CQ_PTR_HI, 2260 mmROT0_QM_ARC_CQ_PTR_HI_STS, 2261 mmROT0_QM_ARB_CFG_0, 2262 mmROT0_QM_ARB_MST_QUIET_PER, 2263 mmROT0_QM_ARB_CHOICE_Q_PUSH, 2264 mmROT0_QM_ARB_WRR_WEIGHT_0, 2265 mmROT0_QM_ARB_WRR_WEIGHT_1, 2266 mmROT0_QM_ARB_WRR_WEIGHT_2, 2267 mmROT0_QM_ARB_WRR_WEIGHT_3, 2268 mmROT0_QM_ARB_BASE_LO, 2269 mmROT0_QM_ARB_BASE_HI, 2270 mmROT0_QM_ARB_MST_SLAVE_EN, 2271 mmROT0_QM_ARB_MST_SLAVE_EN_1, 2272 mmROT0_QM_ARB_MST_CRED_INC, 2273 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0, 2274 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1, 2275 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2, 2276 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3, 2277 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4, 2278 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5, 2279 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6, 2280 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7, 2281 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8, 2282 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9, 2283 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10, 2284 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11, 2285 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12, 2286 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13, 2287 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14, 2288 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15, 2289 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16, 2290 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17, 2291 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18, 2292 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19, 2293 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20, 2294 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21, 2295 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22, 2296 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23, 2297 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24, 2298 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25, 2299 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26, 2300 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27, 2301 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28, 2302 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29, 2303 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30, 2304 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31, 2305 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32, 2306 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33, 2307 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34, 2308 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35, 2309 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36, 2310 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37, 2311 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38, 2312 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39, 2313 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40, 2314 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41, 2315 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42, 2316 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43, 2317 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44, 2318 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45, 2319 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46, 2320 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47, 2321 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48, 2322 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49, 2323 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50, 2324 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51, 2325 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52, 2326 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53, 2327 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54, 2328 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55, 2329 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56, 2330 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57, 2331 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58, 2332 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59, 2333 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60, 2334 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61, 2335 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62, 2336 mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63, 2337 mmROT0_QM_ARB_SLV_ID, 2338 mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST, 2339 mmROT0_QM_ARC_CQ_CFG0, 2340 mmROT0_QM_CQ_IFIFO_CI_0, 2341 mmROT0_QM_CQ_IFIFO_CI_1, 2342 mmROT0_QM_CQ_IFIFO_CI_2, 2343 mmROT0_QM_CQ_IFIFO_CI_3, 2344 mmROT0_QM_CQ_IFIFO_CI_4, 2345 mmROT0_QM_ARC_CQ_IFIFO_CI, 2346 mmROT0_QM_CQ_CTL_CI_0, 2347 mmROT0_QM_CQ_CTL_CI_1, 2348 mmROT0_QM_CQ_CTL_CI_2, 2349 mmROT0_QM_CQ_CTL_CI_3, 2350 mmROT0_QM_CQ_CTL_CI_4, 2351 mmROT0_QM_ARC_CQ_CTL_CI, 2352 mmROT0_QM_ARC_CQ_TSIZE, 2353 mmROT0_QM_ARC_CQ_CTL, 2354 mmROT0_QM_CP_SWITCH_WD_SET, 2355 mmROT0_QM_CP_EXT_SWITCH, 2356 mmROT0_QM_CP_PRED_0, 2357 mmROT0_QM_CP_PRED_1, 2358 mmROT0_QM_CP_PRED_2, 2359 mmROT0_QM_CP_PRED_3, 2360 mmROT0_QM_CP_PRED_4, 2361 mmROT0_QM_CP_PRED_UPEN_0, 2362 mmROT0_QM_CP_PRED_UPEN_1, 2363 mmROT0_QM_CP_PRED_UPEN_2, 2364 mmROT0_QM_CP_PRED_UPEN_3, 2365 mmROT0_QM_CP_PRED_UPEN_4, 2366 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0, 2367 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1, 2368 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2, 2369 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3, 2370 mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4, 2371 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0, 2372 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1, 2373 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2, 2374 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3, 2375 mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4, 2376 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0, 2377 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1, 2378 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2, 2379 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3, 2380 mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4, 2381 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0, 2382 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1, 2383 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2, 2384 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3, 2385 mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4, 2386 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0, 2387 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1, 2388 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2, 2389 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3, 2390 mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4, 2391 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0, 2392 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1, 2393 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2, 2394 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3, 2395 mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4, 2396 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0, 2397 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1, 2398 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2, 2399 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3, 2400 mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4, 2401 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0, 2402 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1, 2403 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2, 2404 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3, 2405 mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4, 2406 mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO, 2407 mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO, 2408 mmROT0_QM_CQ_IFIFO_MSG_BASE_LO, 2409 mmROT0_QM_CQ_CTL_MSG_BASE_LO, 2410 mmROT0_DESC_CONTEXT_ID, 2411 mmROT0_DESC_IN_IMG_START_ADDR_L, 2412 mmROT0_DESC_IN_IMG_START_ADDR_H, 2413 mmROT0_DESC_OUT_IMG_START_ADDR_L, 2414 mmROT0_DESC_OUT_IMG_START_ADDR_H, 2415 mmROT0_DESC_CFG, 2416 mmROT0_DESC_IM_READ_SLOPE, 2417 mmROT0_DESC_SIN_D, 2418 mmROT0_DESC_COS_D, 2419 mmROT0_DESC_IN_IMG, 2420 mmROT0_DESC_IN_STRIDE, 2421 mmROT0_DESC_IN_STRIPE, 2422 mmROT0_DESC_IN_CENTER, 2423 mmROT0_DESC_OUT_IMG, 2424 mmROT0_DESC_OUT_STRIDE, 2425 mmROT0_DESC_OUT_STRIPE, 2426 mmROT0_DESC_OUT_CENTER, 2427 mmROT0_DESC_BACKGROUND, 2428 mmROT0_DESC_CPL_MSG_EN, 2429 mmROT0_DESC_IDLE_STATE, 2430 mmROT0_DESC_CPL_MSG_ADDR, 2431 mmROT0_DESC_CPL_MSG_DATA, 2432 mmROT0_DESC_X_I_START_OFFSET, 2433 mmROT0_DESC_X_I_START_OFFSET_FLIP, 2434 mmROT0_DESC_X_I_FIRST, 2435 mmROT0_DESC_Y_I_FIRST, 2436 mmROT0_DESC_Y_I, 2437 mmROT0_DESC_OUT_STRIPE_SIZE, 2438 mmROT0_DESC_RSB_CFG_0, 2439 mmROT0_DESC_RSB_PAD_VAL, 2440 mmROT0_DESC_OWM_CFG, 2441 mmROT0_DESC_CTRL_CFG, 2442 mmROT0_DESC_PIXEL_PAD, 2443 mmROT0_DESC_PREC_SHIFT, 2444 mmROT0_DESC_MAX_VAL, 2445 mmROT0_DESC_A0_M11, 2446 mmROT0_DESC_A1_M12, 2447 mmROT0_DESC_A2, 2448 mmROT0_DESC_B0_M21, 2449 mmROT0_DESC_B1_M22, 2450 mmROT0_DESC_B2, 2451 mmROT0_DESC_C0, 2452 mmROT0_DESC_C1, 2453 mmROT0_DESC_C2, 2454 mmROT0_DESC_D0, 2455 mmROT0_DESC_D1, 2456 mmROT0_DESC_D2, 2457 mmROT0_DESC_INV_PROC_SIZE_M_1, 2458 mmROT0_DESC_MESH_IMG_START_ADDR_L, 2459 mmROT0_DESC_MESH_IMG_START_ADDR_H, 2460 mmROT0_DESC_MESH_IMG, 2461 mmROT0_DESC_MESH_STRIDE, 2462 mmROT0_DESC_MESH_STRIPE, 2463 mmROT0_DESC_MESH_CTRL, 2464 mmROT0_DESC_MESH_GH, 2465 mmROT0_DESC_MESH_GV, 2466 mmROT0_DESC_MRSB_CFG_0, 2467 mmROT0_DESC_MRSB_PAD_VAL, 2468 mmROT0_DESC_BUF_CFG, 2469 mmROT0_DESC_CID_OFFSET, 2470 mmROT0_DESC_PUSH_DESC 2471 }; 2472 2473 static const u32 gaudi2_pb_psoc_global_conf[] = { 2474 mmPSOC_GLOBAL_CONF_BASE 2475 }; 2476 2477 static const u32 gaudi2_pb_psoc[] = { 2478 mmPSOC_EFUSE_BASE, 2479 mmPSOC_BTL_BASE, 2480 mmPSOC_CS_TRACE_BASE, 2481 mmPSOC_DFT_EFUSE_BASE, 2482 mmPSOC_PID_BASE, 2483 mmPSOC_ARC0_CFG_BASE, 2484 mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE, 2485 mmPSOC_ARC0_AUX_BASE, 2486 mmPSOC_ARC1_CFG_BASE, 2487 mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE, 2488 mmPSOC_ARC1_AUX_BASE, 2489 mmJT_MSTR_IF_RR_SHRD_HBW_BASE, 2490 mmSMI_MSTR_IF_RR_SHRD_HBW_BASE, 2491 mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE, 2492 mmPSOC_SVID0_BASE, 2493 mmPSOC_SVID1_BASE, 2494 mmPSOC_SVID2_BASE, 2495 mmPSOC_AVS0_BASE, 2496 mmPSOC_AVS1_BASE, 2497 mmPSOC_AVS2_BASE, 2498 mmPSOC_PWM0_BASE, 2499 mmPSOC_PWM1_BASE, 2500 mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE, 2501 }; 2502 2503 static const u32 gaudi2_pb_pmmu[] = { 2504 mmPMMU_HBW_MMU_BASE, 2505 mmPMMU_HBW_STLB_BASE, 2506 mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE, 2507 mmPMMU_PIF_BASE, 2508 }; 2509 2510 static const u32 gaudi2_pb_psoc_pll[] = { 2511 mmPSOC_MME_PLL_CTRL_BASE, 2512 mmPSOC_CPU_PLL_CTRL_BASE, 2513 mmPSOC_VID_PLL_CTRL_BASE 2514 }; 2515 2516 static const u32 gaudi2_pb_pmmu_pll[] = { 2517 mmPMMU_MME_PLL_CTRL_BASE, 2518 mmPMMU_VID_PLL_CTRL_BASE 2519 }; 2520 2521 static const u32 gaudi2_pb_xbar_pll[] = { 2522 mmDCORE0_XBAR_DMA_PLL_CTRL_BASE, 2523 mmDCORE0_XBAR_MMU_PLL_CTRL_BASE, 2524 mmDCORE0_XBAR_IF_PLL_CTRL_BASE, 2525 mmDCORE0_XBAR_MESH_PLL_CTRL_BASE, 2526 mmDCORE1_XBAR_DMA_PLL_CTRL_BASE, 2527 mmDCORE1_XBAR_MMU_PLL_CTRL_BASE, 2528 mmDCORE1_XBAR_IF_PLL_CTRL_BASE, 2529 mmDCORE1_XBAR_MESH_PLL_CTRL_BASE, 2530 mmDCORE1_XBAR_HBM_PLL_CTRL_BASE, 2531 mmDCORE2_XBAR_DMA_PLL_CTRL_BASE, 2532 mmDCORE2_XBAR_MMU_PLL_CTRL_BASE, 2533 mmDCORE2_XBAR_IF_PLL_CTRL_BASE, 2534 mmDCORE2_XBAR_BANK_PLL_CTRL_BASE, 2535 mmDCORE2_XBAR_HBM_PLL_CTRL_BASE, 2536 mmDCORE3_XBAR_DMA_PLL_CTRL_BASE, 2537 mmDCORE3_XBAR_MMU_PLL_CTRL_BASE, 2538 mmDCORE3_XBAR_IF_PLL_CTRL_BASE, 2539 mmDCORE3_XBAR_BANK_PLL_CTRL_BASE 2540 }; 2541 2542 static const u32 gaudi2_pb_xft_pll[] = { 2543 mmDCORE0_HBM_PLL_CTRL_BASE, 2544 mmDCORE0_TPC_PLL_CTRL_BASE, 2545 mmDCORE0_PCI_PLL_CTRL_BASE, 2546 mmDCORE1_HBM_PLL_CTRL_BASE, 2547 mmDCORE1_TPC_PLL_CTRL_BASE, 2548 mmDCORE1_NIC_PLL_CTRL_BASE, 2549 mmDCORE2_HBM_PLL_CTRL_BASE, 2550 mmDCORE2_TPC_PLL_CTRL_BASE, 2551 mmDCORE3_HBM_PLL_CTRL_BASE, 2552 mmDCORE3_TPC_PLL_CTRL_BASE, 2553 mmDCORE3_NIC_PLL_CTRL_BASE, 2554 }; 2555 2556 static const u32 gaudi2_pb_pcie[] = { 2557 mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE, 2558 mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE, 2559 mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE, 2560 mmPCIE_WRAP_BASE, 2561 }; 2562 2563 static const u32 gaudi2_pb_pcie_unsecured_regs[] = { 2564 mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0, 2565 }; 2566 2567 static const u32 gaudi2_pb_thermal_sensor0[] = { 2568 mmDCORE0_XFT_BASE, 2569 mmDCORE0_TSTDVS_BASE, 2570 }; 2571 2572 static const u32 gaudi2_pb_hbm[] = { 2573 mmHBM0_MC0_BASE, 2574 mmHBM0_MC1_BASE, 2575 }; 2576 2577 static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = { 2578 mmDCORE0_MME_QM_ARC_ACP_ENG_BASE, 2579 }; 2580 2581 static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = { 2582 {mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG}, 2583 }; 2584 2585 struct gaudi2_tpc_pb_data { 2586 struct hl_block_glbl_sec *glbl_sec; 2587 u32 block_array_size; 2588 }; 2589 2590 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset, 2591 struct iterate_module_ctx *ctx) 2592 { 2593 struct gaudi2_tpc_pb_data *pb_data = ctx->data; 2594 2595 hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec, 2596 offset, pb_data->block_array_size); 2597 } 2598 2599 static int gaudi2_init_pb_tpc(struct hl_device *hdev) 2600 { 2601 u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size; 2602 struct gaudi2_tpc_pb_data tpc_pb_data; 2603 struct hl_block_glbl_sec *glbl_sec; 2604 struct iterate_module_ctx tpc_iter; 2605 int i; 2606 2607 block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0); 2608 2609 glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL); 2610 if (!glbl_sec) 2611 return -ENOMEM; 2612 2613 kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE - 2614 mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE; 2615 qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE; 2616 2617 hl_secure_block(hdev, glbl_sec, block_array_size); 2618 hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs, 2619 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs), 2620 0, gaudi2_pb_dcr0_tpc0, glbl_sec, 2621 block_array_size); 2622 2623 /* Unsecure all TPC kernel tensors */ 2624 for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++) 2625 hl_unsecure_registers(hdev, 2626 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs, 2627 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs), 2628 i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0, 2629 glbl_sec, block_array_size); 2630 2631 /* Unsecure all TPC QM tensors */ 2632 for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++) 2633 hl_unsecure_registers(hdev, 2634 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs, 2635 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs), 2636 i * qm_tensor_stride, 2637 gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size); 2638 2639 /* unsecure all 32 TPC QM SRF regs */ 2640 stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0; 2641 for (i = 0 ; i < 32 ; i++) 2642 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0, 2643 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec, 2644 block_array_size); 2645 2646 /* unsecure the 4 TPC LOCK VALUE regs */ 2647 stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0; 2648 for (i = 0 ; i < 4 ; i++) 2649 hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0, 2650 i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec, 2651 block_array_size); 2652 2653 /* prepare data for TPC iterator */ 2654 tpc_pb_data.glbl_sec = glbl_sec; 2655 tpc_pb_data.block_array_size = block_array_size; 2656 tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec; 2657 tpc_iter.data = &tpc_pb_data; 2658 gaudi2_iterate_tpcs(hdev, &tpc_iter); 2659 2660 kfree(glbl_sec); 2661 2662 return 0; 2663 } 2664 2665 struct gaudi2_tpc_arc_pb_data { 2666 u32 unsecured_regs_arr_size; 2667 u32 arc_regs_arr_size; 2668 }; 2669 2670 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset, 2671 struct iterate_module_ctx *ctx) 2672 { 2673 struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data; 2674 2675 ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1, 2676 offset, gaudi2_pb_dcr0_tpc0_arc, 2677 pb_data->arc_regs_arr_size, 2678 gaudi2_pb_dcr0_tpc0_arc_unsecured_regs, 2679 pb_data->unsecured_regs_arr_size); 2680 } 2681 2682 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev) 2683 { 2684 struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data; 2685 struct iterate_module_ctx tpc_iter; 2686 2687 tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc); 2688 tpc_arc_pb_data.unsecured_regs_arr_size = 2689 ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs); 2690 2691 tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges; 2692 tpc_iter.data = &tpc_arc_pb_data; 2693 gaudi2_iterate_tpcs(hdev, &tpc_iter); 2694 2695 return tpc_iter.rc; 2696 } 2697 2698 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev) 2699 { 2700 int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length; 2701 u32 sec_entry, *sec_array, array_base, first_sob, first_mon; 2702 2703 array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr + 2704 gaudi2_pb_dcr0_sm_objs.glbl_sec_offset; 2705 2706 sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL); 2707 if (!sec_array) 2708 return -ENOMEM; 2709 2710 first_sob = GAUDI2_RESERVED_SOB_NUMBER; 2711 first_mon = GAUDI2_RESERVED_MON_NUMBER; 2712 2713 /* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */ 2714 for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++) 2715 UNSET_GLBL_SEC_BIT(sec_array, j); 2716 2717 /* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */ 2718 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) 2719 UNSET_GLBL_SEC_BIT(sec_array, j); 2720 2721 /* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */ 2722 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) 2723 UNSET_GLBL_SEC_BIT(sec_array, j); 2724 2725 /* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */ 2726 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) 2727 UNSET_GLBL_SEC_BIT(sec_array, j); 2728 2729 /* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */ 2730 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) 2731 UNSET_GLBL_SEC_BIT(sec_array, j); 2732 2733 /* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */ 2734 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) 2735 UNSET_GLBL_SEC_BIT(sec_array, j); 2736 2737 /* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */ 2738 for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++) 2739 UNSET_GLBL_SEC_BIT(sec_array, j); 2740 2741 /* Unsecure selected Dcore0 registers */ 2742 for (i = 0 ; i < glbl_sec_array_len ; i++) { 2743 sec_entry = array_base + i * sizeof(u32); 2744 WREG32(sec_entry, sec_array[i]); 2745 } 2746 2747 /* Unsecure Dcore1 - Dcore3 registers */ 2748 memset(sec_array, -1, glbl_sec_array_len * sizeof(u32)); 2749 2750 for (i = 1 ; i < NUM_OF_DCORES ; i++) { 2751 for (j = 0 ; j < glbl_sec_array_len ; j++) { 2752 sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32); 2753 WREG32(sec_entry, sec_array[j]); 2754 } 2755 } 2756 2757 kfree(sec_array); 2758 2759 return 0; 2760 } 2761 2762 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data) 2763 { 2764 u32 reg_min_offset, reg_max_offset, write_min, write_max; 2765 struct rr_config *rr_cfg = (struct rr_config *) data; 2766 2767 switch (rr_cfg->type) { 2768 case RR_TYPE_SHORT: 2769 reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET; 2770 reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET; 2771 break; 2772 2773 case RR_TYPE_LONG: 2774 reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET; 2775 reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET; 2776 break; 2777 2778 case RR_TYPE_SHORT_PRIV: 2779 reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET; 2780 reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET; 2781 break; 2782 2783 case RR_TYPE_LONG_PRIV: 2784 reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET; 2785 reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET; 2786 break; 2787 2788 default: 2789 dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type); 2790 return; 2791 } 2792 2793 reg_min_offset += rr_cfg->index * sizeof(u32); 2794 reg_max_offset += rr_cfg->index * sizeof(u32); 2795 2796 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) { 2797 write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min)); 2798 write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max)); 2799 2800 } else { 2801 write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min)); 2802 write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max)); 2803 } 2804 2805 /* Configure LBW RR: 2806 * Both RR types start blocking from base address 0x1000007FF8000000 2807 * SHORT RRs address bits [26:12] 2808 * LONG RRs address bits [26:0] 2809 */ 2810 WREG32(base + reg_min_offset, write_min); 2811 WREG32(base + reg_max_offset, write_max); 2812 } 2813 2814 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val, 2815 u64 max_val) 2816 { 2817 struct dup_block_ctx block_ctx; 2818 struct rr_config rr_cfg; 2819 2820 if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) && 2821 rr_index >= NUM_SHORT_LBW_RR) { 2822 2823 dev_err(hdev->dev, "invalid short LBW %s range register index: %u", 2824 rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index); 2825 return; 2826 } 2827 2828 if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) && 2829 rr_index >= NUM_LONG_LBW_RR) { 2830 2831 dev_err(hdev->dev, "invalid long LBW %s range register index: %u", 2832 rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index); 2833 return; 2834 } 2835 2836 rr_cfg.type = rr_type; 2837 rr_cfg.index = rr_index; 2838 rr_cfg.min = min_val; 2839 rr_cfg.max = max_val; 2840 2841 block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register; 2842 block_ctx.data = &rr_cfg; 2843 2844 /* SFT */ 2845 block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE; 2846 block_ctx.blocks = NUM_OF_SFT; 2847 block_ctx.block_off = SFT_OFFSET; 2848 block_ctx.instances = SFT_NUM_OF_LBW_RTR; 2849 block_ctx.instance_off = SFT_LBW_RTR_OFFSET; 2850 gaudi2_init_blocks(hdev, &block_ctx); 2851 2852 /* SIF */ 2853 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE; 2854 block_ctx.blocks = NUM_OF_DCORES; 2855 block_ctx.block_off = DCORE_OFFSET; 2856 block_ctx.instances = NUM_OF_RTR_PER_DCORE; 2857 block_ctx.instance_off = DCORE_RTR_OFFSET; 2858 gaudi2_init_blocks(hdev, &block_ctx); 2859 2860 block_ctx.blocks = 1; 2861 block_ctx.block_off = 0; 2862 block_ctx.instances = 1; 2863 block_ctx.instance_off = 0; 2864 2865 /* PCIE ELBI */ 2866 block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE; 2867 gaudi2_init_blocks(hdev, &block_ctx); 2868 2869 /* PCIE MSTR */ 2870 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE; 2871 gaudi2_init_blocks(hdev, &block_ctx); 2872 2873 /* PCIE LBW */ 2874 block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE; 2875 gaudi2_init_blocks(hdev, &block_ctx); 2876 } 2877 2878 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev) 2879 { 2880 int i; 2881 2882 /* Up to 14 14bit-address regs. 2883 * 2884 * - range 0: NIC0_CFG 2885 * - range 1: NIC1_CFG 2886 * - range 2: NIC2_CFG 2887 * - range 3: NIC3_CFG 2888 * - range 4: NIC4_CFG 2889 * - range 5: NIC5_CFG 2890 * - range 6: NIC6_CFG 2891 * - range 7: NIC7_CFG 2892 * - range 8: NIC8_CFG 2893 * - range 9: NIC9_CFG 2894 * - range 10: NIC10_CFG 2895 * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG) 2896 * 2897 * If F/W security is not enabled: 2898 * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP) 2899 */ 2900 u64 lbw_range_min_short[] = { 2901 mmNIC0_TX_AXUSER_BASE, 2902 mmNIC1_TX_AXUSER_BASE, 2903 mmNIC2_TX_AXUSER_BASE, 2904 mmNIC3_TX_AXUSER_BASE, 2905 mmNIC4_TX_AXUSER_BASE, 2906 mmNIC5_TX_AXUSER_BASE, 2907 mmNIC6_TX_AXUSER_BASE, 2908 mmNIC7_TX_AXUSER_BASE, 2909 mmNIC8_TX_AXUSER_BASE, 2910 mmNIC9_TX_AXUSER_BASE, 2911 mmNIC10_TX_AXUSER_BASE, 2912 mmNIC11_TX_AXUSER_BASE, 2913 mmPSOC_I2C_M0_BASE, 2914 mmPSOC_EFUSE_BASE 2915 }; 2916 u64 lbw_range_max_short[] = { 2917 mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2918 mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2919 mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2920 mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2921 mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2922 mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2923 mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2924 mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2925 mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2926 mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2927 mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE, 2928 mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE, 2929 mmPSOC_WDOG_BASE + HL_BLOCK_SIZE, 2930 mmSVID2_AC_BASE + HL_BLOCK_SIZE 2931 }; 2932 2933 /* Up to 4 26bit-address regs. 2934 * 2935 * - range 0: TPC_DBG 2936 * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF 2937 * - range 2/3: used in soft reset to block access to several blocks and are cleared here 2938 */ 2939 u64 lbw_range_min_long[] = { 2940 mmDCORE0_TPC0_ROM_TABLE_BASE, 2941 mmPCIE_DBI_MSIX_DOORBELL_OFF, 2942 0x0, 2943 0x0 2944 }; 2945 u64 lbw_range_max_long[] = { 2946 mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE, 2947 mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4, 2948 0x0, 2949 0x0 2950 }; 2951 2952 /* write short range registers to all lbw rtrs */ 2953 for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) { 2954 if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE || 2955 lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) && 2956 hdev->asic_prop.fw_security_enabled) 2957 continue; 2958 2959 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i, 2960 lbw_range_min_short[i], lbw_range_max_short[i]); 2961 } 2962 2963 /* write long range registers to all lbw rtrs */ 2964 for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) { 2965 gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i, 2966 lbw_range_min_long[i], lbw_range_max_long[i]); 2967 } 2968 } 2969 2970 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev) 2971 { 2972 gaudi2_init_lbw_range_registers_secure(hdev); 2973 } 2974 2975 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data) 2976 { 2977 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset; 2978 struct rr_config *rr_cfg = (struct rr_config *) data; 2979 u64 val_min, val_max; 2980 2981 switch (rr_cfg->type) { 2982 case RR_TYPE_SHORT: 2983 min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET; 2984 min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET; 2985 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET; 2986 max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET; 2987 break; 2988 2989 case RR_TYPE_LONG: 2990 min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET; 2991 min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET; 2992 max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET; 2993 max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET; 2994 break; 2995 2996 case RR_TYPE_SHORT_PRIV: 2997 min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET; 2998 min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET; 2999 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET; 3000 max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET; 3001 break; 3002 3003 case RR_TYPE_LONG_PRIV: 3004 min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET; 3005 min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET; 3006 max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET; 3007 max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET; 3008 break; 3009 3010 default: 3011 dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type); 3012 return; 3013 } 3014 3015 min_lo_reg_offset += rr_cfg->index * sizeof(u32); 3016 min_hi_reg_offset += rr_cfg->index * sizeof(u32); 3017 max_lo_reg_offset += rr_cfg->index * sizeof(u32); 3018 max_hi_reg_offset += rr_cfg->index * sizeof(u32); 3019 3020 if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) { 3021 val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) | 3022 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min); 3023 val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) | 3024 FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max); 3025 } else { 3026 val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) | 3027 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min); 3028 val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) | 3029 FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max); 3030 } 3031 3032 /* Configure HBW RR: 3033 * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12] 3034 * LONG RRs (0x<52bits>000) - HI: address bits [63:44], LO: address bits [43:12] 3035 */ 3036 WREG32(base + min_lo_reg_offset, lower_32_bits(val_min)); 3037 WREG32(base + min_hi_reg_offset, upper_32_bits(val_min)); 3038 WREG32(base + max_lo_reg_offset, lower_32_bits(val_max)); 3039 WREG32(base + max_hi_reg_offset, upper_32_bits(val_max)); 3040 } 3041 3042 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index, 3043 u64 min_val, u64 max_val) 3044 { 3045 struct dup_block_ctx block_ctx; 3046 struct rr_config rr_cfg; 3047 3048 if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) && 3049 rr_index >= NUM_SHORT_HBW_RR) { 3050 3051 dev_err(hdev->dev, "invalid short HBW %s range register index: %u", 3052 rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index); 3053 return; 3054 } 3055 3056 if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) && 3057 rr_index >= NUM_LONG_HBW_RR) { 3058 3059 dev_err(hdev->dev, "invalid long HBW %s range register index: %u", 3060 rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index); 3061 return; 3062 } 3063 3064 rr_cfg.type = rr_type; 3065 rr_cfg.index = rr_index; 3066 rr_cfg.min = min_val; 3067 rr_cfg.max = max_val; 3068 3069 block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register; 3070 block_ctx.data = &rr_cfg; 3071 3072 /* SFT */ 3073 block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE; 3074 block_ctx.blocks = NUM_OF_SFT; 3075 block_ctx.block_off = SFT_OFFSET; 3076 block_ctx.instances = SFT_NUM_OF_HBW_RTR; 3077 block_ctx.instance_off = SFT_IF_RTR_OFFSET; 3078 gaudi2_init_blocks(hdev, &block_ctx); 3079 3080 /* SIF */ 3081 block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE; 3082 block_ctx.blocks = NUM_OF_DCORES; 3083 block_ctx.block_off = DCORE_OFFSET; 3084 block_ctx.instances = NUM_OF_RTR_PER_DCORE; 3085 block_ctx.instance_off = DCORE_RTR_OFFSET; 3086 gaudi2_init_blocks(hdev, &block_ctx); 3087 3088 /* PCIE MSTR */ 3089 block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE; 3090 block_ctx.blocks = 1; 3091 block_ctx.block_off = 0; 3092 block_ctx.instances = 1; 3093 block_ctx.instance_off = 0; 3094 gaudi2_init_blocks(hdev, &block_ctx); 3095 } 3096 3097 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev) 3098 { 3099 int i; 3100 3101 /* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000). 3102 * 3103 * - short range 0: 3104 * SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM 3105 */ 3106 u64 hbw_range_min_short[] = { 3107 SPI_FLASH_BASE_ADDR 3108 }; 3109 u64 hbw_range_max_short[] = { 3110 PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE 3111 }; 3112 3113 for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) { 3114 gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i], 3115 hbw_range_max_short[i]); 3116 } 3117 } 3118 3119 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base, 3120 struct rr_config *rr_cfg) 3121 { 3122 u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset; 3123 3124 switch (rr_cfg->type) { 3125 case RR_TYPE_LONG: 3126 min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET; 3127 min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET; 3128 max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET; 3129 max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET; 3130 break; 3131 3132 case RR_TYPE_LONG_PRIV: 3133 min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET; 3134 min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET; 3135 max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET; 3136 max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET; 3137 break; 3138 3139 default: 3140 dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type); 3141 return; 3142 } 3143 3144 min_lo_reg_offset += rr_cfg->index * sizeof(u32); 3145 min_hi_reg_offset += rr_cfg->index * sizeof(u32); 3146 max_lo_reg_offset += rr_cfg->index * sizeof(u32); 3147 max_hi_reg_offset += rr_cfg->index * sizeof(u32); 3148 3149 /* Configure MMU RR (address bits [63:0]) */ 3150 WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min)); 3151 WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min)); 3152 WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max)); 3153 WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max)); 3154 } 3155 3156 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev) 3157 { 3158 u32 dcore_id, hmmu_id, hmmu_base; 3159 struct rr_config rr_cfg; 3160 3161 /* Up to 8 ranges [63:0]. 3162 * 3163 * - range 0: Reserved HBM area for F/W and driver 3164 */ 3165 3166 /* The RRs are located after the HMMU so need to use the scrambled addresses */ 3167 rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE); 3168 rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address); 3169 rr_cfg.index = 0; 3170 rr_cfg.type = RR_TYPE_LONG; 3171 3172 for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) { 3173 for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) { 3174 if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id)) 3175 continue; 3176 3177 hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET + 3178 hmmu_id * DCORE_HMMU_OFFSET; 3179 3180 gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg); 3181 } 3182 } 3183 } 3184 3185 /** 3186 * gaudi2_init_range_registers - 3187 * Initialize range registers of all initiators 3188 * 3189 * @hdev: pointer to hl_device structure 3190 */ 3191 static void gaudi2_init_range_registers(struct hl_device *hdev) 3192 { 3193 gaudi2_init_lbw_range_registers(hdev); 3194 gaudi2_init_hbw_range_registers(hdev); 3195 gaudi2_init_mmu_range_registers(hdev); 3196 } 3197 3198 /** 3199 * gaudi2_init_protection_bits - 3200 * Initialize protection bits of specific registers 3201 * 3202 * @hdev: pointer to hl_device structure 3203 * 3204 * All protection bits are 1 by default, means not protected. Need to set to 0 3205 * each bit that belongs to a protected register. 3206 * 3207 */ 3208 static int gaudi2_init_protection_bits(struct hl_device *hdev) 3209 { 3210 struct asic_fixed_properties *prop = &hdev->asic_prop; 3211 u32 instance_offset; 3212 int rc = 0; 3213 u8 i; 3214 3215 /* SFT */ 3216 instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE; 3217 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, 3218 gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0), 3219 NULL, HL_PB_NA); 3220 3221 /* HIF */ 3222 instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE; 3223 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3224 NUM_OF_HIF_PER_DCORE, instance_offset, 3225 gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif), 3226 NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask); 3227 3228 /* RTR */ 3229 instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE; 3230 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, 3231 gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0), 3232 NULL, HL_PB_NA); 3233 3234 /* HMMU */ 3235 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3236 NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET, 3237 gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0), 3238 NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask); 3239 3240 /* CPU. 3241 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected 3242 * by privileged RR. 3243 */ 3244 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3245 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3246 gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if), 3247 NULL, HL_PB_NA); 3248 3249 if (!hdev->asic_prop.fw_security_enabled) 3250 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3251 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3252 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu), 3253 NULL, HL_PB_NA); 3254 3255 /* KDMA */ 3256 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3257 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3258 gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma), 3259 NULL, HL_PB_NA); 3260 3261 /* PDMA */ 3262 instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE; 3263 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset, 3264 gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0), 3265 gaudi2_pb_pdma0_unsecured_regs, 3266 ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs)); 3267 3268 /* ARC PDMA */ 3269 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2, 3270 instance_offset, gaudi2_pb_pdma0_arc, 3271 ARRAY_SIZE(gaudi2_pb_pdma0_arc), 3272 gaudi2_pb_pdma0_arc_unsecured_regs, 3273 ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs)); 3274 3275 /* EDMA */ 3276 instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE; 3277 rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, 3278 instance_offset, gaudi2_pb_dcr0_edma0, 3279 ARRAY_SIZE(gaudi2_pb_dcr0_edma0), 3280 gaudi2_pb_dcr0_edma0_unsecured_regs, 3281 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs), 3282 prop->edma_enabled_mask); 3283 3284 /* ARC EDMA */ 3285 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, 3286 instance_offset, gaudi2_pb_dcr0_edma0_arc, 3287 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc), 3288 gaudi2_pb_dcr0_edma0_arc_unsecured_regs, 3289 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs), 3290 prop->edma_enabled_mask); 3291 3292 /* MME */ 3293 instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE; 3294 3295 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { 3296 /* MME SBTE */ 3297 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5, 3298 instance_offset, gaudi2_pb_dcr0_mme_sbte, 3299 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL, 3300 HL_PB_NA); 3301 3302 /* MME */ 3303 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 3304 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3305 gaudi2_pb_dcr0_mme_eng, 3306 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng), 3307 gaudi2_pb_dcr0_mme_eng_unsecured_regs, 3308 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs)); 3309 } 3310 3311 /* 3312 * we have special iteration for case in which we would like to 3313 * configure stubbed MME's ARC/QMAN 3314 */ 3315 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { 3316 /* MME QM */ 3317 rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 3318 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3319 gaudi2_pb_dcr0_mme_qm, 3320 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm), 3321 gaudi2_pb_dcr0_mme_qm_unsecured_regs, 3322 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs)); 3323 3324 /* ARC MME */ 3325 rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i), 3326 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3327 gaudi2_pb_dcr0_mme_arc, 3328 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc), 3329 gaudi2_pb_dcr0_mme_arc_unsecured_regs, 3330 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs)); 3331 } 3332 3333 /* MME QM ARC ACP ENG */ 3334 rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3335 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3336 gaudi2_pb_mme_qm_arc_acp_eng, 3337 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng), 3338 gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs, 3339 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs), 3340 (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1)); 3341 3342 /* TPC */ 3343 rc |= gaudi2_init_pb_tpc(hdev); 3344 rc |= gaudi2_init_pb_tpc_arc(hdev); 3345 3346 /* SRAM */ 3347 instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE; 3348 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, 3349 gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0), 3350 NULL, HL_PB_NA); 3351 3352 /* Sync Manager MSTR IF */ 3353 rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3354 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3355 gaudi2_pb_dcr0_sm_mstr_if, 3356 ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if), 3357 NULL, HL_PB_NA); 3358 3359 /* Sync Manager GLBL */ 3360 3361 /* Unsecure all CQ registers */ 3362 rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3363 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3364 gaudi2_pb_dcr0_sm_glbl, 3365 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl), 3366 gaudi2_pb_dcr_x_sm_glbl_unsecured_regs, 3367 ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs)); 3368 3369 /* Secure Dcore0 CQ0 registers */ 3370 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 3371 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3372 gaudi2_pb_dcr0_sm_glbl, 3373 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl), 3374 gaudi2_pb_dcr0_sm_glbl_unsecured_regs, 3375 ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs)); 3376 3377 /* PSOC. 3378 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are 3379 * protected by privileged RR. 3380 */ 3381 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3382 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3383 gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf), 3384 NULL, HL_PB_NA); 3385 3386 if (!hdev->asic_prop.fw_security_enabled) 3387 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3388 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3389 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc), 3390 NULL, HL_PB_NA); 3391 3392 /* PMMU */ 3393 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3394 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3395 gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu), 3396 NULL, HL_PB_NA); 3397 3398 /* PLL. 3399 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by 3400 * privileged RR. 3401 */ 3402 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3403 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3404 gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll), 3405 NULL, HL_PB_NA); 3406 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3407 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3408 gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll), 3409 NULL, HL_PB_NA); 3410 3411 if (!hdev->asic_prop.fw_security_enabled) { 3412 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3413 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3414 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll), 3415 NULL, HL_PB_NA); 3416 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3417 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3418 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll), 3419 NULL, HL_PB_NA); 3420 } 3421 3422 /* PCIE */ 3423 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 3424 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3425 gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie), 3426 gaudi2_pb_pcie_unsecured_regs, 3427 ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs)); 3428 3429 /* Thermal Sensor. 3430 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR. 3431 */ 3432 if (!hdev->asic_prop.fw_security_enabled) { 3433 instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE; 3434 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, 3435 gaudi2_pb_thermal_sensor0, 3436 ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA); 3437 } 3438 3439 /* HBM */ 3440 /* Temporarily skip until SW-63348 is solved 3441 * instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE; 3442 * rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM, 3443 * instance_offset, gaudi2_pb_hbm, 3444 * ARRAY_SIZE(gaudi2_pb_hbm), NULL, HL_PB_NA, 3445 * prop->dram_enabled_mask); 3446 */ 3447 3448 /* Scheduler ARCs */ 3449 instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE; 3450 rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 3451 NUM_OF_ARC_FARMS_ARC, 3452 instance_offset, gaudi2_pb_arc_sched, 3453 ARRAY_SIZE(gaudi2_pb_arc_sched), 3454 gaudi2_pb_arc_sched_unsecured_regs, 3455 ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs)); 3456 3457 /* XBAR MIDs */ 3458 instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE; 3459 rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, 3460 instance_offset, gaudi2_pb_xbar_mid, 3461 ARRAY_SIZE(gaudi2_pb_xbar_mid), 3462 gaudi2_pb_xbar_mid_unsecured_regs, 3463 ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs)); 3464 3465 /* XBAR EDGEs */ 3466 instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE; 3467 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, 3468 instance_offset, gaudi2_pb_xbar_edge, 3469 ARRAY_SIZE(gaudi2_pb_xbar_edge), 3470 gaudi2_pb_xbar_edge_unsecured_regs, 3471 ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs), 3472 prop->xbar_edge_enabled_mask); 3473 3474 /* NIC */ 3475 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, 3476 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3477 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), 3478 NULL, HL_PB_NA, hdev->nic_ports_mask); 3479 3480 /* NIC QM and QPC */ 3481 rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, 3482 NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET, 3483 gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc), 3484 gaudi2_pb_nic0_qm_qpc_unsecured_regs, 3485 ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs), 3486 hdev->nic_ports_mask); 3487 3488 /* NIC QM ARC */ 3489 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS, 3490 NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET, 3491 gaudi2_pb_nic0_qm_arc_aux0, 3492 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), 3493 gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs, 3494 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs), 3495 hdev->nic_ports_mask); 3496 3497 /* NIC UMR */ 3498 rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS, 3499 NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET, 3500 gaudi2_pb_nic0_umr, 3501 ARRAY_SIZE(gaudi2_pb_nic0_umr), 3502 gaudi2_pb_nic0_umr_unsecured_regs, 3503 ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs), 3504 hdev->nic_ports_mask); 3505 3506 /* Rotators */ 3507 instance_offset = mmROT1_BASE - mmROT0_BASE; 3508 rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, 3509 instance_offset, gaudi2_pb_rot0, 3510 ARRAY_SIZE(gaudi2_pb_rot0), 3511 gaudi2_pb_rot0_unsecured_regs, 3512 ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs), 3513 (BIT(NUM_OF_ROT) - 1)); 3514 3515 /* Rotators ARCS */ 3516 rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED, 3517 HL_PB_NA, NUM_OF_ROT, instance_offset, 3518 gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), 3519 gaudi2_pb_rot0_arc_unsecured_regs, 3520 ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs), 3521 (BIT(NUM_OF_ROT) - 1)); 3522 3523 rc |= gaudi2_init_pb_sm_objs(hdev); 3524 3525 return rc; 3526 } 3527 3528 /** 3529 * gaudi2_init_security - Initialize security model 3530 * 3531 * @hdev: pointer to hl_device structure 3532 * 3533 * Initialize the security model of the device 3534 * That includes range registers and protection bit per register. 3535 */ 3536 int gaudi2_init_security(struct hl_device *hdev) 3537 { 3538 int rc; 3539 3540 rc = gaudi2_init_protection_bits(hdev); 3541 if (rc) 3542 return rc; 3543 3544 gaudi2_init_range_registers(hdev); 3545 3546 return 0; 3547 } 3548 3549 struct gaudi2_ack_pb_tpc_data { 3550 u32 tpc_regs_array_size; 3551 u32 arc_tpc_regs_array_size; 3552 }; 3553 3554 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset, 3555 struct iterate_module_ctx *ctx) 3556 { 3557 struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data; 3558 3559 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3560 gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size); 3561 3562 hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3563 gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size); 3564 } 3565 3566 static void gaudi2_ack_pb_tpc(struct hl_device *hdev) 3567 { 3568 struct iterate_module_ctx tpc_iter = { 3569 .fn = &gaudi2_ack_pb_tpc_config, 3570 }; 3571 struct gaudi2_ack_pb_tpc_data data; 3572 3573 data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0); 3574 data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc); 3575 tpc_iter.data = &data; 3576 3577 gaudi2_iterate_tpcs(hdev, &tpc_iter); 3578 } 3579 3580 /** 3581 * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits 3582 * and for every protection error found, display the appropriate error message 3583 * and clear the error. 3584 * 3585 * @hdev: pointer to hl_device structure 3586 * 3587 * All protection bits are 1 by default, means not protected. Need to set to 0 3588 * each bit that belongs to a protected register. 3589 * 3590 */ 3591 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev) 3592 { 3593 struct asic_fixed_properties *prop = &hdev->asic_prop; 3594 u32 instance_offset; 3595 u8 i; 3596 3597 /* SFT */ 3598 instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE; 3599 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, 3600 gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0)); 3601 3602 /* HIF */ 3603 instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE; 3604 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3605 NUM_OF_HIF_PER_DCORE, instance_offset, 3606 gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif), 3607 prop->hmmu_hif_enabled_mask); 3608 3609 /* RTR */ 3610 instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE; 3611 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, 3612 gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0)); 3613 3614 /* HMMU */ 3615 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3616 NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET, 3617 gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0), 3618 prop->hmmu_hif_enabled_mask); 3619 3620 /* CPU. 3621 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected 3622 * by privileged RR. 3623 */ 3624 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3625 gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if)); 3626 if (!hdev->asic_prop.fw_security_enabled) 3627 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3628 gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu)); 3629 3630 /* KDMA */ 3631 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3632 gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma)); 3633 3634 /* PDMA */ 3635 instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE; 3636 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset, 3637 gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0)); 3638 3639 /* ARC PDMA */ 3640 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset, 3641 gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc)); 3642 3643 /* EDMA */ 3644 instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE; 3645 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, 3646 instance_offset, gaudi2_pb_dcr0_edma0, 3647 ARRAY_SIZE(gaudi2_pb_dcr0_edma0), 3648 prop->edma_enabled_mask); 3649 3650 /* ARC EDMA */ 3651 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2, 3652 instance_offset, gaudi2_pb_dcr0_edma0_arc, 3653 ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc), 3654 prop->edma_enabled_mask); 3655 3656 /* MME */ 3657 instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE; 3658 3659 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { 3660 /* MME SBTE */ 3661 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5, 3662 instance_offset, gaudi2_pb_dcr0_mme_sbte, 3663 ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte)); 3664 3665 /* MME */ 3666 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 3667 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3668 gaudi2_pb_dcr0_mme_eng, 3669 ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng)); 3670 } 3671 3672 /* 3673 * we have special iteration for case in which we would like to 3674 * configure stubbed MME's ARC/QMAN 3675 */ 3676 for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) { 3677 /* MME QM */ 3678 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 3679 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3680 gaudi2_pb_dcr0_mme_qm, 3681 ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm)); 3682 3683 /* ARC MME */ 3684 hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 3685 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3686 gaudi2_pb_dcr0_mme_arc, 3687 ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc)); 3688 } 3689 3690 /* MME QM ARC ACP ENG */ 3691 hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 3692 HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3693 gaudi2_pb_mme_qm_arc_acp_eng, 3694 ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng), 3695 (BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1)); 3696 3697 /* TPC */ 3698 gaudi2_ack_pb_tpc(hdev); 3699 3700 /* SRAM */ 3701 instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE; 3702 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset, 3703 gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0)); 3704 3705 /* Sync Manager MSTR IF */ 3706 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3707 gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if)); 3708 3709 /* Sync Manager */ 3710 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3711 gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl)); 3712 3713 hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3714 gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if)); 3715 3716 /* PSOC. 3717 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are 3718 * protected by privileged RR. 3719 */ 3720 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3721 gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf)); 3722 if (!hdev->asic_prop.fw_security_enabled) 3723 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3724 gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc)); 3725 3726 /* PMMU */ 3727 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3728 gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu)); 3729 3730 /* PLL. 3731 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by 3732 * privileged RR. 3733 */ 3734 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3735 gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll)); 3736 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3737 gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll)); 3738 if (!hdev->asic_prop.fw_security_enabled) { 3739 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3740 gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll)); 3741 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3742 gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll)); 3743 } 3744 3745 /* PCIE */ 3746 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3747 gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie)); 3748 3749 /* Thermal Sensor. 3750 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR. 3751 */ 3752 if (!hdev->asic_prop.fw_security_enabled) { 3753 instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE; 3754 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset, 3755 gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0)); 3756 } 3757 3758 /* HBM */ 3759 instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE; 3760 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM, 3761 instance_offset, gaudi2_pb_hbm, 3762 ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask); 3763 3764 /* Scheduler ARCs */ 3765 instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE; 3766 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC, 3767 instance_offset, gaudi2_pb_arc_sched, 3768 ARRAY_SIZE(gaudi2_pb_arc_sched)); 3769 3770 /* XBAR MIDs */ 3771 instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE; 3772 hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, 3773 instance_offset, gaudi2_pb_xbar_mid, 3774 ARRAY_SIZE(gaudi2_pb_xbar_mid)); 3775 3776 /* XBAR EDGEs */ 3777 instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE; 3778 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR, 3779 instance_offset, gaudi2_pb_xbar_edge, 3780 ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask); 3781 3782 /* NIC */ 3783 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA, 3784 gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask); 3785 3786 /* NIC QM and QPC */ 3787 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, 3788 NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc), 3789 hdev->nic_ports_mask); 3790 3791 /* NIC QM ARC */ 3792 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, 3793 NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0, 3794 ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask); 3795 3796 /* NIC UMR */ 3797 hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, 3798 NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr), 3799 hdev->nic_ports_mask); 3800 3801 /* Rotators */ 3802 instance_offset = mmROT1_BASE - mmROT0_BASE; 3803 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset, 3804 gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1)); 3805 3806 /* Rotators ARCS */ 3807 hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset, 3808 gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1)); 3809 } 3810 3811 /* 3812 * Print PB security errors 3813 */ 3814 3815 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause, 3816 u32 offended_addr) 3817 { 3818 int i = 0; 3819 const char *error_format = 3820 "Security error at block 0x%x, offending address 0x%x\n" 3821 "Cause 0x%x: %s %s %s %s %s %s %s %s\n"; 3822 char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" }; 3823 3824 if (!cause) 3825 return; 3826 3827 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD) 3828 mcause[i++] = "APB_PRIV_RD"; 3829 3830 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD) 3831 mcause[i++] = "APB_SEC_RD"; 3832 3833 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD) 3834 mcause[i++] = "APB_UNMAPPED_RD"; 3835 3836 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR) 3837 mcause[i++] = "APB_PRIV_WR"; 3838 3839 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR) 3840 mcause[i++] = "APB_SEC_WR"; 3841 3842 if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR) 3843 mcause[i++] = "APB_UNMAPPED_WR"; 3844 3845 if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR) 3846 mcause[i++] = "EXT_SEC_WR"; 3847 3848 if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR) 3849 mcause[i++] = "APB_EXT_UNMAPPED_WR"; 3850 3851 dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr, 3852 cause, mcause[0], mcause[1], mcause[2], mcause[3], 3853 mcause[4], mcause[5], mcause[6], mcause[7]); 3854 } 3855