xref: /openbmc/linux/drivers/accel/habanalabs/gaudi2/gaudi2_security.c (revision 583f12a80dfb7997d59a42e8642019695f5aa15a)
1 // SPDX-License-Identifier: GPL-2.0
2 
3 /*
4  * Copyright 2020-2022 HabanaLabs, Ltd.
5  * All Rights Reserved.
6  */
7 
8 #include "gaudi2P.h"
9 #include "../include/gaudi2/asic_reg/gaudi2_regs.h"
10 
11 #define UNSET_GLBL_SEC_BIT(array, b) ((array)[((b) / 32)] |= (1 << ((b) % 32)))
12 
13 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK
14 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK
15 #define SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK
16 #define SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK
17 #define SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK
18 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD \
19 		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK
20 #define SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR \
21 		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK
22 #define SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR \
23 		PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK
24 
25 /* LBW RR */
26 #define SFT_NUM_OF_LBW_RTR		1
27 #define SFT_LBW_RTR_OFFSET		0
28 #define RR_LBW_LONG_MASK		0x7FFFFFFull
29 #define RR_LBW_SHORT_MASK		0x7FFF000ull
30 
31 /* HBW RR */
32 #define SFT_NUM_OF_HBW_RTR		2
33 #define RR_HBW_SHORT_LO_MASK		0xFFFFFFFF000ull
34 #define RR_HBW_SHORT_HI_MASK		0xF00000000000ull
35 #define RR_HBW_LONG_LO_MASK		0xFFFFFFFF000ull
36 #define RR_HBW_LONG_HI_MASK		0xFFFFF00000000000ull
37 
38 struct rr_config {
39 	u64 min;
40 	u64 max;
41 	u32 index;
42 	u8 type;
43 };
44 
45 struct gaudi2_atypical_bp_blocks {
46 	u32 mm_block_base_addr;
47 	u32 block_size;
48 	u32 glbl_sec_offset;
49 	u32 glbl_sec_length;
50 };
51 
52 static const struct gaudi2_atypical_bp_blocks gaudi2_pb_dcr0_sm_objs = {
53 	mmDCORE0_SYNC_MNGR_OBJS_BASE,
54 	128 * 1024,
55 	SM_OBJS_PROT_BITS_OFFS,
56 	640
57 };
58 
59 static const u32 gaudi2_pb_sft0[] = {
60 	mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE,
61 	mmSFT0_HBW_RTR_IF0_RTR_H3_BASE,
62 	mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE,
63 	mmSFT0_HBW_RTR_IF0_ADDR_DEC_HBW_BASE,
64 	mmSFT0_HBW_RTR_IF1_RTR_CTRL_BASE,
65 	mmSFT0_HBW_RTR_IF1_RTR_H3_BASE,
66 	mmSFT0_HBW_RTR_IF1_MSTR_IF_RR_SHRD_HBW_BASE,
67 	mmSFT0_HBW_RTR_IF1_ADDR_DEC_HBW_BASE,
68 	mmSFT0_LBW_RTR_IF_RTR_CTRL_BASE,
69 	mmSFT0_LBW_RTR_IF_RTR_H3_BASE,
70 	mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_HBW_BASE,
71 	mmSFT0_LBW_RTR_IF_ADDR_DEC_HBW_BASE,
72 	mmSFT0_BASE,
73 };
74 
75 static const u32 gaudi2_pb_dcr0_hif[] = {
76 	mmDCORE0_HIF0_BASE,
77 };
78 
79 static const u32 gaudi2_pb_dcr0_rtr0[] = {
80 	mmDCORE0_RTR0_CTRL_BASE,
81 	mmDCORE0_RTR0_H3_BASE,
82 	mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE,
83 	mmDCORE0_RTR0_ADD_DEC_HBW_BASE,
84 	mmDCORE0_RTR0_BASE,
85 	mmDCORE0_RTR0_DBG_ADDR_BASE,
86 };
87 
88 static const u32 gaudi2_pb_dcr0_hmmu0[] = {
89 	mmDCORE0_HMMU0_MMU_BASE,
90 	mmDCORE0_HMMU0_MSTR_IF_RR_SHRD_HBW_BASE,
91 	mmDCORE0_HMMU0_SCRAMB_OUT_BASE,
92 	mmDCORE0_HMMU0_STLB_BASE,
93 };
94 
95 static const u32 gaudi2_pb_cpu_if[] = {
96 	mmCPU_IF_BASE,
97 };
98 
99 static const u32 gaudi2_pb_cpu[] = {
100 	mmCPU_CA53_CFG_BASE,
101 	mmCPU_MSTR_IF_RR_SHRD_HBW_BASE,
102 };
103 
104 static const u32 gaudi2_pb_kdma[] = {
105 	mmARC_FARM_KDMA_BASE,
106 	mmARC_FARM_KDMA_MSTR_IF_RR_SHRD_HBW_BASE,
107 };
108 
109 static const u32 gaudi2_pb_pdma0[] = {
110 	mmPDMA0_CORE_BASE,
111 	mmPDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
112 	mmPDMA0_QM_BASE,
113 };
114 
115 static const u32 gaudi2_pb_pdma0_arc[] = {
116 	mmPDMA0_QM_ARC_AUX_BASE,
117 };
118 
119 static const struct range gaudi2_pb_pdma0_arc_unsecured_regs[] = {
120 	{mmPDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmPDMA0_QM_ARC_AUX_RUN_HALT_ACK},
121 	{mmPDMA0_QM_ARC_AUX_CLUSTER_NUM, mmPDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
122 	{mmPDMA0_QM_ARC_AUX_ARC_RST_REQ, mmPDMA0_QM_ARC_AUX_CID_OFFSET_7},
123 	{mmPDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmPDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
124 	{mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
125 	{mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmPDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
126 	{mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmPDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
127 	{mmPDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmPDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
128 	{mmPDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmPDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
129 };
130 
131 static const u32 gaudi2_pb_pdma0_unsecured_regs[] = {
132 	mmPDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
133 	mmPDMA0_CORE_CTX_WR_COMP_ADDR_HI,
134 	mmPDMA0_CORE_CTX_WR_COMP_ADDR_LO,
135 	mmPDMA0_CORE_CTX_WR_COMP_WDATA,
136 	mmPDMA0_CORE_CTX_SRC_BASE_LO,
137 	mmPDMA0_CORE_CTX_SRC_BASE_HI,
138 	mmPDMA0_CORE_CTX_DST_BASE_LO,
139 	mmPDMA0_CORE_CTX_DST_BASE_HI,
140 	mmPDMA0_CORE_CTX_SRC_TSIZE_0,
141 	mmPDMA0_CORE_CTX_SRC_TSIZE_1,
142 	mmPDMA0_CORE_CTX_SRC_TSIZE_2,
143 	mmPDMA0_CORE_CTX_SRC_TSIZE_3,
144 	mmPDMA0_CORE_CTX_SRC_TSIZE_4,
145 	mmPDMA0_CORE_CTX_SRC_STRIDE_1,
146 	mmPDMA0_CORE_CTX_SRC_STRIDE_2,
147 	mmPDMA0_CORE_CTX_SRC_STRIDE_3,
148 	mmPDMA0_CORE_CTX_SRC_STRIDE_4,
149 	mmPDMA0_CORE_CTX_SRC_OFFSET_LO,
150 	mmPDMA0_CORE_CTX_SRC_OFFSET_HI,
151 	mmPDMA0_CORE_CTX_DST_TSIZE_0,
152 	mmPDMA0_CORE_CTX_DST_TSIZE_1,
153 	mmPDMA0_CORE_CTX_DST_TSIZE_2,
154 	mmPDMA0_CORE_CTX_DST_TSIZE_3,
155 	mmPDMA0_CORE_CTX_DST_TSIZE_4,
156 	mmPDMA0_CORE_CTX_DST_STRIDE_1,
157 	mmPDMA0_CORE_CTX_DST_STRIDE_2,
158 	mmPDMA0_CORE_CTX_DST_STRIDE_3,
159 	mmPDMA0_CORE_CTX_DST_STRIDE_4,
160 	mmPDMA0_CORE_CTX_DST_OFFSET_LO,
161 	mmPDMA0_CORE_CTX_DST_OFFSET_HI,
162 	mmPDMA0_CORE_CTX_COMMIT,
163 	mmPDMA0_CORE_CTX_CTRL,
164 	mmPDMA0_CORE_CTX_TE_NUMROWS,
165 	mmPDMA0_CORE_CTX_IDX,
166 	mmPDMA0_CORE_CTX_IDX_INC,
167 	mmPDMA0_QM_CQ_CFG0_0,
168 	mmPDMA0_QM_CQ_CFG0_1,
169 	mmPDMA0_QM_CQ_CFG0_2,
170 	mmPDMA0_QM_CQ_CFG0_3,
171 	mmPDMA0_QM_CQ_CFG0_4,
172 	mmPDMA0_QM_CP_FENCE0_RDATA_0,
173 	mmPDMA0_QM_CP_FENCE0_RDATA_1,
174 	mmPDMA0_QM_CP_FENCE0_RDATA_2,
175 	mmPDMA0_QM_CP_FENCE0_RDATA_3,
176 	mmPDMA0_QM_CP_FENCE0_RDATA_4,
177 	mmPDMA0_QM_CP_FENCE1_RDATA_0,
178 	mmPDMA0_QM_CP_FENCE1_RDATA_1,
179 	mmPDMA0_QM_CP_FENCE1_RDATA_2,
180 	mmPDMA0_QM_CP_FENCE1_RDATA_3,
181 	mmPDMA0_QM_CP_FENCE1_RDATA_4,
182 	mmPDMA0_QM_CP_FENCE2_RDATA_0,
183 	mmPDMA0_QM_CP_FENCE2_RDATA_1,
184 	mmPDMA0_QM_CP_FENCE2_RDATA_2,
185 	mmPDMA0_QM_CP_FENCE2_RDATA_3,
186 	mmPDMA0_QM_CP_FENCE2_RDATA_4,
187 	mmPDMA0_QM_CP_FENCE3_RDATA_0,
188 	mmPDMA0_QM_CP_FENCE3_RDATA_1,
189 	mmPDMA0_QM_CP_FENCE3_RDATA_2,
190 	mmPDMA0_QM_CP_FENCE3_RDATA_3,
191 	mmPDMA0_QM_CP_FENCE3_RDATA_4,
192 	mmPDMA0_QM_CP_FENCE0_CNT_0,
193 	mmPDMA0_QM_CP_FENCE0_CNT_1,
194 	mmPDMA0_QM_CP_FENCE0_CNT_2,
195 	mmPDMA0_QM_CP_FENCE0_CNT_3,
196 	mmPDMA0_QM_CP_FENCE0_CNT_4,
197 	mmPDMA0_QM_CP_FENCE1_CNT_0,
198 	mmPDMA0_QM_CP_FENCE1_CNT_1,
199 	mmPDMA0_QM_CP_FENCE1_CNT_2,
200 	mmPDMA0_QM_CP_FENCE1_CNT_3,
201 	mmPDMA0_QM_CP_FENCE1_CNT_4,
202 	mmPDMA0_QM_CP_FENCE2_CNT_0,
203 	mmPDMA0_QM_CP_FENCE2_CNT_1,
204 	mmPDMA0_QM_CP_FENCE2_CNT_2,
205 	mmPDMA0_QM_CP_FENCE2_CNT_3,
206 	mmPDMA0_QM_CP_FENCE2_CNT_4,
207 	mmPDMA0_QM_CP_FENCE3_CNT_0,
208 	mmPDMA0_QM_CP_FENCE3_CNT_1,
209 	mmPDMA0_QM_CP_FENCE3_CNT_2,
210 	mmPDMA0_QM_CP_FENCE3_CNT_3,
211 	mmPDMA0_QM_CP_FENCE3_CNT_4,
212 	mmPDMA0_QM_CQ_PTR_LO_0,
213 	mmPDMA0_QM_CQ_PTR_HI_0,
214 	mmPDMA0_QM_CQ_TSIZE_0,
215 	mmPDMA0_QM_CQ_CTL_0,
216 	mmPDMA0_QM_CQ_PTR_LO_1,
217 	mmPDMA0_QM_CQ_PTR_HI_1,
218 	mmPDMA0_QM_CQ_TSIZE_1,
219 	mmPDMA0_QM_CQ_CTL_1,
220 	mmPDMA0_QM_CQ_PTR_LO_2,
221 	mmPDMA0_QM_CQ_PTR_HI_2,
222 	mmPDMA0_QM_CQ_TSIZE_2,
223 	mmPDMA0_QM_CQ_CTL_2,
224 	mmPDMA0_QM_CQ_PTR_LO_3,
225 	mmPDMA0_QM_CQ_PTR_HI_3,
226 	mmPDMA0_QM_CQ_TSIZE_3,
227 	mmPDMA0_QM_CQ_CTL_3,
228 	mmPDMA0_QM_CQ_PTR_LO_4,
229 	mmPDMA0_QM_CQ_PTR_HI_4,
230 	mmPDMA0_QM_CQ_TSIZE_4,
231 	mmPDMA0_QM_CQ_CTL_4,
232 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
233 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
234 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
235 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
236 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
237 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
238 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
239 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
240 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
241 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
242 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
243 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
244 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
245 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
246 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
247 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
248 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
249 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
250 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
251 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
252 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
253 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
254 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
255 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
256 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
257 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
258 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
259 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
260 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
261 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
262 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
263 	mmPDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
264 	mmPDMA0_QM_ARC_CQ_PTR_LO,
265 	mmPDMA0_QM_ARC_CQ_PTR_LO_STS,
266 	mmPDMA0_QM_ARC_CQ_PTR_HI,
267 	mmPDMA0_QM_ARC_CQ_PTR_HI_STS,
268 	mmPDMA0_QM_ARB_CFG_0,
269 	mmPDMA0_QM_ARB_MST_QUIET_PER,
270 	mmPDMA0_QM_ARB_CHOICE_Q_PUSH,
271 	mmPDMA0_QM_ARB_WRR_WEIGHT_0,
272 	mmPDMA0_QM_ARB_WRR_WEIGHT_1,
273 	mmPDMA0_QM_ARB_WRR_WEIGHT_2,
274 	mmPDMA0_QM_ARB_WRR_WEIGHT_3,
275 	mmPDMA0_QM_ARB_BASE_LO,
276 	mmPDMA0_QM_ARB_BASE_HI,
277 	mmPDMA0_QM_ARB_MST_SLAVE_EN,
278 	mmPDMA0_QM_ARB_MST_SLAVE_EN_1,
279 	mmPDMA0_QM_ARB_MST_CRED_INC,
280 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
281 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
282 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
283 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
284 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
285 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
286 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
287 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
288 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
289 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
290 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
291 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
292 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
293 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
294 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
295 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
296 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
297 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
298 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
299 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
300 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
301 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
302 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
303 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
304 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
305 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
306 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
307 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
308 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
309 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
310 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
311 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
312 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
313 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
314 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
315 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
316 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
317 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
318 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
319 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
320 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
321 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
322 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
323 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
324 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
325 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
326 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
327 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
328 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
329 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
330 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
331 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
332 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
333 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
334 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
335 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
336 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
337 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
338 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
339 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
340 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
341 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
342 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
343 	mmPDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
344 	mmPDMA0_QM_ARB_SLV_ID,
345 	mmPDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
346 	mmPDMA0_QM_ARC_CQ_CFG0,
347 	mmPDMA0_QM_CQ_IFIFO_CI_0,
348 	mmPDMA0_QM_CQ_IFIFO_CI_1,
349 	mmPDMA0_QM_CQ_IFIFO_CI_2,
350 	mmPDMA0_QM_CQ_IFIFO_CI_3,
351 	mmPDMA0_QM_CQ_IFIFO_CI_4,
352 	mmPDMA0_QM_ARC_CQ_IFIFO_CI,
353 	mmPDMA0_QM_CQ_CTL_CI_0,
354 	mmPDMA0_QM_CQ_CTL_CI_1,
355 	mmPDMA0_QM_CQ_CTL_CI_2,
356 	mmPDMA0_QM_CQ_CTL_CI_3,
357 	mmPDMA0_QM_CQ_CTL_CI_4,
358 	mmPDMA0_QM_ARC_CQ_CTL_CI,
359 	mmPDMA0_QM_ARC_CQ_TSIZE,
360 	mmPDMA0_QM_ARC_CQ_CTL,
361 	mmPDMA0_QM_CP_SWITCH_WD_SET,
362 	mmPDMA0_QM_CP_EXT_SWITCH,
363 	mmPDMA0_QM_CP_PRED_0,
364 	mmPDMA0_QM_CP_PRED_1,
365 	mmPDMA0_QM_CP_PRED_2,
366 	mmPDMA0_QM_CP_PRED_3,
367 	mmPDMA0_QM_CP_PRED_4,
368 	mmPDMA0_QM_CP_PRED_UPEN_0,
369 	mmPDMA0_QM_CP_PRED_UPEN_1,
370 	mmPDMA0_QM_CP_PRED_UPEN_2,
371 	mmPDMA0_QM_CP_PRED_UPEN_3,
372 	mmPDMA0_QM_CP_PRED_UPEN_4,
373 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
374 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
375 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
376 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
377 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
378 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
379 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
380 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
381 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
382 	mmPDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
383 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
384 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
385 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
386 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
387 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
388 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
389 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
390 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
391 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
392 	mmPDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
393 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
394 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
395 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
396 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
397 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
398 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
399 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
400 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
401 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
402 	mmPDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
403 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
404 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
405 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
406 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
407 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
408 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
409 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
410 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
411 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
412 	mmPDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
413 	mmPDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
414 	mmPDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
415 	mmPDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
416 	mmPDMA0_QM_CQ_CTL_MSG_BASE_LO
417 };
418 
419 static const u32 gaudi2_pb_dcr0_edma0[] = {
420 	mmDCORE0_EDMA0_CORE_BASE,
421 	mmDCORE0_EDMA0_MSTR_IF_RR_SHRD_HBW_BASE,
422 	mmDCORE0_EDMA0_QM_BASE,
423 };
424 
425 static const u32 gaudi2_pb_dcr0_edma0_arc[] = {
426 	mmDCORE0_EDMA0_QM_ARC_AUX_BASE,
427 };
428 
429 static const struct range gaudi2_pb_dcr0_edma0_arc_unsecured_regs[] = {
430 	{mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_RUN_HALT_ACK},
431 	{mmDCORE0_EDMA0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_EDMA0_QM_ARC_AUX_WAKE_UP_EVENT},
432 	{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_EDMA0_QM_ARC_AUX_CID_OFFSET_7},
433 	{mmDCORE0_EDMA0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_EDMA0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
434 	{mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN,
435 		mmDCORE0_EDMA0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
436 	{mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN,
437 		mmDCORE0_EDMA0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
438 	{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
439 		mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
440 	{mmDCORE0_EDMA0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
441 		mmDCORE0_EDMA0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
442 	{mmDCORE0_EDMA0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
443 		mmDCORE0_EDMA0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
444 };
445 
446 static const u32 gaudi2_pb_dcr0_edma0_unsecured_regs[] = {
447 	mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_WR_REDUCTION,
448 	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_HI,
449 	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_ADDR_LO,
450 	mmDCORE0_EDMA0_CORE_CTX_WR_COMP_WDATA,
451 	mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_LO,
452 	mmDCORE0_EDMA0_CORE_CTX_SRC_BASE_HI,
453 	mmDCORE0_EDMA0_CORE_CTX_DST_BASE_LO,
454 	mmDCORE0_EDMA0_CORE_CTX_DST_BASE_HI,
455 	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_0,
456 	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_1,
457 	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_2,
458 	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_3,
459 	mmDCORE0_EDMA0_CORE_CTX_SRC_TSIZE_4,
460 	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_1,
461 	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_2,
462 	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_3,
463 	mmDCORE0_EDMA0_CORE_CTX_SRC_STRIDE_4,
464 	mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_LO,
465 	mmDCORE0_EDMA0_CORE_CTX_SRC_OFFSET_HI,
466 	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_0,
467 	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_1,
468 	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_2,
469 	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_3,
470 	mmDCORE0_EDMA0_CORE_CTX_DST_TSIZE_4,
471 	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_1,
472 	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_2,
473 	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_3,
474 	mmDCORE0_EDMA0_CORE_CTX_DST_STRIDE_4,
475 	mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_LO,
476 	mmDCORE0_EDMA0_CORE_CTX_DST_OFFSET_HI,
477 	mmDCORE0_EDMA0_CORE_CTX_COMMIT,
478 	mmDCORE0_EDMA0_CORE_CTX_CTRL,
479 	mmDCORE0_EDMA0_CORE_CTX_TE_NUMROWS,
480 	mmDCORE0_EDMA0_CORE_CTX_IDX,
481 	mmDCORE0_EDMA0_CORE_CTX_IDX_INC,
482 	mmDCORE0_EDMA0_CORE_RD_LBW_RATE_LIM_CFG,
483 	mmDCORE0_EDMA0_QM_CQ_CFG0_0,
484 	mmDCORE0_EDMA0_QM_CQ_CFG0_1,
485 	mmDCORE0_EDMA0_QM_CQ_CFG0_2,
486 	mmDCORE0_EDMA0_QM_CQ_CFG0_3,
487 	mmDCORE0_EDMA0_QM_CQ_CFG0_4,
488 	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_0,
489 	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_1,
490 	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_2,
491 	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_3,
492 	mmDCORE0_EDMA0_QM_CP_FENCE0_RDATA_4,
493 	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_0,
494 	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_1,
495 	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_2,
496 	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_3,
497 	mmDCORE0_EDMA0_QM_CP_FENCE1_RDATA_4,
498 	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_0,
499 	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_1,
500 	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_2,
501 	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_3,
502 	mmDCORE0_EDMA0_QM_CP_FENCE2_RDATA_4,
503 	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_0,
504 	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_1,
505 	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_2,
506 	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_3,
507 	mmDCORE0_EDMA0_QM_CP_FENCE3_RDATA_4,
508 	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_0,
509 	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_1,
510 	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_2,
511 	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_3,
512 	mmDCORE0_EDMA0_QM_CP_FENCE0_CNT_4,
513 	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_0,
514 	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_1,
515 	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_2,
516 	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_3,
517 	mmDCORE0_EDMA0_QM_CP_FENCE1_CNT_4,
518 	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_0,
519 	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_1,
520 	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_2,
521 	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_3,
522 	mmDCORE0_EDMA0_QM_CP_FENCE2_CNT_4,
523 	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_0,
524 	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_1,
525 	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_2,
526 	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_3,
527 	mmDCORE0_EDMA0_QM_CP_FENCE3_CNT_4,
528 	mmDCORE0_EDMA0_QM_CQ_PTR_LO_0,
529 	mmDCORE0_EDMA0_QM_CQ_PTR_HI_0,
530 	mmDCORE0_EDMA0_QM_CQ_TSIZE_0,
531 	mmDCORE0_EDMA0_QM_CQ_CTL_0,
532 	mmDCORE0_EDMA0_QM_CQ_PTR_LO_1,
533 	mmDCORE0_EDMA0_QM_CQ_PTR_HI_1,
534 	mmDCORE0_EDMA0_QM_CQ_TSIZE_1,
535 	mmDCORE0_EDMA0_QM_CQ_CTL_1,
536 	mmDCORE0_EDMA0_QM_CQ_PTR_LO_2,
537 	mmDCORE0_EDMA0_QM_CQ_PTR_HI_2,
538 	mmDCORE0_EDMA0_QM_CQ_TSIZE_2,
539 	mmDCORE0_EDMA0_QM_CQ_CTL_2,
540 	mmDCORE0_EDMA0_QM_CQ_PTR_LO_3,
541 	mmDCORE0_EDMA0_QM_CQ_PTR_HI_3,
542 	mmDCORE0_EDMA0_QM_CQ_TSIZE_3,
543 	mmDCORE0_EDMA0_QM_CQ_CTL_3,
544 	mmDCORE0_EDMA0_QM_CQ_PTR_LO_4,
545 	mmDCORE0_EDMA0_QM_CQ_PTR_HI_4,
546 	mmDCORE0_EDMA0_QM_CQ_TSIZE_4,
547 	mmDCORE0_EDMA0_QM_CQ_CTL_4,
548 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE,
549 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
550 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE,
551 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
552 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE,
553 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
554 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE,
555 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
556 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE,
557 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
558 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE,
559 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
560 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE,
561 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
562 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE,
563 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
564 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE,
565 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
566 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE,
567 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
568 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE,
569 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
570 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE,
571 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
572 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE,
573 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
574 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE,
575 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
576 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE,
577 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
578 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE,
579 	mmDCORE0_EDMA0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
580 	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO,
581 	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_LO_STS,
582 	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI,
583 	mmDCORE0_EDMA0_QM_ARC_CQ_PTR_HI_STS,
584 	mmDCORE0_EDMA0_QM_ARB_CFG_0,
585 	mmDCORE0_EDMA0_QM_ARB_MST_QUIET_PER,
586 	mmDCORE0_EDMA0_QM_ARB_CHOICE_Q_PUSH,
587 	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_0,
588 	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_1,
589 	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_2,
590 	mmDCORE0_EDMA0_QM_ARB_WRR_WEIGHT_3,
591 	mmDCORE0_EDMA0_QM_ARB_BASE_LO,
592 	mmDCORE0_EDMA0_QM_ARB_BASE_HI,
593 	mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN,
594 	mmDCORE0_EDMA0_QM_ARB_MST_SLAVE_EN_1,
595 	mmDCORE0_EDMA0_QM_ARB_MST_CRED_INC,
596 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
597 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
598 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
599 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
600 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
601 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
602 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
603 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
604 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
605 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
606 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
607 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
608 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
609 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
610 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
611 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
612 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
613 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
614 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
615 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
616 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
617 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
618 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
619 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
620 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
621 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
622 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
623 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
624 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
625 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
626 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
627 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
628 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
629 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
630 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
631 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
632 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
633 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
634 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
635 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
636 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
637 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
638 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
639 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
640 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
641 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
642 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
643 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
644 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
645 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
646 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
647 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
648 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
649 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
650 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
651 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
652 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
653 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
654 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
655 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
656 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
657 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
658 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
659 	mmDCORE0_EDMA0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
660 	mmDCORE0_EDMA0_QM_ARB_SLV_ID,
661 	mmDCORE0_EDMA0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
662 	mmDCORE0_EDMA0_QM_ARC_CQ_CFG0,
663 	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_0,
664 	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_1,
665 	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_2,
666 	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_3,
667 	mmDCORE0_EDMA0_QM_CQ_IFIFO_CI_4,
668 	mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_CI,
669 	mmDCORE0_EDMA0_QM_CQ_CTL_CI_0,
670 	mmDCORE0_EDMA0_QM_CQ_CTL_CI_1,
671 	mmDCORE0_EDMA0_QM_CQ_CTL_CI_2,
672 	mmDCORE0_EDMA0_QM_CQ_CTL_CI_3,
673 	mmDCORE0_EDMA0_QM_CQ_CTL_CI_4,
674 	mmDCORE0_EDMA0_QM_ARC_CQ_CTL_CI,
675 	mmDCORE0_EDMA0_QM_ARC_CQ_TSIZE,
676 	mmDCORE0_EDMA0_QM_ARC_CQ_CTL,
677 	mmDCORE0_EDMA0_QM_CP_SWITCH_WD_SET,
678 	mmDCORE0_EDMA0_QM_CP_EXT_SWITCH,
679 	mmDCORE0_EDMA0_QM_CP_PRED_0,
680 	mmDCORE0_EDMA0_QM_CP_PRED_1,
681 	mmDCORE0_EDMA0_QM_CP_PRED_2,
682 	mmDCORE0_EDMA0_QM_CP_PRED_3,
683 	mmDCORE0_EDMA0_QM_CP_PRED_4,
684 	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_0,
685 	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_1,
686 	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_2,
687 	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_3,
688 	mmDCORE0_EDMA0_QM_CP_PRED_UPEN_4,
689 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_0,
690 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_1,
691 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_2,
692 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_3,
693 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_LO_4,
694 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_0,
695 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_1,
696 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_2,
697 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_3,
698 	mmDCORE0_EDMA0_QM_CP_MSG_BASE0_ADDR_HI_4,
699 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_0,
700 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_1,
701 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_2,
702 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_3,
703 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_LO_4,
704 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_0,
705 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_1,
706 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_2,
707 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_3,
708 	mmDCORE0_EDMA0_QM_CP_MSG_BASE1_ADDR_HI_4,
709 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_0,
710 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_1,
711 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_2,
712 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_3,
713 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_LO_4,
714 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_0,
715 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_1,
716 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_2,
717 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_3,
718 	mmDCORE0_EDMA0_QM_CP_MSG_BASE2_ADDR_HI_4,
719 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_0,
720 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_1,
721 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_2,
722 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_3,
723 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_LO_4,
724 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_0,
725 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_1,
726 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_2,
727 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_3,
728 	mmDCORE0_EDMA0_QM_CP_MSG_BASE3_ADDR_HI_4,
729 	mmDCORE0_EDMA0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
730 	mmDCORE0_EDMA0_QM_ARC_CQ_CTL_MSG_BASE_LO,
731 	mmDCORE0_EDMA0_QM_CQ_IFIFO_MSG_BASE_LO,
732 	mmDCORE0_EDMA0_QM_CQ_CTL_MSG_BASE_LO
733 };
734 
735 static const u32 gaudi2_pb_dcr0_mme_sbte[] = {
736 	mmDCORE0_MME_SBTE0_BASE,
737 	mmDCORE0_MME_SBTE0_MSTR_IF_RR_SHRD_HBW_BASE,
738 };
739 
740 static const u32 gaudi2_pb_dcr0_mme_qm[] = {
741 	mmDCORE0_MME_QM_BASE,
742 };
743 
744 static const u32 gaudi2_pb_dcr0_mme_eng[] = {
745 	mmDCORE0_MME_ACC_BASE,
746 	mmDCORE0_MME_CTRL_HI_BASE,
747 	mmDCORE0_MME_CTRL_LO_BASE,
748 	mmDCORE0_MME_CTRL_MSTR_IF_RR_SHRD_HBW_BASE,
749 	mmDCORE0_MME_WB0_MSTR_IF_RR_SHRD_HBW_BASE,
750 	mmDCORE0_MME_WB1_MSTR_IF_RR_SHRD_HBW_BASE,
751 };
752 
753 static const u32 gaudi2_pb_dcr0_mme_arc[] = {
754 	mmDCORE0_MME_QM_ARC_AUX_BASE,
755 	mmDCORE0_MME_QM_ARC_DUP_ENG_BASE,
756 };
757 
758 static const struct range gaudi2_pb_dcr0_mme_arc_unsecured_regs[] = {
759 	{mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_MME_QM_ARC_AUX_RUN_HALT_ACK},
760 	{mmDCORE0_MME_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_MME_QM_ARC_AUX_WAKE_UP_EVENT},
761 	{mmDCORE0_MME_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_MME_QM_ARC_AUX_CID_OFFSET_7},
762 	{mmDCORE0_MME_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_MME_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
763 	{mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
764 	{mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_MME_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
765 	{mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
766 		mmDCORE0_MME_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
767 	{mmDCORE0_MME_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
768 		mmDCORE0_MME_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
769 	{mmDCORE0_MME_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
770 		mmDCORE0_MME_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
771 	{mmDCORE0_MME_QM_ARC_DUP_ENG_DUP_TPC_ENG_ADDR_0,
772 		mmDCORE0_MME_QM_ARC_DUP_ENG_ARC_CID_OFFSET_63},
773 	{mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_HB_STRONG_ORDER,
774 		mmDCORE0_MME_QM_ARC_DUP_ENG_AXUSER_LB_OVRD},
775 };
776 
777 static const u32 gaudi2_pb_dcr0_mme_qm_unsecured_regs[] = {
778 	mmDCORE0_MME_QM_CQ_CFG0_0,
779 	mmDCORE0_MME_QM_CQ_CFG0_1,
780 	mmDCORE0_MME_QM_CQ_CFG0_2,
781 	mmDCORE0_MME_QM_CQ_CFG0_3,
782 	mmDCORE0_MME_QM_CQ_CFG0_4,
783 	mmDCORE0_MME_QM_CP_FENCE0_RDATA_0,
784 	mmDCORE0_MME_QM_CP_FENCE0_RDATA_1,
785 	mmDCORE0_MME_QM_CP_FENCE0_RDATA_2,
786 	mmDCORE0_MME_QM_CP_FENCE0_RDATA_3,
787 	mmDCORE0_MME_QM_CP_FENCE0_RDATA_4,
788 	mmDCORE0_MME_QM_CP_FENCE1_RDATA_0,
789 	mmDCORE0_MME_QM_CP_FENCE1_RDATA_1,
790 	mmDCORE0_MME_QM_CP_FENCE1_RDATA_2,
791 	mmDCORE0_MME_QM_CP_FENCE1_RDATA_3,
792 	mmDCORE0_MME_QM_CP_FENCE1_RDATA_4,
793 	mmDCORE0_MME_QM_CP_FENCE2_RDATA_0,
794 	mmDCORE0_MME_QM_CP_FENCE2_RDATA_1,
795 	mmDCORE0_MME_QM_CP_FENCE2_RDATA_2,
796 	mmDCORE0_MME_QM_CP_FENCE2_RDATA_3,
797 	mmDCORE0_MME_QM_CP_FENCE2_RDATA_4,
798 	mmDCORE0_MME_QM_CP_FENCE3_RDATA_0,
799 	mmDCORE0_MME_QM_CP_FENCE3_RDATA_1,
800 	mmDCORE0_MME_QM_CP_FENCE3_RDATA_2,
801 	mmDCORE0_MME_QM_CP_FENCE3_RDATA_3,
802 	mmDCORE0_MME_QM_CP_FENCE3_RDATA_4,
803 	mmDCORE0_MME_QM_CP_FENCE0_CNT_0,
804 	mmDCORE0_MME_QM_CP_FENCE0_CNT_1,
805 	mmDCORE0_MME_QM_CP_FENCE0_CNT_2,
806 	mmDCORE0_MME_QM_CP_FENCE0_CNT_3,
807 	mmDCORE0_MME_QM_CP_FENCE0_CNT_4,
808 	mmDCORE0_MME_QM_CP_FENCE1_CNT_0,
809 	mmDCORE0_MME_QM_CP_FENCE1_CNT_1,
810 	mmDCORE0_MME_QM_CP_FENCE1_CNT_2,
811 	mmDCORE0_MME_QM_CP_FENCE1_CNT_3,
812 	mmDCORE0_MME_QM_CP_FENCE1_CNT_4,
813 	mmDCORE0_MME_QM_CP_FENCE2_CNT_0,
814 	mmDCORE0_MME_QM_CP_FENCE2_CNT_1,
815 	mmDCORE0_MME_QM_CP_FENCE2_CNT_2,
816 	mmDCORE0_MME_QM_CP_FENCE2_CNT_3,
817 	mmDCORE0_MME_QM_CP_FENCE2_CNT_4,
818 	mmDCORE0_MME_QM_CP_FENCE3_CNT_0,
819 	mmDCORE0_MME_QM_CP_FENCE3_CNT_1,
820 	mmDCORE0_MME_QM_CP_FENCE3_CNT_2,
821 	mmDCORE0_MME_QM_CP_FENCE3_CNT_3,
822 	mmDCORE0_MME_QM_CP_FENCE3_CNT_4,
823 	mmDCORE0_MME_QM_CQ_PTR_LO_0,
824 	mmDCORE0_MME_QM_CQ_PTR_HI_0,
825 	mmDCORE0_MME_QM_CQ_TSIZE_0,
826 	mmDCORE0_MME_QM_CQ_CTL_0,
827 	mmDCORE0_MME_QM_CQ_PTR_LO_1,
828 	mmDCORE0_MME_QM_CQ_PTR_HI_1,
829 	mmDCORE0_MME_QM_CQ_TSIZE_1,
830 	mmDCORE0_MME_QM_CQ_CTL_1,
831 	mmDCORE0_MME_QM_CQ_PTR_LO_2,
832 	mmDCORE0_MME_QM_CQ_PTR_HI_2,
833 	mmDCORE0_MME_QM_CQ_TSIZE_2,
834 	mmDCORE0_MME_QM_CQ_CTL_2,
835 	mmDCORE0_MME_QM_CQ_PTR_LO_3,
836 	mmDCORE0_MME_QM_CQ_PTR_HI_3,
837 	mmDCORE0_MME_QM_CQ_TSIZE_3,
838 	mmDCORE0_MME_QM_CQ_CTL_3,
839 	mmDCORE0_MME_QM_CQ_PTR_LO_4,
840 	mmDCORE0_MME_QM_CQ_PTR_HI_4,
841 	mmDCORE0_MME_QM_CQ_TSIZE_4,
842 	mmDCORE0_MME_QM_CQ_CTL_4,
843 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE,
844 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
845 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE,
846 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
847 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE,
848 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
849 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE,
850 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
851 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE,
852 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
853 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE,
854 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
855 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE,
856 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
857 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE,
858 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
859 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE,
860 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
861 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE,
862 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
863 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE,
864 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
865 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE,
866 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
867 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE,
868 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
869 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE,
870 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
871 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE,
872 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
873 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE,
874 	mmDCORE0_MME_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
875 	mmDCORE0_MME_QM_ARC_CQ_PTR_LO,
876 	mmDCORE0_MME_QM_ARC_CQ_PTR_LO_STS,
877 	mmDCORE0_MME_QM_ARC_CQ_PTR_HI,
878 	mmDCORE0_MME_QM_ARC_CQ_PTR_HI_STS,
879 	mmDCORE0_MME_QM_ARB_CFG_0,
880 	mmDCORE0_MME_QM_ARB_MST_QUIET_PER,
881 	mmDCORE0_MME_QM_ARB_CHOICE_Q_PUSH,
882 	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_0,
883 	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_1,
884 	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_2,
885 	mmDCORE0_MME_QM_ARB_WRR_WEIGHT_3,
886 	mmDCORE0_MME_QM_ARB_BASE_LO,
887 	mmDCORE0_MME_QM_ARB_BASE_HI,
888 	mmDCORE0_MME_QM_ARB_MST_SLAVE_EN,
889 	mmDCORE0_MME_QM_ARB_MST_SLAVE_EN_1,
890 	mmDCORE0_MME_QM_ARB_MST_CRED_INC,
891 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_0,
892 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_1,
893 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_2,
894 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_3,
895 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_4,
896 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_5,
897 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_6,
898 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_7,
899 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_8,
900 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_9,
901 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_10,
902 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_11,
903 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_12,
904 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_13,
905 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_14,
906 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_15,
907 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_16,
908 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_17,
909 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_18,
910 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_19,
911 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_20,
912 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_21,
913 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_22,
914 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_23,
915 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_24,
916 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_25,
917 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_26,
918 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_27,
919 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_28,
920 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_29,
921 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_30,
922 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_31,
923 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_32,
924 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_33,
925 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_34,
926 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_35,
927 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_36,
928 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_37,
929 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_38,
930 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_39,
931 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_40,
932 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_41,
933 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_42,
934 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_43,
935 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_44,
936 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_45,
937 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_46,
938 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_47,
939 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_48,
940 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_49,
941 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_50,
942 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_51,
943 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_52,
944 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_53,
945 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_54,
946 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_55,
947 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_56,
948 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_57,
949 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_58,
950 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_59,
951 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_60,
952 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_61,
953 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_62,
954 	mmDCORE0_MME_QM_ARB_MST_CHOICE_PUSH_OFST_63,
955 	mmDCORE0_MME_QM_ARB_SLV_ID,
956 	mmDCORE0_MME_QM_ARB_SLV_MASTER_INC_CRED_OFST,
957 	mmDCORE0_MME_QM_ARC_CQ_CFG0,
958 	mmDCORE0_MME_QM_CQ_IFIFO_CI_0,
959 	mmDCORE0_MME_QM_CQ_IFIFO_CI_1,
960 	mmDCORE0_MME_QM_CQ_IFIFO_CI_2,
961 	mmDCORE0_MME_QM_CQ_IFIFO_CI_3,
962 	mmDCORE0_MME_QM_CQ_IFIFO_CI_4,
963 	mmDCORE0_MME_QM_ARC_CQ_IFIFO_CI,
964 	mmDCORE0_MME_QM_CQ_CTL_CI_0,
965 	mmDCORE0_MME_QM_CQ_CTL_CI_1,
966 	mmDCORE0_MME_QM_CQ_CTL_CI_2,
967 	mmDCORE0_MME_QM_CQ_CTL_CI_3,
968 	mmDCORE0_MME_QM_CQ_CTL_CI_4,
969 	mmDCORE0_MME_QM_ARC_CQ_CTL_CI,
970 	mmDCORE0_MME_QM_ARC_CQ_TSIZE,
971 	mmDCORE0_MME_QM_ARC_CQ_CTL,
972 	mmDCORE0_MME_QM_CP_SWITCH_WD_SET,
973 	mmDCORE0_MME_QM_CP_EXT_SWITCH,
974 	mmDCORE0_MME_QM_CP_PRED_0,
975 	mmDCORE0_MME_QM_CP_PRED_1,
976 	mmDCORE0_MME_QM_CP_PRED_2,
977 	mmDCORE0_MME_QM_CP_PRED_3,
978 	mmDCORE0_MME_QM_CP_PRED_4,
979 	mmDCORE0_MME_QM_CP_PRED_UPEN_0,
980 	mmDCORE0_MME_QM_CP_PRED_UPEN_1,
981 	mmDCORE0_MME_QM_CP_PRED_UPEN_2,
982 	mmDCORE0_MME_QM_CP_PRED_UPEN_3,
983 	mmDCORE0_MME_QM_CP_PRED_UPEN_4,
984 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_0,
985 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_1,
986 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_2,
987 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_3,
988 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_LO_4,
989 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_0,
990 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_1,
991 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_2,
992 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_3,
993 	mmDCORE0_MME_QM_CP_MSG_BASE0_ADDR_HI_4,
994 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_0,
995 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_1,
996 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_2,
997 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_3,
998 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_LO_4,
999 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_0,
1000 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_1,
1001 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_2,
1002 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_3,
1003 	mmDCORE0_MME_QM_CP_MSG_BASE1_ADDR_HI_4,
1004 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_0,
1005 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_1,
1006 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_2,
1007 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_3,
1008 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_LO_4,
1009 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_0,
1010 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_1,
1011 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_2,
1012 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_3,
1013 	mmDCORE0_MME_QM_CP_MSG_BASE2_ADDR_HI_4,
1014 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_0,
1015 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_1,
1016 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_2,
1017 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_3,
1018 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_LO_4,
1019 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_0,
1020 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_1,
1021 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_2,
1022 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_3,
1023 	mmDCORE0_MME_QM_CP_MSG_BASE3_ADDR_HI_4,
1024 	mmDCORE0_MME_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1025 	mmDCORE0_MME_QM_ARC_CQ_CTL_MSG_BASE_LO,
1026 	mmDCORE0_MME_QM_CQ_IFIFO_MSG_BASE_LO,
1027 	mmDCORE0_MME_QM_CQ_CTL_MSG_BASE_LO
1028 };
1029 
1030 static const u32 gaudi2_pb_dcr0_mme_eng_unsecured_regs[] = {
1031 	mmDCORE0_MME_CTRL_LO_CMD,
1032 	mmDCORE0_MME_CTRL_LO_AGU,
1033 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_0,
1034 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_1,
1035 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_2,
1036 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_3,
1037 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_ROI_BASE_OFFSET_4,
1038 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_0,
1039 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_1,
1040 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_2,
1041 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_3,
1042 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_ROI_BASE_OFFSET_4,
1043 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_LOW,
1044 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BRAINS_HIGH,
1045 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_LOW,
1046 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_HEADER_HIGH,
1047 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_MASTER,
1048 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_EUS_SLAVE,
1049 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_KERNEL_SIZE_MINUS_1,
1050 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_LOW,
1051 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_CONV_HIGH,
1052 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_OUTER_LOOP,
1053 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_NUM_ITERATIONS_MINUS_1,
1054 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SB_REPEAT,
1055 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_FP8_BIAS,
1056 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_RATE_LIMITER,
1057 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_USER_DATA,
1058 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_IN,
1059 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PERF_EVT_OUT,
1060 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_PCU,
1061 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ0_ADDR,
1062 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SLAVE_SYNC_OBJ1_ADDR,
1063 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_POWER_LOOP,
1064 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_MASTER,
1065 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_MASTER,
1066 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_MASTER,
1067 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_MASTER,
1068 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE0_SLAVE,
1069 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE1_SLAVE,
1070 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE2_SLAVE,
1071 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_SPARE3_SLAVE,
1072 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_WKL_ID,
1073 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_0,
1074 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_1,
1075 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_2,
1076 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_3,
1077 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_ROI_BASE_OFFSET_4,
1078 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_0,
1079 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_1,
1080 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_2,
1081 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_3,
1082 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_ROI_BASE_OFFSET_4,
1083 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_0,
1084 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_1,
1085 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_2,
1086 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_3,
1087 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_ROI_BASE_OFFSET_4,
1088 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_0,
1089 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_1,
1090 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_2,
1091 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_3,
1092 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_ROI_BASE_OFFSET_4,
1093 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_0,
1094 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_1,
1095 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_2,
1096 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_3,
1097 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_ROI_BASE_OFFSET_4,
1098 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_0,
1099 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_1,
1100 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_2,
1101 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_3,
1102 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_ROI_BASE_OFFSET_4,
1103 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_0,
1104 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_1,
1105 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_2,
1106 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_3,
1107 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_VALID_ELEMENTS_4,
1108 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_0,
1109 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_1,
1110 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_2,
1111 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_3,
1112 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_LOOP_STRIDE_4,
1113 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_0,
1114 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_1,
1115 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_2,
1116 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_ROI_SIZE_3,
1117 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_0,
1118 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_1,
1119 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_2,
1120 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_SPATIAL_STRIDES_3,
1121 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_0,
1122 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_1,
1123 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_2,
1124 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_START_OFFSET_3,
1125 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_0,
1126 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_1,
1127 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_2,
1128 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_3,
1129 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_ROI_BASE_OFFSET_4,
1130 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_LOW,
1131 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT1_HIGH,
1132 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_LOW,
1133 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_COUT0_HIGH,
1134 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_LOW,
1135 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_A_HIGH,
1136 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_LOW,
1137 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_B_HIGH,
1138 	mmDCORE0_MME_CTRL_LO_ARCH_STATUS,
1139 	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_DW0,
1140 	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR0,
1141 	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL0,
1142 	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_ADDR1,
1143 	mmDCORE0_MME_CTRL_LO_ARCH_SYNC_OBJ_VAL1,
1144 	mmDCORE0_MME_CTRL_LO_ARCH_A_SS,
1145 	mmDCORE0_MME_CTRL_LO_ARCH_B_SS,
1146 	mmDCORE0_MME_CTRL_LO_ARCH_COUT_SS,
1147 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_0,
1148 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_1,
1149 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_2,
1150 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_3,
1151 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_ROI_BASE_OFFSET_4,
1152 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_0,
1153 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_1,
1154 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_2,
1155 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_3,
1156 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_ROI_BASE_OFFSET_4,
1157 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_0,
1158 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_1,
1159 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_2,
1160 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_3,
1161 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_VALID_ELEMENTS_4,
1162 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_0,
1163 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_1,
1164 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_2,
1165 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_3,
1166 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_LOOP_STRIDE_4,
1167 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_0,
1168 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_1,
1169 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_2,
1170 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_ROI_SIZE_3,
1171 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_0,
1172 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_1,
1173 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_2,
1174 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_SPATIAL_STRIDES_3,
1175 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_0,
1176 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_1,
1177 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_2,
1178 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_START_OFFSET_3,
1179 	mmDCORE0_MME_CTRL_LO_ARCH_BASE_ADDR_BASE,
1180 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_START_BASE,
1181 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_A_BASE,
1182 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_BASE,
1183 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_COUT_BASE,
1184 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_MASTER_BASE,
1185 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_BASE,
1186 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_MASTER_BASE,
1187 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN1_SLAVE_BASE,
1188 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_MASTER_BASE,
1189 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN2_SLAVE_BASE,
1190 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_MASTER_BASE,
1191 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN3_SLAVE_BASE,
1192 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_MASTER_BASE,
1193 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_BASE,
1194 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_MASTER_BASE,
1195 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_BASE,
1196 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_MASTER_BASE,
1197 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT1_SLAVE_BASE,
1198 	mmDCORE0_MME_CTRL_LO_ARCH_NON_TENSOR_END_BASE,
1199 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_0,
1200 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_1,
1201 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_2,
1202 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_3,
1203 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_COUT0_SLAVE_ROI_BASE_OFFSET_4,
1204 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_0,
1205 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_1,
1206 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_2,
1207 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_3,
1208 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN4_SLAVE_ROI_BASE_OFFSET_4,
1209 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_0,
1210 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_1,
1211 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_2,
1212 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_3,
1213 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_VALID_ELEMENTS_4,
1214 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_0,
1215 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_1,
1216 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_2,
1217 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_3,
1218 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_LOOP_STRIDE_4,
1219 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_0,
1220 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_1,
1221 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_2,
1222 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_ROI_SIZE_3,
1223 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_0,
1224 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_1,
1225 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_2,
1226 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_SPATIAL_STRIDES_3,
1227 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_0,
1228 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_1,
1229 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_2,
1230 	mmDCORE0_MME_CTRL_LO_ARCH_TENSOR_B_START_OFFSET_3,
1231 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_0,
1232 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_1,
1233 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_2,
1234 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_3,
1235 	mmDCORE0_MME_CTRL_LO_ARCH_AGU_IN0_SLAVE_ROI_BASE_OFFSET_4,
1236 	mmDCORE0_MME_ACC_AP_LFSR_POLY,
1237 	mmDCORE0_MME_ACC_AP_LFSR_SEED_WDATA,
1238 	mmDCORE0_MME_ACC_AP_LFSR_SEED_SEL,
1239 	mmDCORE0_MME_ACC_AP_LFSR_SEED_RDATA,
1240 	mmDCORE0_MME_ACC_AP_LFSR_CLOSE_CGATE_DLY,
1241 	mmDCORE0_MME_ACC_WBC_SRC_BP,
1242 };
1243 
1244 static const u32 gaudi2_pb_dcr0_tpc0[] = {
1245 	mmDCORE0_TPC0_QM_BASE,
1246 	mmDCORE0_TPC0_CFG_BASE,
1247 	mmDCORE0_TPC0_MSTR_IF_RR_SHRD_HBW_BASE,
1248 };
1249 
1250 static const u32 gaudi2_pb_dcr0_tpc0_arc[] = {
1251 	mmDCORE0_TPC0_QM_ARC_AUX_BASE,
1252 };
1253 
1254 static const struct range gaudi2_pb_dcr0_tpc0_arc_unsecured_regs[] = {
1255 	{mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_REQ, mmDCORE0_TPC0_QM_ARC_AUX_RUN_HALT_ACK},
1256 	{mmDCORE0_TPC0_QM_ARC_AUX_CLUSTER_NUM, mmDCORE0_TPC0_QM_ARC_AUX_WAKE_UP_EVENT},
1257 	{mmDCORE0_TPC0_QM_ARC_AUX_ARC_RST_REQ, mmDCORE0_TPC0_QM_ARC_AUX_CID_OFFSET_7},
1258 	{mmDCORE0_TPC0_QM_ARC_AUX_SCRATCHPAD_0, mmDCORE0_TPC0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
1259 	{mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
1260 	{mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmDCORE0_TPC0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
1261 	{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0,
1262 		mmDCORE0_TPC0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
1263 	{mmDCORE0_TPC0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT,
1264 		mmDCORE0_TPC0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
1265 	{mmDCORE0_TPC0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT,
1266 		mmDCORE0_TPC0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
1267 };
1268 
1269 static const u32 gaudi2_pb_dcr0_tpc0_unsecured_regs[] = {
1270 	mmDCORE0_TPC0_QM_CQ_CFG0_0,
1271 	mmDCORE0_TPC0_QM_CQ_CFG0_1,
1272 	mmDCORE0_TPC0_QM_CQ_CFG0_2,
1273 	mmDCORE0_TPC0_QM_CQ_CFG0_3,
1274 	mmDCORE0_TPC0_QM_CQ_CFG0_4,
1275 	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_0,
1276 	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_1,
1277 	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_2,
1278 	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_3,
1279 	mmDCORE0_TPC0_QM_CP_FENCE0_RDATA_4,
1280 	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_0,
1281 	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_1,
1282 	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_2,
1283 	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_3,
1284 	mmDCORE0_TPC0_QM_CP_FENCE1_RDATA_4,
1285 	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_0,
1286 	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_1,
1287 	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_2,
1288 	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_3,
1289 	mmDCORE0_TPC0_QM_CP_FENCE2_RDATA_4,
1290 	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_0,
1291 	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_1,
1292 	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_2,
1293 	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_3,
1294 	mmDCORE0_TPC0_QM_CP_FENCE3_RDATA_4,
1295 	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_0,
1296 	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_1,
1297 	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_2,
1298 	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_3,
1299 	mmDCORE0_TPC0_QM_CP_FENCE0_CNT_4,
1300 	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_0,
1301 	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_1,
1302 	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_2,
1303 	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_3,
1304 	mmDCORE0_TPC0_QM_CP_FENCE1_CNT_4,
1305 	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_0,
1306 	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_1,
1307 	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_2,
1308 	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_3,
1309 	mmDCORE0_TPC0_QM_CP_FENCE2_CNT_4,
1310 	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_0,
1311 	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_1,
1312 	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_2,
1313 	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_3,
1314 	mmDCORE0_TPC0_QM_CP_FENCE3_CNT_4,
1315 	mmDCORE0_TPC0_QM_CQ_PTR_LO_0,
1316 	mmDCORE0_TPC0_QM_CQ_PTR_HI_0,
1317 	mmDCORE0_TPC0_QM_CQ_TSIZE_0,
1318 	mmDCORE0_TPC0_QM_CQ_CTL_0,
1319 	mmDCORE0_TPC0_QM_CQ_PTR_LO_1,
1320 	mmDCORE0_TPC0_QM_CQ_PTR_HI_1,
1321 	mmDCORE0_TPC0_QM_CQ_TSIZE_1,
1322 	mmDCORE0_TPC0_QM_CQ_CTL_1,
1323 	mmDCORE0_TPC0_QM_CQ_PTR_LO_2,
1324 	mmDCORE0_TPC0_QM_CQ_PTR_HI_2,
1325 	mmDCORE0_TPC0_QM_CQ_TSIZE_2,
1326 	mmDCORE0_TPC0_QM_CQ_CTL_2,
1327 	mmDCORE0_TPC0_QM_CQ_PTR_LO_3,
1328 	mmDCORE0_TPC0_QM_CQ_PTR_HI_3,
1329 	mmDCORE0_TPC0_QM_CQ_TSIZE_3,
1330 	mmDCORE0_TPC0_QM_CQ_CTL_3,
1331 	mmDCORE0_TPC0_QM_CQ_PTR_LO_4,
1332 	mmDCORE0_TPC0_QM_CQ_PTR_HI_4,
1333 	mmDCORE0_TPC0_QM_CQ_TSIZE_4,
1334 	mmDCORE0_TPC0_QM_CQ_CTL_4,
1335 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE,
1336 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
1337 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE,
1338 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
1339 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE,
1340 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
1341 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE,
1342 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
1343 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE,
1344 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
1345 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE,
1346 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
1347 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE,
1348 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
1349 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE,
1350 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
1351 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE,
1352 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
1353 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE,
1354 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
1355 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE,
1356 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
1357 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE,
1358 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
1359 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE,
1360 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
1361 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE,
1362 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
1363 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE,
1364 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
1365 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE,
1366 	mmDCORE0_TPC0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
1367 	mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO,
1368 	mmDCORE0_TPC0_QM_ARC_CQ_PTR_LO_STS,
1369 	mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI,
1370 	mmDCORE0_TPC0_QM_ARC_CQ_PTR_HI_STS,
1371 	mmDCORE0_TPC0_QM_ARB_CFG_0,
1372 	mmDCORE0_TPC0_QM_ARB_MST_QUIET_PER,
1373 	mmDCORE0_TPC0_QM_ARB_CHOICE_Q_PUSH,
1374 	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_0,
1375 	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_1,
1376 	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_2,
1377 	mmDCORE0_TPC0_QM_ARB_WRR_WEIGHT_3,
1378 	mmDCORE0_TPC0_QM_ARB_BASE_LO,
1379 	mmDCORE0_TPC0_QM_ARB_BASE_HI,
1380 	mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN,
1381 	mmDCORE0_TPC0_QM_ARB_MST_SLAVE_EN_1,
1382 	mmDCORE0_TPC0_QM_ARB_MST_CRED_INC,
1383 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
1384 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
1385 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
1386 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
1387 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
1388 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
1389 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
1390 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
1391 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
1392 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
1393 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
1394 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
1395 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
1396 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
1397 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
1398 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
1399 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
1400 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
1401 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
1402 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
1403 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
1404 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
1405 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
1406 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
1407 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
1408 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
1409 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
1410 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
1411 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
1412 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
1413 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
1414 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
1415 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
1416 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
1417 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
1418 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
1419 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
1420 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
1421 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
1422 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
1423 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
1424 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
1425 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
1426 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
1427 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
1428 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
1429 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
1430 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
1431 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
1432 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
1433 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
1434 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
1435 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
1436 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
1437 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
1438 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
1439 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
1440 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
1441 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
1442 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
1443 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
1444 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
1445 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
1446 	mmDCORE0_TPC0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
1447 	mmDCORE0_TPC0_QM_ARB_SLV_ID,
1448 	mmDCORE0_TPC0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
1449 	mmDCORE0_TPC0_QM_ARC_CQ_CFG0,
1450 	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_0,
1451 	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_1,
1452 	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_2,
1453 	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_3,
1454 	mmDCORE0_TPC0_QM_CQ_IFIFO_CI_4,
1455 	mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_CI,
1456 	mmDCORE0_TPC0_QM_CQ_CTL_CI_0,
1457 	mmDCORE0_TPC0_QM_CQ_CTL_CI_1,
1458 	mmDCORE0_TPC0_QM_CQ_CTL_CI_2,
1459 	mmDCORE0_TPC0_QM_CQ_CTL_CI_3,
1460 	mmDCORE0_TPC0_QM_CQ_CTL_CI_4,
1461 	mmDCORE0_TPC0_QM_ARC_CQ_CTL_CI,
1462 	mmDCORE0_TPC0_QM_ARC_CQ_TSIZE,
1463 	mmDCORE0_TPC0_QM_ARC_CQ_CTL,
1464 	mmDCORE0_TPC0_QM_CP_SWITCH_WD_SET,
1465 	mmDCORE0_TPC0_QM_CP_EXT_SWITCH,
1466 	mmDCORE0_TPC0_QM_CP_PRED_0,
1467 	mmDCORE0_TPC0_QM_CP_PRED_1,
1468 	mmDCORE0_TPC0_QM_CP_PRED_2,
1469 	mmDCORE0_TPC0_QM_CP_PRED_3,
1470 	mmDCORE0_TPC0_QM_CP_PRED_4,
1471 	mmDCORE0_TPC0_QM_CP_PRED_UPEN_0,
1472 	mmDCORE0_TPC0_QM_CP_PRED_UPEN_1,
1473 	mmDCORE0_TPC0_QM_CP_PRED_UPEN_2,
1474 	mmDCORE0_TPC0_QM_CP_PRED_UPEN_3,
1475 	mmDCORE0_TPC0_QM_CP_PRED_UPEN_4,
1476 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_0,
1477 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_1,
1478 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_2,
1479 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_3,
1480 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_LO_4,
1481 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_0,
1482 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_1,
1483 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_2,
1484 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_3,
1485 	mmDCORE0_TPC0_QM_CP_MSG_BASE0_ADDR_HI_4,
1486 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_0,
1487 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_1,
1488 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_2,
1489 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_3,
1490 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_LO_4,
1491 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_0,
1492 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_1,
1493 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_2,
1494 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_3,
1495 	mmDCORE0_TPC0_QM_CP_MSG_BASE1_ADDR_HI_4,
1496 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_0,
1497 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_1,
1498 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_2,
1499 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_3,
1500 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_LO_4,
1501 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_0,
1502 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_1,
1503 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_2,
1504 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_3,
1505 	mmDCORE0_TPC0_QM_CP_MSG_BASE2_ADDR_HI_4,
1506 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_0,
1507 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_1,
1508 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_2,
1509 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_3,
1510 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_LO_4,
1511 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_0,
1512 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_1,
1513 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_2,
1514 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_3,
1515 	mmDCORE0_TPC0_QM_CP_MSG_BASE3_ADDR_HI_4,
1516 	mmDCORE0_TPC0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
1517 	mmDCORE0_TPC0_QM_ARC_CQ_CTL_MSG_BASE_LO,
1518 	mmDCORE0_TPC0_QM_CQ_IFIFO_MSG_BASE_LO,
1519 	mmDCORE0_TPC0_QM_CQ_CTL_MSG_BASE_LO,
1520 	mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_MESSAGE,
1521 	mmDCORE0_TPC0_CFG_QM_SYNC_OBJECT_ADDR,
1522 	mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_LOW,
1523 	mmDCORE0_TPC0_CFG_QM_KERNEL_BASE_ADDRESS_HIGH,
1524 	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_0,
1525 	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_0,
1526 	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_1,
1527 	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_1,
1528 	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_2,
1529 	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_2,
1530 	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_3,
1531 	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_3,
1532 	mmDCORE0_TPC0_CFG_QM_TID_BASE_DIM_4,
1533 	mmDCORE0_TPC0_CFG_QM_TID_SIZE_DIM_4,
1534 	mmDCORE0_TPC0_CFG_QM_KERNEL_CONFIG,
1535 	mmDCORE0_TPC0_CFG_QM_KERNEL_ID,
1536 	mmDCORE0_TPC0_CFG_QM_POWER_LOOP,
1537 	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_LO,
1538 	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE2_ADDR_HI,
1539 	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_LO,
1540 	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE2_ADDR_HI,
1541 	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_LO,
1542 	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE2_ADDR_HI,
1543 	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_LO,
1544 	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE2_ADDR_HI,
1545 	mmDCORE0_TPC0_CFG_FP8_143_BIAS,
1546 	mmDCORE0_TPC0_CFG_ROUND_CSR,
1547 	mmDCORE0_TPC0_CFG_CONV_ROUND_CSR,
1548 	mmDCORE0_TPC0_CFG_SEMAPHORE,
1549 	mmDCORE0_TPC0_CFG_LFSR_POLYNOM,
1550 	mmDCORE0_TPC0_CFG_STATUS,
1551 	mmDCORE0_TPC0_CFG_TPC_CMD,
1552 	mmDCORE0_TPC0_CFG_TPC_EXECUTE,
1553 	mmDCORE0_TPC0_CFG_TPC_DCACHE_L0CD,
1554 	mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_LOW,
1555 	mmDCORE0_TPC0_CFG_ICACHE_BASE_ADDERESS_HIGH,
1556 	mmDCORE0_TPC0_CFG_RD_RATE_LIMIT,
1557 	mmDCORE0_TPC0_CFG_WR_RATE_LIMIT,
1558 	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_LO,
1559 	mmDCORE0_TPC0_CFG_LUT_FUNC32_BASE_ADDR_HI,
1560 	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_LO,
1561 	mmDCORE0_TPC0_CFG_LUT_FUNC64_BASE_ADDR_HI,
1562 	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_LO,
1563 	mmDCORE0_TPC0_CFG_LUT_FUNC128_BASE_ADDR_HI,
1564 	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_LO,
1565 	mmDCORE0_TPC0_CFG_LUT_FUNC256_BASE_ADDR_HI,
1566 	mmDCORE0_TPC0_CFG_KERNEL_KERNEL_CONFIG,
1567 	mmDCORE0_TPC0_CFG_KERNEL_SRF_0,
1568 	mmDCORE0_TPC0_CFG_KERNEL_SRF_1,
1569 	mmDCORE0_TPC0_CFG_KERNEL_SRF_2,
1570 	mmDCORE0_TPC0_CFG_KERNEL_SRF_3,
1571 	mmDCORE0_TPC0_CFG_KERNEL_SRF_4,
1572 	mmDCORE0_TPC0_CFG_KERNEL_SRF_5,
1573 	mmDCORE0_TPC0_CFG_KERNEL_SRF_6,
1574 	mmDCORE0_TPC0_CFG_KERNEL_SRF_7,
1575 	mmDCORE0_TPC0_CFG_KERNEL_SRF_8,
1576 	mmDCORE0_TPC0_CFG_KERNEL_SRF_9,
1577 	mmDCORE0_TPC0_CFG_KERNEL_SRF_10,
1578 	mmDCORE0_TPC0_CFG_KERNEL_SRF_11,
1579 	mmDCORE0_TPC0_CFG_KERNEL_SRF_12,
1580 	mmDCORE0_TPC0_CFG_KERNEL_SRF_13,
1581 	mmDCORE0_TPC0_CFG_KERNEL_SRF_14,
1582 	mmDCORE0_TPC0_CFG_KERNEL_SRF_15,
1583 	mmDCORE0_TPC0_CFG_KERNEL_SRF_16,
1584 	mmDCORE0_TPC0_CFG_KERNEL_SRF_17,
1585 	mmDCORE0_TPC0_CFG_KERNEL_SRF_18,
1586 	mmDCORE0_TPC0_CFG_KERNEL_SRF_19,
1587 	mmDCORE0_TPC0_CFG_KERNEL_SRF_20,
1588 	mmDCORE0_TPC0_CFG_KERNEL_SRF_21,
1589 	mmDCORE0_TPC0_CFG_KERNEL_SRF_22,
1590 	mmDCORE0_TPC0_CFG_KERNEL_SRF_23,
1591 	mmDCORE0_TPC0_CFG_KERNEL_SRF_24,
1592 	mmDCORE0_TPC0_CFG_KERNEL_SRF_25,
1593 	mmDCORE0_TPC0_CFG_KERNEL_SRF_26,
1594 	mmDCORE0_TPC0_CFG_KERNEL_SRF_27,
1595 	mmDCORE0_TPC0_CFG_KERNEL_SRF_28,
1596 	mmDCORE0_TPC0_CFG_KERNEL_SRF_29,
1597 	mmDCORE0_TPC0_CFG_KERNEL_SRF_30,
1598 	mmDCORE0_TPC0_CFG_KERNEL_SRF_31,
1599 	mmDCORE0_TPC0_CFG_TPC_SB_L0CD,
1600 	mmDCORE0_TPC0_CFG_TPC_ID,
1601 	mmDCORE0_TPC0_CFG_QM_KERNEL_ID_INC,
1602 	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_0,
1603 	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_1,
1604 	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_2,
1605 	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_3,
1606 	mmDCORE0_TPC0_CFG_QM_TID_BASE_SIZE_HIGH_DIM_4,
1607 	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_0,
1608 	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_1,
1609 	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_2,
1610 	mmDCORE0_TPC0_CFG_SPECIAL_GLBL_SPARE_3
1611 };
1612 
1613 static const u32 gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs[] = {
1614 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_LOW,
1615 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE_ADDR_HIGH,
1616 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PADDING_VALUE,
1617 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_TENSOR_CONFIG,
1618 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE,
1619 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_STRIDE,
1620 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE,
1621 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_STRIDE,
1622 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE,
1623 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_STRIDE,
1624 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE,
1625 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_STRIDE,
1626 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE,
1627 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_STRIDE,
1628 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_PREF_STRIDE,
1629 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1630 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1631 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1632 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1633 	mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1634 };
1635 
1636 static const u32 gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs[] = {
1637 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_LOW,
1638 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE_ADDR_HIGH,
1639 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_PADDING_VALUE,
1640 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_TENSOR_CONFIG,
1641 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE,
1642 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_STRIDE,
1643 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE,
1644 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_STRIDE,
1645 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE,
1646 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_STRIDE,
1647 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE,
1648 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_STRIDE,
1649 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE,
1650 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_STRIDE,
1651 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_PREF_STRIDE,
1652 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_0_SIZE_STRIDE_HIGH,
1653 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_1_SIZE_STRIDE_HIGH,
1654 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_2_SIZE_STRIDE_HIGH,
1655 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_3_SIZE_STRIDE_HIGH,
1656 	mmDCORE0_TPC0_CFG_QM_TENSOR_0_DIM_4_SIZE_STRIDE_HIGH,
1657 };
1658 
1659 static const u32 gaudi2_pb_dcr0_sram0[] = {
1660 	mmDCORE0_SRAM0_BANK_BASE,
1661 	mmDCORE0_SRAM0_DBG_CNT_N_HBW_DBG_CNT_BASE,
1662 	mmDCORE0_SRAM0_RTR_BASE,
1663 };
1664 
1665 static const u32 gaudi2_pb_dcr0_sm_mstr_if[] = {
1666 	mmDCORE0_SYNC_MNGR_MSTR_IF_RR_SHRD_HBW_BASE,
1667 };
1668 
1669 static const u32 gaudi2_pb_dcr0_sm_glbl[] = {
1670 	mmDCORE0_SYNC_MNGR_GLBL_BASE,
1671 };
1672 
1673 static const u32 gaudi2_pb_dcr1_sm_glbl[] = {
1674 	mmDCORE1_SYNC_MNGR_GLBL_BASE,
1675 };
1676 
1677 static const struct range gaudi2_pb_dcr0_sm_glbl_unsecured_regs[] = {
1678 	{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1679 	{mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1680 	{mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1681 	{mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_PI_63},
1682 	{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1683 	{mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1684 	{mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_1, mmDCORE0_SYNC_MNGR_GLBL_LBW_DATA_63},
1685 	{mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_1, mmDCORE0_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1686 };
1687 
1688 static const struct range gaudi2_pb_dcr_x_sm_glbl_unsecured_regs[] = {
1689 	{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_L_63},
1690 	{mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_BASE_ADDR_H_63},
1691 	{mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_SIZE_LOG2_63},
1692 	{mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_PI_63},
1693 	{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_L_63},
1694 	{mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_ADDR_H_63},
1695 	{mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_0, mmDCORE1_SYNC_MNGR_GLBL_LBW_DATA_63},
1696 	{mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_0, mmDCORE1_SYNC_MNGR_GLBL_CQ_INC_MODE_63},
1697 };
1698 
1699 static const u32 gaudi2_pb_arc_sched[] = {
1700 	mmARC_FARM_ARC0_AUX_BASE,
1701 	mmARC_FARM_ARC0_DUP_ENG_BASE,
1702 	mmARC_FARM_ARC0_ACP_ENG_BASE,
1703 };
1704 
1705 static const struct range gaudi2_pb_arc_sched_unsecured_regs[] = {
1706 	{mmARC_FARM_ARC0_AUX_RUN_HALT_REQ, mmARC_FARM_ARC0_AUX_RUN_HALT_ACK},
1707 	{mmARC_FARM_ARC0_AUX_CLUSTER_NUM, mmARC_FARM_ARC0_AUX_WAKE_UP_EVENT},
1708 	{mmARC_FARM_ARC0_AUX_ARC_RST_REQ, mmARC_FARM_ARC0_AUX_CID_OFFSET_7},
1709 	{mmARC_FARM_ARC0_AUX_SCRATCHPAD_0, mmARC_FARM_ARC0_AUX_INFLIGHT_LBU_RD_CNT},
1710 	{mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_CBU_EARLY_BRESP_EN},
1711 	{mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN, mmARC_FARM_ARC0_AUX_LBU_EARLY_BRESP_EN},
1712 	{mmARC_FARM_ARC0_AUX_DCCM_QUEUE_BASE_ADDR_0, mmARC_FARM_ARC0_AUX_DCCM_QUEUE_ALERT_MSG},
1713 	{mmARC_FARM_ARC0_AUX_DCCM_Q_PUSH_FIFO_CNT, mmARC_FARM_ARC0_AUX_QMAN_ARC_CQ_SHADOW_CI},
1714 	{mmARC_FARM_ARC0_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmARC_FARM_ARC0_AUX_MME_ARC_UPPER_DCCM_EN},
1715 	{mmARC_FARM_ARC0_DUP_ENG_DUP_TPC_ENG_ADDR_0, mmARC_FARM_ARC0_DUP_ENG_ARC_CID_OFFSET_63},
1716 	{mmARC_FARM_ARC0_DUP_ENG_AXUSER_HB_STRONG_ORDER, mmARC_FARM_ARC0_DUP_ENG_AXUSER_LB_OVRD},
1717 	{mmARC_FARM_ARC0_ACP_ENG_ACP_PI_REG_0, mmARC_FARM_ARC0_ACP_ENG_ACP_DBG_REG},
1718 };
1719 
1720 static const u32 gaudi2_pb_xbar_mid[] = {
1721 	mmXBAR_MID_0_BASE,
1722 };
1723 
1724 static const u32 gaudi2_pb_xbar_mid_unsecured_regs[] = {
1725 	mmXBAR_MID_0_UPSCALE,
1726 	mmXBAR_MID_0_DOWN_CONV,
1727 	mmXBAR_MID_0_DOWN_CONV_LFSR_EN,
1728 	mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VLD,
1729 	mmXBAR_MID_0_DOWN_CONV_LFSR_SET_VALUE,
1730 	mmXBAR_MID_0_DOWN_CONV_LFSR_CFG_POLY,
1731 };
1732 
1733 static const u32 gaudi2_pb_xbar_edge[] = {
1734 	mmXBAR_EDGE_0_BASE,
1735 };
1736 
1737 static const u32 gaudi2_pb_xbar_edge_unsecured_regs[] = {
1738 	mmXBAR_EDGE_0_UPSCALE,
1739 	mmXBAR_EDGE_0_DOWN_CONV,
1740 	mmXBAR_EDGE_0_DOWN_CONV_LFSR_EN,
1741 	mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VLD,
1742 	mmXBAR_EDGE_0_DOWN_CONV_LFSR_SET_VALUE,
1743 	mmXBAR_EDGE_0_DOWN_CONV_LFSR_CFG_POLY,
1744 };
1745 
1746 static const u32 gaudi2_pb_nic0[] = {
1747 	mmNIC0_TMR_BASE,
1748 	mmNIC0_RXB_CORE_BASE,
1749 	mmNIC0_RXE0_BASE,
1750 	mmNIC0_RXE1_BASE,
1751 	mmNIC0_RXE0_AXUSER_AXUSER_CQ0_BASE,
1752 	mmNIC0_RXE1_AXUSER_AXUSER_CQ0_BASE,
1753 	mmNIC0_TXS0_BASE,
1754 	mmNIC0_TXS1_BASE,
1755 	mmNIC0_TXE0_BASE,
1756 	mmNIC0_TXE1_BASE,
1757 	mmNIC0_TXB_BASE,
1758 	mmNIC0_MSTR_IF_RR_SHRD_HBW_BASE,
1759 };
1760 
1761 static const u32 gaudi2_pb_nic0_qm_qpc[] = {
1762 	mmNIC0_QM0_BASE,
1763 	mmNIC0_QPC0_BASE,
1764 };
1765 
1766 static const u32 gaudi2_pb_nic0_qm_arc_aux0[] = {
1767 	mmNIC0_QM_ARC_AUX0_BASE,
1768 };
1769 
1770 static const struct range gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs[] = {
1771 	{mmNIC0_QM_ARC_AUX0_RUN_HALT_REQ, mmNIC0_QM_ARC_AUX0_RUN_HALT_ACK},
1772 	{mmNIC0_QM_ARC_AUX0_CLUSTER_NUM, mmNIC0_QM_ARC_AUX0_WAKE_UP_EVENT},
1773 	{mmNIC0_QM_ARC_AUX0_ARC_RST_REQ, mmNIC0_QM_ARC_AUX0_CID_OFFSET_7},
1774 	{mmNIC0_QM_ARC_AUX0_SCRATCHPAD_0, mmNIC0_QM_ARC_AUX0_INFLIGHT_LBU_RD_CNT},
1775 	{mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_CBU_EARLY_BRESP_EN},
1776 	{mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN, mmNIC0_QM_ARC_AUX0_LBU_EARLY_BRESP_EN},
1777 	{mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_BASE_ADDR_0, mmNIC0_QM_ARC_AUX0_DCCM_QUEUE_ALERT_MSG},
1778 	{mmNIC0_QM_ARC_AUX0_DCCM_Q_PUSH_FIFO_CNT, mmNIC0_QM_ARC_AUX0_QMAN_ARC_CQ_SHADOW_CI},
1779 	{mmNIC0_QM_ARC_AUX0_ARC_AXI_ORDERING_WR_IF_CNT, mmNIC0_QM_ARC_AUX0_MME_ARC_UPPER_DCCM_EN},
1780 };
1781 
1782 static const u32 gaudi2_pb_nic0_umr[] = {
1783 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE,
1784 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1785 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1786 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1787 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1788 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1789 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1790 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1791 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1792 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1793 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1794 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1795 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1796 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1797 	mmNIC0_UMR0_0_UNSECURE_DOORBELL0_BASE + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1798 };
1799 
1800 static const struct range gaudi2_pb_nic0_umr_unsecured_regs[] = {
1801 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32,
1802 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX},
1803 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 1, /* UMR0_1 */
1804 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 1},
1805 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 2, /* UMR0_2 */
1806 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 2},
1807 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 3, /* UMR0_3 */
1808 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 3},
1809 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 4, /* UMR0_4 */
1810 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 4},
1811 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 5, /* UMR0_5 */
1812 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 5},
1813 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 6, /* UMR0_6 */
1814 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 6},
1815 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 7, /* UMR0_7 */
1816 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 7},
1817 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 8, /* UMR0_8 */
1818 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 8},
1819 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 9, /* UMR0_9 */
1820 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 9},
1821 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 10, /* UMR0_10 */
1822 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 10},
1823 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 11, /* UMR0_11 */
1824 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 11},
1825 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 12, /* UMR0_12 */
1826 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 12},
1827 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 13, /* UMR0_13 */
1828 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 13},
1829 	{mmNIC0_UMR0_0_UNSECURE_DOORBELL0_UNSECURE_DB_FIRST32 + HL_BLOCK_SIZE * 14, /* UMR0_14 */
1830 		mmNIC0_UMR0_0_COMPLETION_QUEUE_CI_1_CQ_CONSUMER_INDEX + HL_BLOCK_SIZE * 14},
1831 };
1832 
1833 /*
1834  * mmNIC0_QPC0_LINEAR_WQE_QPN and mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN are 32-bit
1835  * registers and since the user writes in bulks of 64 bits we need to un-secure
1836  * also the following 32 bits (that's why we added also the next 4 bytes to the
1837  * table). In the RTL, as part of ECO (2874), writing to the next 4 bytes
1838  * triggers a write to the SPECIAL_GLBL_SPARE register, hence it's must be
1839  * unsecured as well.
1840  */
1841 #define mmNIC0_QPC0_LINEAR_WQE_RSV (mmNIC0_QPC0_LINEAR_WQE_QPN + 4)
1842 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV (mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN + 4)
1843 #define mmNIC0_QPC0_SPECIAL_GLBL_SPARE 0x541FF60
1844 
1845 static const u32 gaudi2_pb_nic0_qm_qpc_unsecured_regs[] = {
1846 	mmNIC0_QPC0_LINEAR_WQE_STATIC_0,
1847 	mmNIC0_QPC0_LINEAR_WQE_STATIC_1,
1848 	mmNIC0_QPC0_LINEAR_WQE_STATIC_2,
1849 	mmNIC0_QPC0_LINEAR_WQE_STATIC_3,
1850 	mmNIC0_QPC0_LINEAR_WQE_STATIC_4,
1851 	mmNIC0_QPC0_LINEAR_WQE_STATIC_5,
1852 	mmNIC0_QPC0_LINEAR_WQE_STATIC_6,
1853 	mmNIC0_QPC0_LINEAR_WQE_STATIC_7,
1854 	mmNIC0_QPC0_LINEAR_WQE_STATIC_8,
1855 	mmNIC0_QPC0_LINEAR_WQE_STATIC_9,
1856 	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0,
1857 	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1,
1858 	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2,
1859 	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3,
1860 	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4,
1861 	mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5,
1862 	mmNIC0_QPC0_LINEAR_WQE_QPN,
1863 	mmNIC0_QPC0_LINEAR_WQE_RSV,
1864 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0,
1865 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1,
1866 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2,
1867 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3,
1868 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4,
1869 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5,
1870 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6,
1871 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7,
1872 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8,
1873 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9,
1874 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10,
1875 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11,
1876 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12,
1877 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13,
1878 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14,
1879 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15,
1880 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16,
1881 	mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17,
1882 	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0,
1883 	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1,
1884 	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2,
1885 	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3,
1886 	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4,
1887 	mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5,
1888 	mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN,
1889 	mmNIC0_QPC0_MULTI_STRIDE_WQE_RSV,
1890 	mmNIC0_QPC0_QMAN_DOORBELL,
1891 	mmNIC0_QPC0_QMAN_DOORBELL_QPN,
1892 	mmNIC0_QPC0_SPECIAL_GLBL_SPARE,
1893 	mmNIC0_QM0_CQ_CFG0_0,
1894 	mmNIC0_QM0_CQ_CFG0_1,
1895 	mmNIC0_QM0_CQ_CFG0_2,
1896 	mmNIC0_QM0_CQ_CFG0_3,
1897 	mmNIC0_QM0_CQ_CFG0_4,
1898 	mmNIC0_QM0_CP_FENCE0_RDATA_0,
1899 	mmNIC0_QM0_CP_FENCE0_RDATA_1,
1900 	mmNIC0_QM0_CP_FENCE0_RDATA_2,
1901 	mmNIC0_QM0_CP_FENCE0_RDATA_3,
1902 	mmNIC0_QM0_CP_FENCE0_RDATA_4,
1903 	mmNIC0_QM0_CP_FENCE1_RDATA_0,
1904 	mmNIC0_QM0_CP_FENCE1_RDATA_1,
1905 	mmNIC0_QM0_CP_FENCE1_RDATA_2,
1906 	mmNIC0_QM0_CP_FENCE1_RDATA_3,
1907 	mmNIC0_QM0_CP_FENCE1_RDATA_4,
1908 	mmNIC0_QM0_CP_FENCE2_RDATA_0,
1909 	mmNIC0_QM0_CP_FENCE2_RDATA_1,
1910 	mmNIC0_QM0_CP_FENCE2_RDATA_2,
1911 	mmNIC0_QM0_CP_FENCE2_RDATA_3,
1912 	mmNIC0_QM0_CP_FENCE2_RDATA_4,
1913 	mmNIC0_QM0_CP_FENCE3_RDATA_0,
1914 	mmNIC0_QM0_CP_FENCE3_RDATA_1,
1915 	mmNIC0_QM0_CP_FENCE3_RDATA_2,
1916 	mmNIC0_QM0_CP_FENCE3_RDATA_3,
1917 	mmNIC0_QM0_CP_FENCE3_RDATA_4,
1918 	mmNIC0_QM0_CP_FENCE0_CNT_0,
1919 	mmNIC0_QM0_CP_FENCE0_CNT_1,
1920 	mmNIC0_QM0_CP_FENCE0_CNT_2,
1921 	mmNIC0_QM0_CP_FENCE0_CNT_3,
1922 	mmNIC0_QM0_CP_FENCE0_CNT_4,
1923 	mmNIC0_QM0_CP_FENCE1_CNT_0,
1924 	mmNIC0_QM0_CP_FENCE1_CNT_1,
1925 	mmNIC0_QM0_CP_FENCE1_CNT_2,
1926 	mmNIC0_QM0_CP_FENCE1_CNT_3,
1927 	mmNIC0_QM0_CP_FENCE1_CNT_4,
1928 	mmNIC0_QM0_CP_FENCE2_CNT_0,
1929 	mmNIC0_QM0_CP_FENCE2_CNT_1,
1930 	mmNIC0_QM0_CP_FENCE2_CNT_2,
1931 	mmNIC0_QM0_CP_FENCE2_CNT_3,
1932 	mmNIC0_QM0_CP_FENCE2_CNT_4,
1933 	mmNIC0_QM0_CP_FENCE3_CNT_0,
1934 	mmNIC0_QM0_CP_FENCE3_CNT_1,
1935 	mmNIC0_QM0_CP_FENCE3_CNT_2,
1936 	mmNIC0_QM0_CP_FENCE3_CNT_3,
1937 	mmNIC0_QM0_CP_FENCE3_CNT_4,
1938 	mmNIC0_QM0_CQ_PTR_LO_0,
1939 	mmNIC0_QM0_CQ_PTR_HI_0,
1940 	mmNIC0_QM0_CQ_TSIZE_0,
1941 	mmNIC0_QM0_CQ_CTL_0,
1942 	mmNIC0_QM0_CQ_PTR_LO_1,
1943 	mmNIC0_QM0_CQ_PTR_HI_1,
1944 	mmNIC0_QM0_CQ_TSIZE_1,
1945 	mmNIC0_QM0_CQ_CTL_1,
1946 	mmNIC0_QM0_CQ_PTR_LO_2,
1947 	mmNIC0_QM0_CQ_PTR_HI_2,
1948 	mmNIC0_QM0_CQ_TSIZE_2,
1949 	mmNIC0_QM0_CQ_CTL_2,
1950 	mmNIC0_QM0_CQ_PTR_LO_3,
1951 	mmNIC0_QM0_CQ_PTR_HI_3,
1952 	mmNIC0_QM0_CQ_TSIZE_3,
1953 	mmNIC0_QM0_CQ_CTL_3,
1954 	mmNIC0_QM0_CQ_PTR_LO_4,
1955 	mmNIC0_QM0_CQ_PTR_HI_4,
1956 	mmNIC0_QM0_CQ_TSIZE_4,
1957 	mmNIC0_QM0_CQ_CTL_4,
1958 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE,
1959 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR0_BASE + 4,
1960 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE,
1961 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR1_BASE + 4,
1962 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE,
1963 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR2_BASE + 4,
1964 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE,
1965 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR3_BASE + 4,
1966 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE,
1967 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR4_BASE + 4,
1968 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE,
1969 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR5_BASE + 4,
1970 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE,
1971 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR6_BASE + 4,
1972 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE,
1973 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR7_BASE + 4,
1974 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE,
1975 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR8_BASE + 4,
1976 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE,
1977 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR9_BASE + 4,
1978 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE,
1979 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR10_BASE + 4,
1980 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE,
1981 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR11_BASE + 4,
1982 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE,
1983 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR12_BASE + 4,
1984 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE,
1985 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR13_BASE + 4,
1986 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE,
1987 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR14_BASE + 4,
1988 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE,
1989 	mmNIC0_QM0_QMAN_WR64_BASE_ADDR15_BASE + 4,
1990 	mmNIC0_QM0_ARC_CQ_PTR_LO,
1991 	mmNIC0_QM0_ARC_CQ_PTR_LO_STS,
1992 	mmNIC0_QM0_ARC_CQ_PTR_HI,
1993 	mmNIC0_QM0_ARC_CQ_PTR_HI_STS,
1994 	mmNIC0_QM0_ARB_CFG_0,
1995 	mmNIC0_QM0_ARB_MST_QUIET_PER,
1996 	mmNIC0_QM0_ARB_CHOICE_Q_PUSH,
1997 	mmNIC0_QM0_ARB_WRR_WEIGHT_0,
1998 	mmNIC0_QM0_ARB_WRR_WEIGHT_1,
1999 	mmNIC0_QM0_ARB_WRR_WEIGHT_2,
2000 	mmNIC0_QM0_ARB_WRR_WEIGHT_3,
2001 	mmNIC0_QM0_ARB_BASE_LO,
2002 	mmNIC0_QM0_ARB_BASE_HI,
2003 	mmNIC0_QM0_ARB_MST_SLAVE_EN,
2004 	mmNIC0_QM0_ARB_MST_SLAVE_EN_1,
2005 	mmNIC0_QM0_ARB_MST_CRED_INC,
2006 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_0,
2007 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_1,
2008 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_2,
2009 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_3,
2010 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_4,
2011 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_5,
2012 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_6,
2013 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_7,
2014 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_8,
2015 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_9,
2016 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_10,
2017 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_11,
2018 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_12,
2019 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_13,
2020 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_14,
2021 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_15,
2022 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_16,
2023 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_17,
2024 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_18,
2025 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_19,
2026 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_20,
2027 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_21,
2028 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_22,
2029 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_23,
2030 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_24,
2031 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_25,
2032 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_26,
2033 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_27,
2034 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_28,
2035 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_29,
2036 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_30,
2037 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_31,
2038 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_32,
2039 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_33,
2040 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_34,
2041 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_35,
2042 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_36,
2043 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_37,
2044 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_38,
2045 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_39,
2046 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_40,
2047 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_41,
2048 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_42,
2049 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_43,
2050 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_44,
2051 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_45,
2052 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_46,
2053 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_47,
2054 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_48,
2055 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_49,
2056 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_50,
2057 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_51,
2058 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_52,
2059 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_53,
2060 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_54,
2061 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_55,
2062 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_56,
2063 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_57,
2064 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_58,
2065 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_59,
2066 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_60,
2067 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_61,
2068 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_62,
2069 	mmNIC0_QM0_ARB_MST_CHOICE_PUSH_OFST_63,
2070 	mmNIC0_QM0_ARB_SLV_ID,
2071 	mmNIC0_QM0_ARB_SLV_MASTER_INC_CRED_OFST,
2072 	mmNIC0_QM0_ARC_CQ_CFG0,
2073 	mmNIC0_QM0_CQ_IFIFO_CI_0,
2074 	mmNIC0_QM0_CQ_IFIFO_CI_1,
2075 	mmNIC0_QM0_CQ_IFIFO_CI_2,
2076 	mmNIC0_QM0_CQ_IFIFO_CI_3,
2077 	mmNIC0_QM0_CQ_IFIFO_CI_4,
2078 	mmNIC0_QM0_ARC_CQ_IFIFO_CI,
2079 	mmNIC0_QM0_CQ_CTL_CI_0,
2080 	mmNIC0_QM0_CQ_CTL_CI_1,
2081 	mmNIC0_QM0_CQ_CTL_CI_2,
2082 	mmNIC0_QM0_CQ_CTL_CI_3,
2083 	mmNIC0_QM0_CQ_CTL_CI_4,
2084 	mmNIC0_QM0_ARC_CQ_CTL_CI,
2085 	mmNIC0_QM0_ARC_CQ_TSIZE,
2086 	mmNIC0_QM0_ARC_CQ_CTL,
2087 	mmNIC0_QM0_CP_SWITCH_WD_SET,
2088 	mmNIC0_QM0_CP_EXT_SWITCH,
2089 	mmNIC0_QM0_CP_PRED_0,
2090 	mmNIC0_QM0_CP_PRED_1,
2091 	mmNIC0_QM0_CP_PRED_2,
2092 	mmNIC0_QM0_CP_PRED_3,
2093 	mmNIC0_QM0_CP_PRED_4,
2094 	mmNIC0_QM0_CP_PRED_UPEN_0,
2095 	mmNIC0_QM0_CP_PRED_UPEN_1,
2096 	mmNIC0_QM0_CP_PRED_UPEN_2,
2097 	mmNIC0_QM0_CP_PRED_UPEN_3,
2098 	mmNIC0_QM0_CP_PRED_UPEN_4,
2099 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_0,
2100 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_1,
2101 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_2,
2102 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_3,
2103 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_LO_4,
2104 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_0,
2105 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_1,
2106 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_2,
2107 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_3,
2108 	mmNIC0_QM0_CP_MSG_BASE0_ADDR_HI_4,
2109 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_0,
2110 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_1,
2111 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_2,
2112 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_3,
2113 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_LO_4,
2114 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_0,
2115 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_1,
2116 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_2,
2117 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_3,
2118 	mmNIC0_QM0_CP_MSG_BASE1_ADDR_HI_4,
2119 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_0,
2120 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_1,
2121 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_2,
2122 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_3,
2123 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_LO_4,
2124 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_0,
2125 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_1,
2126 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_2,
2127 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_3,
2128 	mmNIC0_QM0_CP_MSG_BASE2_ADDR_HI_4,
2129 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_0,
2130 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_1,
2131 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_2,
2132 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_3,
2133 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_LO_4,
2134 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_0,
2135 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_1,
2136 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_2,
2137 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_3,
2138 	mmNIC0_QM0_CP_MSG_BASE3_ADDR_HI_4,
2139 	mmNIC0_QM0_ARC_CQ_IFIFO_MSG_BASE_LO,
2140 	mmNIC0_QM0_ARC_CQ_CTL_MSG_BASE_LO,
2141 	mmNIC0_QM0_CQ_IFIFO_MSG_BASE_LO,
2142 	mmNIC0_QM0_CQ_CTL_MSG_BASE_LO
2143 };
2144 
2145 static const u32 gaudi2_pb_rot0[] = {
2146 	mmROT0_BASE,
2147 	mmROT0_MSTR_IF_RR_SHRD_HBW_BASE,
2148 	mmROT0_QM_BASE,
2149 };
2150 
2151 static const u32 gaudi2_pb_rot0_arc[] = {
2152 	mmROT0_QM_ARC_AUX_BASE
2153 };
2154 
2155 static const struct range gaudi2_pb_rot0_arc_unsecured_regs[] = {
2156 	{mmROT0_QM_ARC_AUX_RUN_HALT_REQ, mmROT0_QM_ARC_AUX_RUN_HALT_ACK},
2157 	{mmROT0_QM_ARC_AUX_CLUSTER_NUM, mmROT0_QM_ARC_AUX_WAKE_UP_EVENT},
2158 	{mmROT0_QM_ARC_AUX_ARC_RST_REQ, mmROT0_QM_ARC_AUX_CID_OFFSET_7},
2159 	{mmROT0_QM_ARC_AUX_SCRATCHPAD_0, mmROT0_QM_ARC_AUX_INFLIGHT_LBU_RD_CNT},
2160 	{mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_CBU_EARLY_BRESP_EN},
2161 	{mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN, mmROT0_QM_ARC_AUX_LBU_EARLY_BRESP_EN},
2162 	{mmROT0_QM_ARC_AUX_DCCM_QUEUE_BASE_ADDR_0, mmROT0_QM_ARC_AUX_DCCM_QUEUE_ALERT_MSG},
2163 	{mmROT0_QM_ARC_AUX_DCCM_Q_PUSH_FIFO_CNT, mmROT0_QM_ARC_AUX_QMAN_ARC_CQ_SHADOW_CI},
2164 	{mmROT0_QM_ARC_AUX_ARC_AXI_ORDERING_WR_IF_CNT, mmROT0_QM_ARC_AUX_MME_ARC_UPPER_DCCM_EN},
2165 };
2166 
2167 static const u32 gaudi2_pb_rot0_unsecured_regs[] = {
2168 	mmROT0_QM_CQ_CFG0_0,
2169 	mmROT0_QM_CQ_CFG0_1,
2170 	mmROT0_QM_CQ_CFG0_2,
2171 	mmROT0_QM_CQ_CFG0_3,
2172 	mmROT0_QM_CQ_CFG0_4,
2173 	mmROT0_QM_CP_FENCE0_RDATA_0,
2174 	mmROT0_QM_CP_FENCE0_RDATA_1,
2175 	mmROT0_QM_CP_FENCE0_RDATA_2,
2176 	mmROT0_QM_CP_FENCE0_RDATA_3,
2177 	mmROT0_QM_CP_FENCE0_RDATA_4,
2178 	mmROT0_QM_CP_FENCE1_RDATA_0,
2179 	mmROT0_QM_CP_FENCE1_RDATA_1,
2180 	mmROT0_QM_CP_FENCE1_RDATA_2,
2181 	mmROT0_QM_CP_FENCE1_RDATA_3,
2182 	mmROT0_QM_CP_FENCE1_RDATA_4,
2183 	mmROT0_QM_CP_FENCE2_RDATA_0,
2184 	mmROT0_QM_CP_FENCE2_RDATA_1,
2185 	mmROT0_QM_CP_FENCE2_RDATA_2,
2186 	mmROT0_QM_CP_FENCE2_RDATA_3,
2187 	mmROT0_QM_CP_FENCE2_RDATA_4,
2188 	mmROT0_QM_CP_FENCE3_RDATA_0,
2189 	mmROT0_QM_CP_FENCE3_RDATA_1,
2190 	mmROT0_QM_CP_FENCE3_RDATA_2,
2191 	mmROT0_QM_CP_FENCE3_RDATA_3,
2192 	mmROT0_QM_CP_FENCE3_RDATA_4,
2193 	mmROT0_QM_CP_FENCE0_CNT_0,
2194 	mmROT0_QM_CP_FENCE0_CNT_1,
2195 	mmROT0_QM_CP_FENCE0_CNT_2,
2196 	mmROT0_QM_CP_FENCE0_CNT_3,
2197 	mmROT0_QM_CP_FENCE0_CNT_4,
2198 	mmROT0_QM_CP_FENCE1_CNT_0,
2199 	mmROT0_QM_CP_FENCE1_CNT_1,
2200 	mmROT0_QM_CP_FENCE1_CNT_2,
2201 	mmROT0_QM_CP_FENCE1_CNT_3,
2202 	mmROT0_QM_CP_FENCE1_CNT_4,
2203 	mmROT0_QM_CP_FENCE2_CNT_0,
2204 	mmROT0_QM_CP_FENCE2_CNT_1,
2205 	mmROT0_QM_CP_FENCE2_CNT_2,
2206 	mmROT0_QM_CP_FENCE2_CNT_3,
2207 	mmROT0_QM_CP_FENCE2_CNT_4,
2208 	mmROT0_QM_CP_FENCE3_CNT_0,
2209 	mmROT0_QM_CP_FENCE3_CNT_1,
2210 	mmROT0_QM_CP_FENCE3_CNT_2,
2211 	mmROT0_QM_CP_FENCE3_CNT_3,
2212 	mmROT0_QM_CP_FENCE3_CNT_4,
2213 	mmROT0_QM_CQ_PTR_LO_0,
2214 	mmROT0_QM_CQ_PTR_HI_0,
2215 	mmROT0_QM_CQ_TSIZE_0,
2216 	mmROT0_QM_CQ_CTL_0,
2217 	mmROT0_QM_CQ_PTR_LO_1,
2218 	mmROT0_QM_CQ_PTR_HI_1,
2219 	mmROT0_QM_CQ_TSIZE_1,
2220 	mmROT0_QM_CQ_CTL_1,
2221 	mmROT0_QM_CQ_PTR_LO_2,
2222 	mmROT0_QM_CQ_PTR_HI_2,
2223 	mmROT0_QM_CQ_TSIZE_2,
2224 	mmROT0_QM_CQ_CTL_2,
2225 	mmROT0_QM_CQ_PTR_LO_3,
2226 	mmROT0_QM_CQ_PTR_HI_3,
2227 	mmROT0_QM_CQ_TSIZE_3,
2228 	mmROT0_QM_CQ_CTL_3,
2229 	mmROT0_QM_CQ_PTR_LO_4,
2230 	mmROT0_QM_CQ_PTR_HI_4,
2231 	mmROT0_QM_CQ_TSIZE_4,
2232 	mmROT0_QM_CQ_CTL_4,
2233 	mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE,
2234 	mmROT0_QM_QMAN_WR64_BASE_ADDR0_BASE + 4,
2235 	mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE,
2236 	mmROT0_QM_QMAN_WR64_BASE_ADDR1_BASE + 4,
2237 	mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE,
2238 	mmROT0_QM_QMAN_WR64_BASE_ADDR2_BASE + 4,
2239 	mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE,
2240 	mmROT0_QM_QMAN_WR64_BASE_ADDR3_BASE + 4,
2241 	mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE,
2242 	mmROT0_QM_QMAN_WR64_BASE_ADDR4_BASE + 4,
2243 	mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE,
2244 	mmROT0_QM_QMAN_WR64_BASE_ADDR5_BASE + 4,
2245 	mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE,
2246 	mmROT0_QM_QMAN_WR64_BASE_ADDR6_BASE + 4,
2247 	mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE,
2248 	mmROT0_QM_QMAN_WR64_BASE_ADDR7_BASE + 4,
2249 	mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE,
2250 	mmROT0_QM_QMAN_WR64_BASE_ADDR8_BASE + 4,
2251 	mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE,
2252 	mmROT0_QM_QMAN_WR64_BASE_ADDR9_BASE + 4,
2253 	mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE,
2254 	mmROT0_QM_QMAN_WR64_BASE_ADDR10_BASE + 4,
2255 	mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE,
2256 	mmROT0_QM_QMAN_WR64_BASE_ADDR11_BASE + 4,
2257 	mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE,
2258 	mmROT0_QM_QMAN_WR64_BASE_ADDR12_BASE + 4,
2259 	mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE,
2260 	mmROT0_QM_QMAN_WR64_BASE_ADDR13_BASE + 4,
2261 	mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE,
2262 	mmROT0_QM_QMAN_WR64_BASE_ADDR14_BASE + 4,
2263 	mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE,
2264 	mmROT0_QM_QMAN_WR64_BASE_ADDR15_BASE + 4,
2265 	mmROT0_QM_ARC_CQ_PTR_LO,
2266 	mmROT0_QM_ARC_CQ_PTR_LO_STS,
2267 	mmROT0_QM_ARC_CQ_PTR_HI,
2268 	mmROT0_QM_ARC_CQ_PTR_HI_STS,
2269 	mmROT0_QM_ARB_CFG_0,
2270 	mmROT0_QM_ARB_MST_QUIET_PER,
2271 	mmROT0_QM_ARB_CHOICE_Q_PUSH,
2272 	mmROT0_QM_ARB_WRR_WEIGHT_0,
2273 	mmROT0_QM_ARB_WRR_WEIGHT_1,
2274 	mmROT0_QM_ARB_WRR_WEIGHT_2,
2275 	mmROT0_QM_ARB_WRR_WEIGHT_3,
2276 	mmROT0_QM_ARB_BASE_LO,
2277 	mmROT0_QM_ARB_BASE_HI,
2278 	mmROT0_QM_ARB_MST_SLAVE_EN,
2279 	mmROT0_QM_ARB_MST_SLAVE_EN_1,
2280 	mmROT0_QM_ARB_MST_CRED_INC,
2281 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_0,
2282 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_1,
2283 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_2,
2284 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_3,
2285 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_4,
2286 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_5,
2287 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_6,
2288 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_7,
2289 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_8,
2290 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_9,
2291 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_10,
2292 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_11,
2293 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_12,
2294 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_13,
2295 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_14,
2296 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_15,
2297 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_16,
2298 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_17,
2299 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_18,
2300 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_19,
2301 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_20,
2302 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_21,
2303 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_22,
2304 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_23,
2305 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_24,
2306 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_25,
2307 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_26,
2308 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_27,
2309 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_28,
2310 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_29,
2311 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_30,
2312 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_31,
2313 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_32,
2314 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_33,
2315 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_34,
2316 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_35,
2317 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_36,
2318 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_37,
2319 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_38,
2320 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_39,
2321 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_40,
2322 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_41,
2323 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_42,
2324 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_43,
2325 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_44,
2326 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_45,
2327 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_46,
2328 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_47,
2329 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_48,
2330 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_49,
2331 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_50,
2332 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_51,
2333 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_52,
2334 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_53,
2335 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_54,
2336 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_55,
2337 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_56,
2338 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_57,
2339 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_58,
2340 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_59,
2341 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_60,
2342 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_61,
2343 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_62,
2344 	mmROT0_QM_ARB_MST_CHOICE_PUSH_OFST_63,
2345 	mmROT0_QM_ARB_SLV_ID,
2346 	mmROT0_QM_ARB_SLV_MASTER_INC_CRED_OFST,
2347 	mmROT0_QM_ARC_CQ_CFG0,
2348 	mmROT0_QM_CQ_IFIFO_CI_0,
2349 	mmROT0_QM_CQ_IFIFO_CI_1,
2350 	mmROT0_QM_CQ_IFIFO_CI_2,
2351 	mmROT0_QM_CQ_IFIFO_CI_3,
2352 	mmROT0_QM_CQ_IFIFO_CI_4,
2353 	mmROT0_QM_ARC_CQ_IFIFO_CI,
2354 	mmROT0_QM_CQ_CTL_CI_0,
2355 	mmROT0_QM_CQ_CTL_CI_1,
2356 	mmROT0_QM_CQ_CTL_CI_2,
2357 	mmROT0_QM_CQ_CTL_CI_3,
2358 	mmROT0_QM_CQ_CTL_CI_4,
2359 	mmROT0_QM_ARC_CQ_CTL_CI,
2360 	mmROT0_QM_ARC_CQ_TSIZE,
2361 	mmROT0_QM_ARC_CQ_CTL,
2362 	mmROT0_QM_CP_SWITCH_WD_SET,
2363 	mmROT0_QM_CP_EXT_SWITCH,
2364 	mmROT0_QM_CP_PRED_0,
2365 	mmROT0_QM_CP_PRED_1,
2366 	mmROT0_QM_CP_PRED_2,
2367 	mmROT0_QM_CP_PRED_3,
2368 	mmROT0_QM_CP_PRED_4,
2369 	mmROT0_QM_CP_PRED_UPEN_0,
2370 	mmROT0_QM_CP_PRED_UPEN_1,
2371 	mmROT0_QM_CP_PRED_UPEN_2,
2372 	mmROT0_QM_CP_PRED_UPEN_3,
2373 	mmROT0_QM_CP_PRED_UPEN_4,
2374 	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_0,
2375 	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_1,
2376 	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_2,
2377 	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_3,
2378 	mmROT0_QM_CP_MSG_BASE0_ADDR_LO_4,
2379 	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_0,
2380 	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_1,
2381 	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_2,
2382 	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_3,
2383 	mmROT0_QM_CP_MSG_BASE0_ADDR_HI_4,
2384 	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_0,
2385 	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_1,
2386 	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_2,
2387 	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_3,
2388 	mmROT0_QM_CP_MSG_BASE1_ADDR_LO_4,
2389 	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_0,
2390 	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_1,
2391 	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_2,
2392 	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_3,
2393 	mmROT0_QM_CP_MSG_BASE1_ADDR_HI_4,
2394 	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_0,
2395 	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_1,
2396 	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_2,
2397 	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_3,
2398 	mmROT0_QM_CP_MSG_BASE2_ADDR_LO_4,
2399 	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_0,
2400 	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_1,
2401 	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_2,
2402 	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_3,
2403 	mmROT0_QM_CP_MSG_BASE2_ADDR_HI_4,
2404 	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_0,
2405 	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_1,
2406 	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_2,
2407 	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_3,
2408 	mmROT0_QM_CP_MSG_BASE3_ADDR_LO_4,
2409 	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_0,
2410 	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_1,
2411 	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_2,
2412 	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_3,
2413 	mmROT0_QM_CP_MSG_BASE3_ADDR_HI_4,
2414 	mmROT0_QM_ARC_CQ_IFIFO_MSG_BASE_LO,
2415 	mmROT0_QM_ARC_CQ_CTL_MSG_BASE_LO,
2416 	mmROT0_QM_CQ_IFIFO_MSG_BASE_LO,
2417 	mmROT0_QM_CQ_CTL_MSG_BASE_LO,
2418 	mmROT0_DESC_CONTEXT_ID,
2419 	mmROT0_DESC_IN_IMG_START_ADDR_L,
2420 	mmROT0_DESC_IN_IMG_START_ADDR_H,
2421 	mmROT0_DESC_OUT_IMG_START_ADDR_L,
2422 	mmROT0_DESC_OUT_IMG_START_ADDR_H,
2423 	mmROT0_DESC_CFG,
2424 	mmROT0_DESC_IM_READ_SLOPE,
2425 	mmROT0_DESC_SIN_D,
2426 	mmROT0_DESC_COS_D,
2427 	mmROT0_DESC_IN_IMG,
2428 	mmROT0_DESC_IN_STRIDE,
2429 	mmROT0_DESC_IN_STRIPE,
2430 	mmROT0_DESC_IN_CENTER,
2431 	mmROT0_DESC_OUT_IMG,
2432 	mmROT0_DESC_OUT_STRIDE,
2433 	mmROT0_DESC_OUT_STRIPE,
2434 	mmROT0_DESC_OUT_CENTER,
2435 	mmROT0_DESC_BACKGROUND,
2436 	mmROT0_DESC_CPL_MSG_EN,
2437 	mmROT0_DESC_IDLE_STATE,
2438 	mmROT0_DESC_CPL_MSG_ADDR,
2439 	mmROT0_DESC_CPL_MSG_DATA,
2440 	mmROT0_DESC_X_I_START_OFFSET,
2441 	mmROT0_DESC_X_I_START_OFFSET_FLIP,
2442 	mmROT0_DESC_X_I_FIRST,
2443 	mmROT0_DESC_Y_I_FIRST,
2444 	mmROT0_DESC_Y_I,
2445 	mmROT0_DESC_OUT_STRIPE_SIZE,
2446 	mmROT0_DESC_RSB_CFG_0,
2447 	mmROT0_DESC_RSB_PAD_VAL,
2448 	mmROT0_DESC_OWM_CFG,
2449 	mmROT0_DESC_CTRL_CFG,
2450 	mmROT0_DESC_PIXEL_PAD,
2451 	mmROT0_DESC_PREC_SHIFT,
2452 	mmROT0_DESC_MAX_VAL,
2453 	mmROT0_DESC_A0_M11,
2454 	mmROT0_DESC_A1_M12,
2455 	mmROT0_DESC_A2,
2456 	mmROT0_DESC_B0_M21,
2457 	mmROT0_DESC_B1_M22,
2458 	mmROT0_DESC_B2,
2459 	mmROT0_DESC_C0,
2460 	mmROT0_DESC_C1,
2461 	mmROT0_DESC_C2,
2462 	mmROT0_DESC_D0,
2463 	mmROT0_DESC_D1,
2464 	mmROT0_DESC_D2,
2465 	mmROT0_DESC_INV_PROC_SIZE_M_1,
2466 	mmROT0_DESC_MESH_IMG_START_ADDR_L,
2467 	mmROT0_DESC_MESH_IMG_START_ADDR_H,
2468 	mmROT0_DESC_MESH_IMG,
2469 	mmROT0_DESC_MESH_STRIDE,
2470 	mmROT0_DESC_MESH_STRIPE,
2471 	mmROT0_DESC_MESH_CTRL,
2472 	mmROT0_DESC_MESH_GH,
2473 	mmROT0_DESC_MESH_GV,
2474 	mmROT0_DESC_MRSB_CFG_0,
2475 	mmROT0_DESC_MRSB_PAD_VAL,
2476 	mmROT0_DESC_BUF_CFG,
2477 	mmROT0_DESC_CID_OFFSET,
2478 	mmROT0_DESC_PUSH_DESC
2479 };
2480 
2481 static const u32 gaudi2_pb_psoc_global_conf[] = {
2482 	mmPSOC_GLOBAL_CONF_BASE
2483 };
2484 
2485 static const u32 gaudi2_pb_psoc[] = {
2486 	mmPSOC_EFUSE_BASE,
2487 	mmPSOC_BTL_BASE,
2488 	mmPSOC_CS_TRACE_BASE,
2489 	mmPSOC_DFT_EFUSE_BASE,
2490 	mmPSOC_PID_BASE,
2491 	mmPSOC_ARC0_CFG_BASE,
2492 	mmPSOC_ARC0_MSTR_IF_RR_SHRD_HBW_BASE,
2493 	mmPSOC_ARC0_AUX_BASE,
2494 	mmPSOC_ARC1_CFG_BASE,
2495 	mmPSOC_ARC1_MSTR_IF_RR_SHRD_HBW_BASE,
2496 	mmPSOC_ARC1_AUX_BASE,
2497 	mmJT_MSTR_IF_RR_SHRD_HBW_BASE,
2498 	mmSMI_MSTR_IF_RR_SHRD_HBW_BASE,
2499 	mmI2C_S_MSTR_IF_RR_SHRD_HBW_BASE,
2500 	mmPSOC_SVID0_BASE,
2501 	mmPSOC_SVID1_BASE,
2502 	mmPSOC_SVID2_BASE,
2503 	mmPSOC_AVS0_BASE,
2504 	mmPSOC_AVS1_BASE,
2505 	mmPSOC_AVS2_BASE,
2506 	mmPSOC_PWM0_BASE,
2507 	mmPSOC_PWM1_BASE,
2508 	mmPSOC_MSTR_IF_RR_SHRD_HBW_BASE,
2509 };
2510 
2511 static const u32 gaudi2_pb_pmmu[] = {
2512 	mmPMMU_HBW_MMU_BASE,
2513 	mmPMMU_HBW_STLB_BASE,
2514 	mmPMMU_HBW_MSTR_IF_RR_SHRD_HBW_BASE,
2515 	mmPMMU_PIF_BASE,
2516 };
2517 
2518 static const u32 gaudi2_pb_psoc_pll[] = {
2519 	mmPSOC_MME_PLL_CTRL_BASE,
2520 	mmPSOC_CPU_PLL_CTRL_BASE,
2521 	mmPSOC_VID_PLL_CTRL_BASE
2522 };
2523 
2524 static const u32 gaudi2_pb_pmmu_pll[] = {
2525 	mmPMMU_MME_PLL_CTRL_BASE,
2526 	mmPMMU_VID_PLL_CTRL_BASE
2527 };
2528 
2529 static const u32 gaudi2_pb_xbar_pll[] = {
2530 	mmDCORE0_XBAR_DMA_PLL_CTRL_BASE,
2531 	mmDCORE0_XBAR_MMU_PLL_CTRL_BASE,
2532 	mmDCORE0_XBAR_IF_PLL_CTRL_BASE,
2533 	mmDCORE0_XBAR_MESH_PLL_CTRL_BASE,
2534 	mmDCORE1_XBAR_DMA_PLL_CTRL_BASE,
2535 	mmDCORE1_XBAR_MMU_PLL_CTRL_BASE,
2536 	mmDCORE1_XBAR_IF_PLL_CTRL_BASE,
2537 	mmDCORE1_XBAR_MESH_PLL_CTRL_BASE,
2538 	mmDCORE1_XBAR_HBM_PLL_CTRL_BASE,
2539 	mmDCORE2_XBAR_DMA_PLL_CTRL_BASE,
2540 	mmDCORE2_XBAR_MMU_PLL_CTRL_BASE,
2541 	mmDCORE2_XBAR_IF_PLL_CTRL_BASE,
2542 	mmDCORE2_XBAR_BANK_PLL_CTRL_BASE,
2543 	mmDCORE2_XBAR_HBM_PLL_CTRL_BASE,
2544 	mmDCORE3_XBAR_DMA_PLL_CTRL_BASE,
2545 	mmDCORE3_XBAR_MMU_PLL_CTRL_BASE,
2546 	mmDCORE3_XBAR_IF_PLL_CTRL_BASE,
2547 	mmDCORE3_XBAR_BANK_PLL_CTRL_BASE
2548 };
2549 
2550 static const u32 gaudi2_pb_xft_pll[] = {
2551 	mmDCORE0_HBM_PLL_CTRL_BASE,
2552 	mmDCORE0_TPC_PLL_CTRL_BASE,
2553 	mmDCORE0_PCI_PLL_CTRL_BASE,
2554 	mmDCORE1_HBM_PLL_CTRL_BASE,
2555 	mmDCORE1_TPC_PLL_CTRL_BASE,
2556 	mmDCORE1_NIC_PLL_CTRL_BASE,
2557 	mmDCORE2_HBM_PLL_CTRL_BASE,
2558 	mmDCORE2_TPC_PLL_CTRL_BASE,
2559 	mmDCORE3_HBM_PLL_CTRL_BASE,
2560 	mmDCORE3_TPC_PLL_CTRL_BASE,
2561 	mmDCORE3_NIC_PLL_CTRL_BASE,
2562 };
2563 
2564 static const u32 gaudi2_pb_pcie[] = {
2565 	mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2566 	mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2567 	mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE,
2568 	mmPCIE_WRAP_BASE,
2569 };
2570 
2571 static const u32 gaudi2_pb_pcie_unsecured_regs[] = {
2572 	mmPCIE_WRAP_SPECIAL_GLBL_SPARE_0,
2573 };
2574 
2575 static const u32 gaudi2_pb_thermal_sensor0[] = {
2576 	mmDCORE0_XFT_BASE,
2577 	mmDCORE0_TSTDVS_BASE,
2578 };
2579 
2580 static const u32 gaudi2_pb_hbm[] = {
2581 	mmHBM0_MC0_BASE,
2582 	mmHBM0_MC1_BASE,
2583 };
2584 
2585 static const u32 gaudi2_pb_mme_qm_arc_acp_eng[] = {
2586 	mmDCORE0_MME_QM_ARC_ACP_ENG_BASE,
2587 };
2588 
2589 static const struct range gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs[] = {
2590 	{mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_PI_REG_0, mmDCORE0_MME_QM_ARC_ACP_ENG_ACP_DBG_REG},
2591 };
2592 
2593 struct gaudi2_tpc_pb_data {
2594 	struct hl_block_glbl_sec *glbl_sec;
2595 	u32 block_array_size;
2596 };
2597 
2598 static void gaudi2_config_tpcs_glbl_sec(struct hl_device *hdev, int dcore, int inst, u32 offset,
2599 						struct iterate_module_ctx *ctx)
2600 {
2601 	struct gaudi2_tpc_pb_data *pb_data = ctx->data;
2602 
2603 	hl_config_glbl_sec(hdev, gaudi2_pb_dcr0_tpc0, pb_data->glbl_sec,
2604 					offset, pb_data->block_array_size);
2605 }
2606 
2607 static int gaudi2_init_pb_tpc(struct hl_device *hdev)
2608 {
2609 	u32 stride, kernel_tensor_stride, qm_tensor_stride, block_array_size;
2610 	struct gaudi2_tpc_pb_data tpc_pb_data;
2611 	struct hl_block_glbl_sec *glbl_sec;
2612 	struct iterate_module_ctx tpc_iter;
2613 	int i;
2614 
2615 	block_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
2616 
2617 	glbl_sec = kcalloc(block_array_size, sizeof(struct hl_block_glbl_sec), GFP_KERNEL);
2618 	if (!glbl_sec)
2619 		return -ENOMEM;
2620 
2621 	kernel_tensor_stride = mmDCORE0_TPC0_CFG_KERNEL_TENSOR_1_BASE -
2622 				mmDCORE0_TPC0_CFG_KERNEL_TENSOR_0_BASE;
2623 	qm_tensor_stride = mmDCORE0_TPC0_CFG_QM_TENSOR_1_BASE - mmDCORE0_TPC0_CFG_QM_TENSOR_0_BASE;
2624 
2625 	hl_secure_block(hdev, glbl_sec, block_array_size);
2626 	hl_unsecure_registers(hdev, gaudi2_pb_dcr0_tpc0_unsecured_regs,
2627 			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_unsecured_regs),
2628 			0, gaudi2_pb_dcr0_tpc0, glbl_sec,
2629 			block_array_size);
2630 
2631 	/* Unsecure all TPC kernel tensors */
2632 	for (i = 0 ; i < TPC_NUM_OF_KERNEL_TENSORS ; i++)
2633 		hl_unsecure_registers(hdev,
2634 			gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs,
2635 			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_ktensor_unsecured_regs),
2636 			i * kernel_tensor_stride, gaudi2_pb_dcr0_tpc0,
2637 			glbl_sec, block_array_size);
2638 
2639 	/* Unsecure all TPC QM tensors */
2640 	for (i = 0 ; i < TPC_NUM_OF_QM_TENSORS ; i++)
2641 		hl_unsecure_registers(hdev,
2642 			gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs,
2643 			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_qtensor_unsecured_regs),
2644 			i * qm_tensor_stride,
2645 			gaudi2_pb_dcr0_tpc0, glbl_sec, block_array_size);
2646 
2647 	/* unsecure all 32 TPC QM SRF regs */
2648 	stride = mmDCORE0_TPC0_CFG_QM_SRF_1 - mmDCORE0_TPC0_CFG_QM_SRF_0;
2649 	for (i = 0 ; i < 32 ; i++)
2650 		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_QM_SRF_0,
2651 				i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2652 				block_array_size);
2653 
2654 	/* unsecure the 4 TPC LOCK VALUE regs */
2655 	stride = mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_1 - mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0;
2656 	for (i = 0 ; i < 4 ; i++)
2657 		hl_unsecure_register(hdev, mmDCORE0_TPC0_CFG_TPC_LOCK_VALUE_0,
2658 				i * stride, gaudi2_pb_dcr0_tpc0, glbl_sec,
2659 				block_array_size);
2660 
2661 	/* prepare data for TPC iterator */
2662 	tpc_pb_data.glbl_sec = glbl_sec;
2663 	tpc_pb_data.block_array_size = block_array_size;
2664 	tpc_iter.fn = &gaudi2_config_tpcs_glbl_sec;
2665 	tpc_iter.data = &tpc_pb_data;
2666 	gaudi2_iterate_tpcs(hdev, &tpc_iter);
2667 
2668 	kfree(glbl_sec);
2669 
2670 	return 0;
2671 }
2672 
2673 struct gaudi2_tpc_arc_pb_data {
2674 	u32 unsecured_regs_arr_size;
2675 	u32 arc_regs_arr_size;
2676 };
2677 
2678 static void gaudi2_config_tpcs_pb_ranges(struct hl_device *hdev, int dcore, int inst, u32 offset,
2679 						struct iterate_module_ctx *ctx)
2680 {
2681 	struct gaudi2_tpc_arc_pb_data *pb_data = ctx->data;
2682 
2683 	ctx->rc = hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 1,
2684 					offset, gaudi2_pb_dcr0_tpc0_arc,
2685 					pb_data->arc_regs_arr_size,
2686 					gaudi2_pb_dcr0_tpc0_arc_unsecured_regs,
2687 					pb_data->unsecured_regs_arr_size);
2688 }
2689 
2690 static int gaudi2_init_pb_tpc_arc(struct hl_device *hdev)
2691 {
2692 	struct gaudi2_tpc_arc_pb_data tpc_arc_pb_data;
2693 	struct iterate_module_ctx tpc_iter;
2694 
2695 	tpc_arc_pb_data.arc_regs_arr_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
2696 	tpc_arc_pb_data.unsecured_regs_arr_size =
2697 			ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc_unsecured_regs);
2698 
2699 	tpc_iter.fn = &gaudi2_config_tpcs_pb_ranges;
2700 	tpc_iter.data = &tpc_arc_pb_data;
2701 	gaudi2_iterate_tpcs(hdev, &tpc_iter);
2702 
2703 	return tpc_iter.rc;
2704 }
2705 
2706 static int gaudi2_init_pb_sm_objs(struct hl_device *hdev)
2707 {
2708 	int i, j, glbl_sec_array_len = gaudi2_pb_dcr0_sm_objs.glbl_sec_length;
2709 	u32 sec_entry, *sec_array, array_base, first_sob, first_mon;
2710 
2711 	array_base = gaudi2_pb_dcr0_sm_objs.mm_block_base_addr +
2712 				gaudi2_pb_dcr0_sm_objs.glbl_sec_offset;
2713 
2714 	sec_array = kcalloc(glbl_sec_array_len, sizeof(u32), GFP_KERNEL);
2715 	if (!sec_array)
2716 		return -ENOMEM;
2717 
2718 	first_sob = GAUDI2_RESERVED_SOB_NUMBER;
2719 	first_mon = GAUDI2_RESERVED_MON_NUMBER;
2720 
2721 	/* 8192 SOB_OBJs skipping first GAUDI2_MAX_PENDING_CS of them */
2722 	for (j = i = first_sob ; i < DCORE_NUM_OF_SOB ; i++, j++)
2723 		UNSET_GLBL_SEC_BIT(sec_array, j);
2724 
2725 	/* 2048 MON_PAY ADDR_L skipping first GAUDI2_MAX_PENDING_CS of them */
2726 	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2727 		UNSET_GLBL_SEC_BIT(sec_array, j);
2728 
2729 	/* 2048 MON_PAY ADDR_H skipping first GAUDI2_MAX_PENDING_CS of them */
2730 	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2731 		UNSET_GLBL_SEC_BIT(sec_array, j);
2732 
2733 	/* 2048 MON_PAY DATA skipping first GAUDI2_MAX_PENDING_CS of them */
2734 	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2735 		UNSET_GLBL_SEC_BIT(sec_array, j);
2736 
2737 	/* 2048 MON_ARM skipping first GAUDI2_MAX_PENDING_CS of them */
2738 	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2739 		UNSET_GLBL_SEC_BIT(sec_array, j);
2740 
2741 	/* 2048 MON_CONFIG skipping first GAUDI2_MAX_PENDING_CS of them */
2742 	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2743 		UNSET_GLBL_SEC_BIT(sec_array, j);
2744 
2745 	/* 2048 MON_STATUS skipping first GAUDI2_MAX_PENDING_CS of them */
2746 	for (i = first_mon, j += i ; i < DCORE_NUM_OF_MONITORS ; i++, j++)
2747 		UNSET_GLBL_SEC_BIT(sec_array, j);
2748 
2749 	/* Unsecure selected Dcore0 registers */
2750 	for (i = 0 ; i < glbl_sec_array_len ; i++) {
2751 		sec_entry = array_base + i * sizeof(u32);
2752 		WREG32(sec_entry, sec_array[i]);
2753 	}
2754 
2755 	/* Unsecure Dcore1 - Dcore3 registers */
2756 	memset(sec_array, -1, glbl_sec_array_len * sizeof(u32));
2757 
2758 	for (i = 1 ; i < NUM_OF_DCORES ; i++) {
2759 		for (j = 0 ; j < glbl_sec_array_len ; j++) {
2760 			sec_entry = DCORE_OFFSET * i + array_base + j * sizeof(u32);
2761 			WREG32(sec_entry, sec_array[j]);
2762 		}
2763 	}
2764 
2765 	kfree(sec_array);
2766 
2767 	return 0;
2768 }
2769 
2770 static void gaudi2_write_lbw_range_register(struct hl_device *hdev, u64 base, void *data)
2771 {
2772 	u32 reg_min_offset, reg_max_offset, write_min, write_max;
2773 	struct rr_config *rr_cfg = (struct rr_config *) data;
2774 
2775 	switch (rr_cfg->type) {
2776 	case RR_TYPE_SHORT:
2777 		reg_min_offset = RR_LBW_SEC_RANGE_MIN_SHORT_0_OFFSET;
2778 		reg_max_offset = RR_LBW_SEC_RANGE_MAX_SHORT_0_OFFSET;
2779 		break;
2780 
2781 	case RR_TYPE_LONG:
2782 		reg_min_offset = RR_LBW_SEC_RANGE_MIN_0_OFFSET;
2783 		reg_max_offset = RR_LBW_SEC_RANGE_MAX_0_OFFSET;
2784 		break;
2785 
2786 	case RR_TYPE_SHORT_PRIV:
2787 		reg_min_offset = RR_LBW_PRIV_RANGE_MIN_SHORT_0_OFFSET;
2788 		reg_max_offset = RR_LBW_PRIV_RANGE_MAX_SHORT_0_OFFSET;
2789 		break;
2790 
2791 	case RR_TYPE_LONG_PRIV:
2792 		reg_min_offset = RR_LBW_PRIV_RANGE_MIN_0_OFFSET;
2793 		reg_max_offset = RR_LBW_PRIV_RANGE_MAX_0_OFFSET;
2794 		break;
2795 
2796 	default:
2797 		dev_err(hdev->dev, "Invalid LBW RR type %u\n", rr_cfg->type);
2798 		return;
2799 	}
2800 
2801 	reg_min_offset += rr_cfg->index * sizeof(u32);
2802 	reg_max_offset += rr_cfg->index * sizeof(u32);
2803 
2804 	if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
2805 		write_min = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->min));
2806 		write_max = FIELD_GET(RR_LBW_SHORT_MASK, lower_32_bits(rr_cfg->max));
2807 
2808 	} else {
2809 		write_min = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->min));
2810 		write_max = FIELD_GET(RR_LBW_LONG_MASK, lower_32_bits(rr_cfg->max));
2811 	}
2812 
2813 	/* Configure LBW RR:
2814 	 * Both RR types start blocking from base address 0x1000007FF8000000
2815 	 * SHORT RRs address bits [26:12]
2816 	 * LONG RRs address bits [26:0]
2817 	 */
2818 	WREG32(base + reg_min_offset, write_min);
2819 	WREG32(base + reg_max_offset, write_max);
2820 }
2821 
2822 void gaudi2_write_rr_to_all_lbw_rtrs(struct hl_device *hdev, u8 rr_type, u32 rr_index, u64 min_val,
2823 					u64 max_val)
2824 {
2825 	struct dup_block_ctx block_ctx;
2826 	struct rr_config rr_cfg;
2827 
2828 	if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
2829 								rr_index >= NUM_SHORT_LBW_RR) {
2830 
2831 		dev_err(hdev->dev, "invalid short LBW %s range register index: %u",
2832 			rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
2833 		return;
2834 	}
2835 
2836 	if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
2837 								rr_index >= NUM_LONG_LBW_RR) {
2838 
2839 		dev_err(hdev->dev, "invalid long LBW %s range register index: %u",
2840 			rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
2841 		return;
2842 	}
2843 
2844 	rr_cfg.type = rr_type;
2845 	rr_cfg.index = rr_index;
2846 	rr_cfg.min = min_val;
2847 	rr_cfg.max = max_val;
2848 
2849 	block_ctx.instance_cfg_fn = &gaudi2_write_lbw_range_register;
2850 	block_ctx.data = &rr_cfg;
2851 
2852 	/* SFT */
2853 	block_ctx.base = mmSFT0_LBW_RTR_IF_MSTR_IF_RR_SHRD_LBW_BASE;
2854 	block_ctx.blocks = NUM_OF_SFT;
2855 	block_ctx.block_off = SFT_OFFSET;
2856 	block_ctx.instances = SFT_NUM_OF_LBW_RTR;
2857 	block_ctx.instance_off = SFT_LBW_RTR_OFFSET;
2858 	gaudi2_init_blocks(hdev, &block_ctx);
2859 
2860 	/* SIF */
2861 	block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_LBW_BASE;
2862 	block_ctx.blocks = NUM_OF_DCORES;
2863 	block_ctx.block_off = DCORE_OFFSET;
2864 	block_ctx.instances = NUM_OF_RTR_PER_DCORE;
2865 	block_ctx.instance_off = DCORE_RTR_OFFSET;
2866 	gaudi2_init_blocks(hdev, &block_ctx);
2867 
2868 	block_ctx.blocks = 1;
2869 	block_ctx.block_off = 0;
2870 	block_ctx.instances = 1;
2871 	block_ctx.instance_off = 0;
2872 
2873 	/* PCIE ELBI */
2874 	block_ctx.base = mmPCIE_ELBI_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2875 	gaudi2_init_blocks(hdev, &block_ctx);
2876 
2877 	/* PCIE MSTR */
2878 	block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2879 	gaudi2_init_blocks(hdev, &block_ctx);
2880 
2881 	/* PCIE LBW */
2882 	block_ctx.base = mmPCIE_LBW_RR_MSTR_IF_RR_SHRD_LBW_BASE;
2883 	gaudi2_init_blocks(hdev, &block_ctx);
2884 }
2885 
2886 static void gaudi2_init_lbw_range_registers_secure(struct hl_device *hdev)
2887 {
2888 	int i;
2889 
2890 	/* Up to 14 14bit-address regs.
2891 	 *
2892 	 * - range 0: NIC0_CFG
2893 	 * - range 1: NIC1_CFG
2894 	 * - range 2: NIC2_CFG
2895 	 * - range 3: NIC3_CFG
2896 	 * - range 4: NIC4_CFG
2897 	 * - range 5: NIC5_CFG
2898 	 * - range 6: NIC6_CFG
2899 	 * - range 7: NIC7_CFG
2900 	 * - range 8: NIC8_CFG
2901 	 * - range 9: NIC9_CFG
2902 	 * - range 10: NIC10_CFG
2903 	 * - range 11: NIC11_CFG + *_DBG (not including TPC_DBG)
2904 	 *
2905 	 * If F/W security is not enabled:
2906 	 * - ranges 12,13: PSOC_CFG (excluding PSOC_TIMESTAMP)
2907 	 */
2908 	u64 lbw_range_min_short[] = {
2909 		mmNIC0_TX_AXUSER_BASE,
2910 		mmNIC1_TX_AXUSER_BASE,
2911 		mmNIC2_TX_AXUSER_BASE,
2912 		mmNIC3_TX_AXUSER_BASE,
2913 		mmNIC4_TX_AXUSER_BASE,
2914 		mmNIC5_TX_AXUSER_BASE,
2915 		mmNIC6_TX_AXUSER_BASE,
2916 		mmNIC7_TX_AXUSER_BASE,
2917 		mmNIC8_TX_AXUSER_BASE,
2918 		mmNIC9_TX_AXUSER_BASE,
2919 		mmNIC10_TX_AXUSER_BASE,
2920 		mmNIC11_TX_AXUSER_BASE,
2921 		mmPSOC_I2C_M0_BASE,
2922 		mmPSOC_EFUSE_BASE
2923 	};
2924 	u64 lbw_range_max_short[] = {
2925 		mmNIC0_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2926 		mmNIC1_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2927 		mmNIC2_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2928 		mmNIC3_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2929 		mmNIC4_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2930 		mmNIC5_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2931 		mmNIC6_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2932 		mmNIC7_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2933 		mmNIC8_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2934 		mmNIC9_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2935 		mmNIC10_MAC_CH3_MAC_PCS_BASE + HL_BLOCK_SIZE,
2936 		mmNIC11_DBG_FUNNEL_NCH_BASE + HL_BLOCK_SIZE,
2937 		mmPSOC_WDOG_BASE + HL_BLOCK_SIZE,
2938 		mmSVID2_AC_BASE + HL_BLOCK_SIZE
2939 	};
2940 
2941 	/* Up to 4 26bit-address regs.
2942 	 *
2943 	 * - range 0: TPC_DBG
2944 	 * - range 1: PCIE_DBI.MSIX_DOORBELL_OFF
2945 	 * - range 2/3: used in soft reset to block access to several blocks and are cleared here
2946 	 */
2947 	u64 lbw_range_min_long[] = {
2948 		mmDCORE0_TPC0_ROM_TABLE_BASE,
2949 		mmPCIE_DBI_MSIX_DOORBELL_OFF,
2950 		0x0,
2951 		0x0
2952 	};
2953 	u64 lbw_range_max_long[] = {
2954 		mmDCORE3_TPC5_EML_CS_BASE + HL_BLOCK_SIZE,
2955 		mmPCIE_DBI_MSIX_DOORBELL_OFF + 0x4,
2956 		0x0,
2957 		0x0
2958 	};
2959 
2960 	/* write short range registers to all lbw rtrs */
2961 	for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_short) ; i++) {
2962 		if ((lbw_range_min_short[i] == mmPSOC_I2C_M0_BASE ||
2963 				lbw_range_min_short[i] == mmPSOC_EFUSE_BASE) &&
2964 				hdev->asic_prop.fw_security_enabled)
2965 			continue;
2966 
2967 		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_SHORT, i,
2968 				lbw_range_min_short[i], lbw_range_max_short[i]);
2969 	}
2970 
2971 	/* write long range registers to all lbw rtrs */
2972 	for (i = 0 ; i < ARRAY_SIZE(lbw_range_min_long) ; i++) {
2973 		gaudi2_write_rr_to_all_lbw_rtrs(hdev, RR_TYPE_LONG, i,
2974 				lbw_range_min_long[i], lbw_range_max_long[i]);
2975 	}
2976 }
2977 
2978 static void gaudi2_init_lbw_range_registers(struct hl_device *hdev)
2979 {
2980 	gaudi2_init_lbw_range_registers_secure(hdev);
2981 }
2982 
2983 static void gaudi2_write_hbw_range_register(struct hl_device *hdev, u64 base, void *data)
2984 {
2985 	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
2986 	struct rr_config *rr_cfg = (struct rr_config *) data;
2987 	u64 val_min, val_max;
2988 
2989 	switch (rr_cfg->type) {
2990 	case RR_TYPE_SHORT:
2991 		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_LO_0_OFFSET;
2992 		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_SHORT_HI_0_OFFSET;
2993 		max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_LO_0_OFFSET;
2994 		max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_SHORT_HI_0_OFFSET;
2995 		break;
2996 
2997 	case RR_TYPE_LONG:
2998 		min_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_LO_0_OFFSET;
2999 		min_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MIN_HI_0_OFFSET;
3000 		max_lo_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_LO_0_OFFSET;
3001 		max_hi_reg_offset = RR_SHRD_HBW_SEC_RANGE_MAX_HI_0_OFFSET;
3002 		break;
3003 
3004 	case RR_TYPE_SHORT_PRIV:
3005 		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_LO_0_OFFSET;
3006 		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_SHORT_HI_0_OFFSET;
3007 		max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_LO_0_OFFSET;
3008 		max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_SHORT_HI_0_OFFSET;
3009 		break;
3010 
3011 	case RR_TYPE_LONG_PRIV:
3012 		min_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_LO_0_OFFSET;
3013 		min_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MIN_HI_0_OFFSET;
3014 		max_lo_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_LO_0_OFFSET;
3015 		max_hi_reg_offset = RR_SHRD_HBW_PRIV_RANGE_MAX_HI_0_OFFSET;
3016 		break;
3017 
3018 	default:
3019 		dev_err(hdev->dev, "Invalid HBW RR type %u\n", rr_cfg->type);
3020 		return;
3021 	}
3022 
3023 	min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3024 	min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3025 	max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3026 	max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3027 
3028 	if (rr_cfg->type == RR_TYPE_SHORT || rr_cfg->type == RR_TYPE_SHORT_PRIV) {
3029 		val_min = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->min) |
3030 				FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->min);
3031 		val_max = FIELD_GET(RR_HBW_SHORT_HI_MASK, rr_cfg->max) |
3032 				FIELD_GET(RR_HBW_SHORT_LO_MASK, rr_cfg->max);
3033 	} else {
3034 		val_min = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->min) |
3035 				FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->min);
3036 		val_max = FIELD_GET(RR_HBW_LONG_HI_MASK, rr_cfg->max) |
3037 				FIELD_GET(RR_HBW_LONG_LO_MASK, rr_cfg->max);
3038 	}
3039 
3040 	/* Configure HBW RR:
3041 	 * SHORT RRs (0x1000_<36bits>000) - HI: address bits [47:44], LO: address bits [43:12]
3042 	 * LONG  RRs (0x<52bits>000)      - HI: address bits [63:44], LO: address bits [43:12]
3043 	 */
3044 	WREG32(base + min_lo_reg_offset, lower_32_bits(val_min));
3045 	WREG32(base + min_hi_reg_offset, upper_32_bits(val_min));
3046 	WREG32(base + max_lo_reg_offset, lower_32_bits(val_max));
3047 	WREG32(base + max_hi_reg_offset, upper_32_bits(val_max));
3048 }
3049 
3050 static void gaudi2_write_hbw_rr_to_all_mstr_if(struct hl_device *hdev, u8 rr_type, u32 rr_index,
3051 						u64 min_val, u64 max_val)
3052 {
3053 	struct dup_block_ctx block_ctx;
3054 	struct rr_config rr_cfg;
3055 
3056 	if ((rr_type == RR_TYPE_SHORT || rr_type == RR_TYPE_SHORT_PRIV) &&
3057 								rr_index >= NUM_SHORT_HBW_RR) {
3058 
3059 		dev_err(hdev->dev, "invalid short HBW %s range register index: %u",
3060 			rr_type == RR_TYPE_SHORT ? "secure" : "privileged", rr_index);
3061 		return;
3062 	}
3063 
3064 	if ((rr_type == RR_TYPE_LONG || rr_type == RR_TYPE_LONG_PRIV) &&
3065 								rr_index >= NUM_LONG_HBW_RR) {
3066 
3067 		dev_err(hdev->dev, "invalid long HBW %s range register index: %u",
3068 			rr_type == RR_TYPE_LONG ? "secure" : "privileged", rr_index);
3069 		return;
3070 	}
3071 
3072 	rr_cfg.type = rr_type;
3073 	rr_cfg.index = rr_index;
3074 	rr_cfg.min = min_val;
3075 	rr_cfg.max = max_val;
3076 
3077 	block_ctx.instance_cfg_fn = &gaudi2_write_hbw_range_register;
3078 	block_ctx.data = &rr_cfg;
3079 
3080 	/* SFT */
3081 	block_ctx.base = mmSFT0_HBW_RTR_IF0_MSTR_IF_RR_SHRD_HBW_BASE;
3082 	block_ctx.blocks = NUM_OF_SFT;
3083 	block_ctx.block_off = SFT_OFFSET;
3084 	block_ctx.instances = SFT_NUM_OF_HBW_RTR;
3085 	block_ctx.instance_off = SFT_IF_RTR_OFFSET;
3086 	gaudi2_init_blocks(hdev, &block_ctx);
3087 
3088 	/* SIF */
3089 	block_ctx.base = mmDCORE0_RTR0_MSTR_IF_RR_SHRD_HBW_BASE;
3090 	block_ctx.blocks = NUM_OF_DCORES;
3091 	block_ctx.block_off = DCORE_OFFSET;
3092 	block_ctx.instances = NUM_OF_RTR_PER_DCORE;
3093 	block_ctx.instance_off = DCORE_RTR_OFFSET;
3094 	gaudi2_init_blocks(hdev, &block_ctx);
3095 
3096 	/* PCIE MSTR */
3097 	block_ctx.base = mmPCIE_MSTR_RR_MSTR_IF_RR_SHRD_HBW_BASE;
3098 	block_ctx.blocks = 1;
3099 	block_ctx.block_off = 0;
3100 	block_ctx.instances = 1;
3101 	block_ctx.instance_off = 0;
3102 	gaudi2_init_blocks(hdev, &block_ctx);
3103 }
3104 
3105 static void gaudi2_init_hbw_range_registers(struct hl_device *hdev)
3106 {
3107 	int i;
3108 
3109 	/* Up to 6 short RR (0x1000_<36bits>000) and 4 long RR (0x<52bits>000).
3110 	 *
3111 	 * - short range 0:
3112 	 *	SPI Flash, ARC0/1 ICCM/DCCM, Secure Boot ROM, PSOC_FW/Scratchpad/PCIE_FW SRAM
3113 	 */
3114 	u64 hbw_range_min_short[] = {
3115 		SPI_FLASH_BASE_ADDR
3116 	};
3117 	u64 hbw_range_max_short[] = {
3118 		PCIE_FW_SRAM_ADDR + PCIE_FW_SRAM_SIZE
3119 	};
3120 
3121 	for (i = 0 ; i < ARRAY_SIZE(hbw_range_min_short) ; i++) {
3122 		gaudi2_write_hbw_rr_to_all_mstr_if(hdev, RR_TYPE_SHORT, i, hbw_range_min_short[i],
3123 							hbw_range_max_short[i]);
3124 	}
3125 }
3126 
3127 static void gaudi2_write_mmu_range_register(struct hl_device *hdev, u64 base,
3128 						struct rr_config *rr_cfg)
3129 {
3130 	u32 min_lo_reg_offset, min_hi_reg_offset, max_lo_reg_offset, max_hi_reg_offset;
3131 
3132 	switch (rr_cfg->type) {
3133 	case RR_TYPE_LONG:
3134 		min_lo_reg_offset = MMU_RR_SEC_MIN_31_0_0_OFFSET;
3135 		min_hi_reg_offset = MMU_RR_SEC_MIN_63_32_0_OFFSET;
3136 		max_lo_reg_offset = MMU_RR_SEC_MAX_31_0_0_OFFSET;
3137 		max_hi_reg_offset = MMU_RR_SEC_MAX_63_32_0_OFFSET;
3138 		break;
3139 
3140 	case RR_TYPE_LONG_PRIV:
3141 		min_lo_reg_offset = MMU_RR_PRIV_MIN_31_0_0_OFFSET;
3142 		min_hi_reg_offset = MMU_RR_PRIV_MIN_63_32_0_OFFSET;
3143 		max_lo_reg_offset = MMU_RR_PRIV_MAX_31_0_0_OFFSET;
3144 		max_hi_reg_offset = MMU_RR_PRIV_MAX_63_32_0_OFFSET;
3145 		break;
3146 
3147 	default:
3148 		dev_err(hdev->dev, "Invalid MMU RR type %u\n", rr_cfg->type);
3149 		return;
3150 	}
3151 
3152 	min_lo_reg_offset += rr_cfg->index * sizeof(u32);
3153 	min_hi_reg_offset += rr_cfg->index * sizeof(u32);
3154 	max_lo_reg_offset += rr_cfg->index * sizeof(u32);
3155 	max_hi_reg_offset += rr_cfg->index * sizeof(u32);
3156 
3157 	/* Configure MMU RR (address bits [63:0]) */
3158 	WREG32(base + min_lo_reg_offset, lower_32_bits(rr_cfg->min));
3159 	WREG32(base + min_hi_reg_offset, upper_32_bits(rr_cfg->min));
3160 	WREG32(base + max_lo_reg_offset, lower_32_bits(rr_cfg->max));
3161 	WREG32(base + max_hi_reg_offset, upper_32_bits(rr_cfg->max));
3162 }
3163 
3164 static void gaudi2_init_mmu_range_registers(struct hl_device *hdev)
3165 {
3166 	u32 dcore_id, hmmu_id, hmmu_base;
3167 	struct rr_config rr_cfg;
3168 
3169 	/* Up to 8 ranges [63:0].
3170 	 *
3171 	 * - range 0: Reserved HBM area for F/W and driver
3172 	 */
3173 
3174 	/* The RRs are located after the HMMU so need to use the scrambled addresses */
3175 	rr_cfg.min = hdev->asic_funcs->scramble_addr(hdev, DRAM_PHYS_BASE);
3176 	rr_cfg.max = hdev->asic_funcs->scramble_addr(hdev, hdev->asic_prop.dram_user_base_address);
3177 	rr_cfg.index = 0;
3178 	rr_cfg.type = RR_TYPE_LONG;
3179 
3180 	for (dcore_id = 0 ; dcore_id < NUM_OF_DCORES ; dcore_id++) {
3181 		for (hmmu_id = 0 ; hmmu_id < NUM_OF_HMMU_PER_DCORE; hmmu_id++) {
3182 			if (!gaudi2_is_hmmu_enabled(hdev, dcore_id, hmmu_id))
3183 				continue;
3184 
3185 			hmmu_base = mmDCORE0_HMMU0_MMU_BASE + dcore_id * DCORE_OFFSET +
3186 					hmmu_id * DCORE_HMMU_OFFSET;
3187 
3188 			gaudi2_write_mmu_range_register(hdev, hmmu_base, &rr_cfg);
3189 		}
3190 	}
3191 }
3192 
3193 /**
3194  * gaudi2_init_range_registers -
3195  * Initialize range registers of all initiators
3196  *
3197  * @hdev: pointer to hl_device structure
3198  */
3199 static void gaudi2_init_range_registers(struct hl_device *hdev)
3200 {
3201 	gaudi2_init_lbw_range_registers(hdev);
3202 	gaudi2_init_hbw_range_registers(hdev);
3203 	gaudi2_init_mmu_range_registers(hdev);
3204 }
3205 
3206 /**
3207  * gaudi2_init_protection_bits -
3208  * Initialize protection bits of specific registers
3209  *
3210  * @hdev: pointer to hl_device structure
3211  *
3212  * All protection bits are 1 by default, means not protected. Need to set to 0
3213  * each bit that belongs to a protected register.
3214  *
3215  */
3216 static int gaudi2_init_protection_bits(struct hl_device *hdev)
3217 {
3218 	struct asic_fixed_properties *prop = &hdev->asic_prop;
3219 	u32 instance_offset;
3220 	int rc = 0;
3221 	u8 i;
3222 
3223 	/* SFT */
3224 	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3225 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3226 			gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0),
3227 			NULL, HL_PB_NA);
3228 
3229 	/* HIF */
3230 	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3231 	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3232 			NUM_OF_HIF_PER_DCORE, instance_offset,
3233 			gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3234 			NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3235 
3236 	/* RTR */
3237 	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3238 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3239 			gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0),
3240 			NULL, HL_PB_NA);
3241 
3242 	/* HMMU */
3243 	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3244 			NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3245 			gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3246 			NULL, HL_PB_NA, prop->hmmu_hif_enabled_mask);
3247 
3248 	/* CPU.
3249 	 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3250 	 * by privileged RR.
3251 	 */
3252 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3253 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3254 			gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if),
3255 			NULL, HL_PB_NA);
3256 
3257 	if (!hdev->asic_prop.fw_security_enabled)
3258 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3259 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3260 				gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu),
3261 				NULL, HL_PB_NA);
3262 
3263 	/* KDMA */
3264 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3265 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3266 			gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma),
3267 			NULL, HL_PB_NA);
3268 
3269 	/* PDMA */
3270 	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3271 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3272 			gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0),
3273 			gaudi2_pb_pdma0_unsecured_regs,
3274 			ARRAY_SIZE(gaudi2_pb_pdma0_unsecured_regs));
3275 
3276 	/* ARC PDMA */
3277 	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA, 2,
3278 			instance_offset, gaudi2_pb_pdma0_arc,
3279 			ARRAY_SIZE(gaudi2_pb_pdma0_arc),
3280 			gaudi2_pb_pdma0_arc_unsecured_regs,
3281 			ARRAY_SIZE(gaudi2_pb_pdma0_arc_unsecured_regs));
3282 
3283 	/* EDMA */
3284 	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3285 	rc |= hl_init_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3286 			instance_offset, gaudi2_pb_dcr0_edma0,
3287 			ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3288 			gaudi2_pb_dcr0_edma0_unsecured_regs,
3289 			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_unsecured_regs),
3290 			prop->edma_enabled_mask);
3291 
3292 	/* ARC EDMA */
3293 	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3294 			instance_offset, gaudi2_pb_dcr0_edma0_arc,
3295 			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3296 			gaudi2_pb_dcr0_edma0_arc_unsecured_regs,
3297 			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc_unsecured_regs),
3298 			prop->edma_enabled_mask);
3299 
3300 	/* MME */
3301 	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3302 
3303 	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3304 		/* MME SBTE */
3305 		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3306 				instance_offset, gaudi2_pb_dcr0_mme_sbte,
3307 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte), NULL,
3308 				HL_PB_NA);
3309 
3310 		/* MME */
3311 		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3312 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3313 				gaudi2_pb_dcr0_mme_eng,
3314 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng),
3315 				gaudi2_pb_dcr0_mme_eng_unsecured_regs,
3316 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng_unsecured_regs));
3317 	}
3318 
3319 	/*
3320 	 * we have special iteration for case in which we would like to
3321 	 * configure stubbed MME's ARC/QMAN
3322 	 */
3323 	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3324 		/* MME QM */
3325 		rc |= hl_init_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3326 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3327 				gaudi2_pb_dcr0_mme_qm,
3328 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm),
3329 				gaudi2_pb_dcr0_mme_qm_unsecured_regs,
3330 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm_unsecured_regs));
3331 
3332 		/* ARC MME */
3333 		rc |= hl_init_pb_ranges_single_dcore(hdev, (DCORE_OFFSET * i),
3334 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3335 			gaudi2_pb_dcr0_mme_arc,
3336 			ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc),
3337 			gaudi2_pb_dcr0_mme_arc_unsecured_regs,
3338 			ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc_unsecured_regs));
3339 	}
3340 
3341 	/* MME QM ARC ACP ENG */
3342 	rc |= hl_init_pb_ranges_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3343 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3344 			gaudi2_pb_mme_qm_arc_acp_eng,
3345 			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3346 			gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs,
3347 			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng_unsecured_regs),
3348 			(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3349 
3350 	/* TPC */
3351 	rc |= gaudi2_init_pb_tpc(hdev);
3352 	rc |= gaudi2_init_pb_tpc_arc(hdev);
3353 
3354 	/* SRAM */
3355 	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3356 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3357 			gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0),
3358 			NULL, HL_PB_NA);
3359 
3360 	/* Sync Manager MSTR IF */
3361 	rc |= hl_init_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3362 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3363 			gaudi2_pb_dcr0_sm_mstr_if,
3364 			ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if),
3365 			NULL, HL_PB_NA);
3366 
3367 	/* Sync Manager GLBL */
3368 
3369 	/* Secure Dcore0 CQ0 registers */
3370 	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3371 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3372 			gaudi2_pb_dcr0_sm_glbl,
3373 			ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl),
3374 			gaudi2_pb_dcr0_sm_glbl_unsecured_regs,
3375 			ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl_unsecured_regs));
3376 
3377 	/* Unsecure all other CQ registers */
3378 	rc |= hl_init_pb_ranges(hdev, NUM_OF_DCORES - 1, DCORE_OFFSET,
3379 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3380 			gaudi2_pb_dcr1_sm_glbl,
3381 			ARRAY_SIZE(gaudi2_pb_dcr1_sm_glbl),
3382 			gaudi2_pb_dcr_x_sm_glbl_unsecured_regs,
3383 			ARRAY_SIZE(gaudi2_pb_dcr_x_sm_glbl_unsecured_regs));
3384 
3385 	/* PSOC.
3386 	 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3387 	 * protected by privileged RR.
3388 	 */
3389 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3390 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3391 			gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf),
3392 			NULL, HL_PB_NA);
3393 
3394 	if (!hdev->asic_prop.fw_security_enabled)
3395 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3396 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3397 				gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc),
3398 				NULL, HL_PB_NA);
3399 
3400 	/* PMMU */
3401 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3402 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3403 			gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu),
3404 			NULL, HL_PB_NA);
3405 
3406 	/* PLL.
3407 	 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3408 	 * privileged RR.
3409 	 */
3410 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3411 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3412 			gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll),
3413 			NULL, HL_PB_NA);
3414 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3415 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3416 			gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll),
3417 			NULL, HL_PB_NA);
3418 
3419 	if (!hdev->asic_prop.fw_security_enabled) {
3420 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3421 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3422 				gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll),
3423 				NULL, HL_PB_NA);
3424 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3425 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3426 				gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll),
3427 				NULL, HL_PB_NA);
3428 	}
3429 
3430 	/* PCIE */
3431 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA,
3432 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3433 			gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie),
3434 			gaudi2_pb_pcie_unsecured_regs,
3435 			ARRAY_SIZE(gaudi2_pb_pcie_unsecured_regs));
3436 
3437 	/* Thermal Sensor.
3438 	 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3439 	 */
3440 	if (!hdev->asic_prop.fw_security_enabled) {
3441 		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3442 		rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3443 				gaudi2_pb_thermal_sensor0,
3444 				ARRAY_SIZE(gaudi2_pb_thermal_sensor0), NULL, HL_PB_NA);
3445 	}
3446 
3447 	/* Scheduler ARCs */
3448 	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3449 	rc |= hl_init_pb_ranges(hdev, HL_PB_SHARED, HL_PB_NA,
3450 			NUM_OF_ARC_FARMS_ARC,
3451 			instance_offset, gaudi2_pb_arc_sched,
3452 			ARRAY_SIZE(gaudi2_pb_arc_sched),
3453 			gaudi2_pb_arc_sched_unsecured_regs,
3454 			ARRAY_SIZE(gaudi2_pb_arc_sched_unsecured_regs));
3455 
3456 	/* XBAR MIDs */
3457 	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3458 	rc |= hl_init_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3459 			instance_offset, gaudi2_pb_xbar_mid,
3460 			ARRAY_SIZE(gaudi2_pb_xbar_mid),
3461 			gaudi2_pb_xbar_mid_unsecured_regs,
3462 			ARRAY_SIZE(gaudi2_pb_xbar_mid_unsecured_regs));
3463 
3464 	/* XBAR EDGEs */
3465 	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3466 	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3467 			instance_offset, gaudi2_pb_xbar_edge,
3468 			ARRAY_SIZE(gaudi2_pb_xbar_edge),
3469 			gaudi2_pb_xbar_edge_unsecured_regs,
3470 			ARRAY_SIZE(gaudi2_pb_xbar_edge_unsecured_regs),
3471 			prop->xbar_edge_enabled_mask);
3472 
3473 	/* NIC */
3474 	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3475 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3476 			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0),
3477 			NULL, HL_PB_NA, hdev->nic_ports_mask);
3478 
3479 	/* NIC QM and QPC */
3480 	rc |= hl_init_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET,
3481 			NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3482 			gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3483 			gaudi2_pb_nic0_qm_qpc_unsecured_regs,
3484 			ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc_unsecured_regs),
3485 			hdev->nic_ports_mask);
3486 
3487 	/* NIC QM ARC */
3488 	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3489 			NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3490 			gaudi2_pb_nic0_qm_arc_aux0,
3491 			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0),
3492 			gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs,
3493 			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0_unsecured_regs),
3494 			hdev->nic_ports_mask);
3495 
3496 	/* NIC UMR */
3497 	rc |= hl_init_pb_ranges_with_mask(hdev, NIC_NUMBER_OF_MACROS,
3498 			NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO, NIC_QM_OFFSET,
3499 			gaudi2_pb_nic0_umr,
3500 			ARRAY_SIZE(gaudi2_pb_nic0_umr),
3501 			gaudi2_pb_nic0_umr_unsecured_regs,
3502 			ARRAY_SIZE(gaudi2_pb_nic0_umr_unsecured_regs),
3503 			hdev->nic_ports_mask);
3504 
3505 	/* Rotators */
3506 	instance_offset = mmROT1_BASE - mmROT0_BASE;
3507 	rc |= hl_init_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT,
3508 			instance_offset, gaudi2_pb_rot0,
3509 			ARRAY_SIZE(gaudi2_pb_rot0),
3510 			gaudi2_pb_rot0_unsecured_regs,
3511 			ARRAY_SIZE(gaudi2_pb_rot0_unsecured_regs),
3512 			(BIT(NUM_OF_ROT) - 1));
3513 
3514 	/* Rotators ARCS */
3515 	rc |= hl_init_pb_ranges_with_mask(hdev, HL_PB_SHARED,
3516 			HL_PB_NA, NUM_OF_ROT, instance_offset,
3517 			gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc),
3518 			gaudi2_pb_rot0_arc_unsecured_regs,
3519 			ARRAY_SIZE(gaudi2_pb_rot0_arc_unsecured_regs),
3520 			(BIT(NUM_OF_ROT) - 1));
3521 
3522 	rc |= gaudi2_init_pb_sm_objs(hdev);
3523 
3524 	return rc;
3525 }
3526 
3527 /**
3528  * gaudi2_init_security - Initialize security model
3529  *
3530  * @hdev: pointer to hl_device structure
3531  *
3532  * Initialize the security model of the device
3533  * That includes range registers and protection bit per register.
3534  */
3535 int gaudi2_init_security(struct hl_device *hdev)
3536 {
3537 	int rc;
3538 
3539 	rc = gaudi2_init_protection_bits(hdev);
3540 	if (rc)
3541 		return rc;
3542 
3543 	gaudi2_init_range_registers(hdev);
3544 
3545 	return 0;
3546 }
3547 
3548 struct gaudi2_ack_pb_tpc_data {
3549 	u32 tpc_regs_array_size;
3550 	u32 arc_tpc_regs_array_size;
3551 };
3552 
3553 static void gaudi2_ack_pb_tpc_config(struct hl_device *hdev, int dcore, int inst, u32 offset,
3554 					struct iterate_module_ctx *ctx)
3555 {
3556 	struct gaudi2_ack_pb_tpc_data *pb_data = ctx->data;
3557 
3558 	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3559 				gaudi2_pb_dcr0_tpc0, pb_data->tpc_regs_array_size);
3560 
3561 	hl_ack_pb_single_dcore(hdev, offset, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3562 				gaudi2_pb_dcr0_tpc0_arc, pb_data->arc_tpc_regs_array_size);
3563 }
3564 
3565 static void gaudi2_ack_pb_tpc(struct hl_device *hdev)
3566 {
3567 	struct iterate_module_ctx tpc_iter = {
3568 		.fn = &gaudi2_ack_pb_tpc_config,
3569 	};
3570 	struct gaudi2_ack_pb_tpc_data data;
3571 
3572 	data.tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0);
3573 	data.arc_tpc_regs_array_size = ARRAY_SIZE(gaudi2_pb_dcr0_tpc0_arc);
3574 	tpc_iter.data = &data;
3575 
3576 	gaudi2_iterate_tpcs(hdev, &tpc_iter);
3577 }
3578 
3579 /**
3580  * gaudi2_ack_protection_bits_errors - scan all blocks having protection bits
3581  * and for every protection error found, display the appropriate error message
3582  * and clear the error.
3583  *
3584  * @hdev: pointer to hl_device structure
3585  *
3586  * All protection bits are 1 by default, means not protected. Need to set to 0
3587  * each bit that belongs to a protected register.
3588  *
3589  */
3590 void gaudi2_ack_protection_bits_errors(struct hl_device *hdev)
3591 {
3592 	struct asic_fixed_properties *prop = &hdev->asic_prop;
3593 	u32 instance_offset;
3594 	u8 i;
3595 
3596 	/* SFT */
3597 	instance_offset = mmSFT1_HBW_RTR_IF0_RTR_CTRL_BASE - mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE;
3598 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3599 			gaudi2_pb_sft0, ARRAY_SIZE(gaudi2_pb_sft0));
3600 
3601 	/* HIF */
3602 	instance_offset = mmDCORE0_HIF1_BASE - mmDCORE0_HIF0_BASE;
3603 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3604 			NUM_OF_HIF_PER_DCORE, instance_offset,
3605 			gaudi2_pb_dcr0_hif, ARRAY_SIZE(gaudi2_pb_dcr0_hif),
3606 			prop->hmmu_hif_enabled_mask);
3607 
3608 	/* RTR */
3609 	instance_offset = mmDCORE0_RTR1_CTRL_BASE - mmDCORE0_RTR0_CTRL_BASE;
3610 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3611 			gaudi2_pb_dcr0_rtr0, ARRAY_SIZE(gaudi2_pb_dcr0_rtr0));
3612 
3613 	/* HMMU */
3614 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3615 			NUM_OF_HMMU_PER_DCORE, DCORE_HMMU_OFFSET,
3616 			gaudi2_pb_dcr0_hmmu0, ARRAY_SIZE(gaudi2_pb_dcr0_hmmu0),
3617 			prop->hmmu_hif_enabled_mask);
3618 
3619 	/* CPU.
3620 	 * Except for CPU_IF, skip when security is enabled in F/W, because the blocks are protected
3621 	 * by privileged RR.
3622 	 */
3623 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3624 			gaudi2_pb_cpu_if, ARRAY_SIZE(gaudi2_pb_cpu_if));
3625 	if (!hdev->asic_prop.fw_security_enabled)
3626 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3627 				gaudi2_pb_cpu, ARRAY_SIZE(gaudi2_pb_cpu));
3628 
3629 	/* KDMA */
3630 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3631 			gaudi2_pb_kdma, ARRAY_SIZE(gaudi2_pb_kdma));
3632 
3633 	/* PDMA */
3634 	instance_offset = mmPDMA1_CORE_BASE - mmPDMA0_CORE_BASE;
3635 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3636 			gaudi2_pb_pdma0, ARRAY_SIZE(gaudi2_pb_pdma0));
3637 
3638 	/* ARC PDMA */
3639 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 2, instance_offset,
3640 			gaudi2_pb_pdma0_arc, ARRAY_SIZE(gaudi2_pb_pdma0_arc));
3641 
3642 	/* EDMA */
3643 	instance_offset = mmDCORE0_EDMA1_CORE_BASE - mmDCORE0_EDMA0_CORE_BASE;
3644 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3645 			instance_offset, gaudi2_pb_dcr0_edma0,
3646 			ARRAY_SIZE(gaudi2_pb_dcr0_edma0),
3647 			prop->edma_enabled_mask);
3648 
3649 	/* ARC EDMA */
3650 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET, 2,
3651 			instance_offset, gaudi2_pb_dcr0_edma0_arc,
3652 			ARRAY_SIZE(gaudi2_pb_dcr0_edma0_arc),
3653 			prop->edma_enabled_mask);
3654 
3655 	/* MME */
3656 	instance_offset = mmDCORE0_MME_SBTE1_BASE - mmDCORE0_MME_SBTE0_BASE;
3657 
3658 	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3659 		/* MME SBTE */
3660 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i), 5,
3661 				instance_offset, gaudi2_pb_dcr0_mme_sbte,
3662 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_sbte));
3663 
3664 		/* MME */
3665 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3666 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3667 				gaudi2_pb_dcr0_mme_eng,
3668 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_eng));
3669 	}
3670 
3671 	/*
3672 	 * we have special iteration for case in which we would like to
3673 	 * configure stubbed MME's ARC/QMAN
3674 	 */
3675 	for (i = 0 ; i < NUM_OF_DCORES * NUM_OF_MME_PER_DCORE ; i++) {
3676 		/* MME QM */
3677 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3678 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3679 				gaudi2_pb_dcr0_mme_qm,
3680 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_qm));
3681 
3682 		/* ARC MME */
3683 		hl_ack_pb_single_dcore(hdev, (DCORE_OFFSET * i),
3684 				HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3685 				gaudi2_pb_dcr0_mme_arc,
3686 				ARRAY_SIZE(gaudi2_pb_dcr0_mme_arc));
3687 	}
3688 
3689 	/* MME QM ARC ACP ENG */
3690 	hl_ack_pb_with_mask(hdev, NUM_OF_DCORES, DCORE_OFFSET,
3691 			HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3692 			gaudi2_pb_mme_qm_arc_acp_eng,
3693 			ARRAY_SIZE(gaudi2_pb_mme_qm_arc_acp_eng),
3694 			(BIT(NUM_OF_DCORES * NUM_OF_MME_PER_DCORE) - 1));
3695 
3696 	/* TPC */
3697 	gaudi2_ack_pb_tpc(hdev);
3698 
3699 	/* SRAM */
3700 	instance_offset = mmDCORE0_SRAM1_BANK_BASE - mmDCORE0_SRAM0_BANK_BASE;
3701 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, 8, instance_offset,
3702 			gaudi2_pb_dcr0_sram0, ARRAY_SIZE(gaudi2_pb_dcr0_sram0));
3703 
3704 	/* Sync Manager MSTR IF */
3705 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3706 			gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3707 
3708 	/* Sync Manager */
3709 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3710 			gaudi2_pb_dcr0_sm_glbl, ARRAY_SIZE(gaudi2_pb_dcr0_sm_glbl));
3711 
3712 	hl_ack_pb(hdev, NUM_OF_DCORES, DCORE_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3713 			gaudi2_pb_dcr0_sm_mstr_if, ARRAY_SIZE(gaudi2_pb_dcr0_sm_mstr_if));
3714 
3715 	/* PSOC.
3716 	 * Except for PSOC_GLOBAL_CONF, skip when security is enabled in F/W, because the blocks are
3717 	 * protected by privileged RR.
3718 	 */
3719 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3720 			gaudi2_pb_psoc_global_conf, ARRAY_SIZE(gaudi2_pb_psoc_global_conf));
3721 	if (!hdev->asic_prop.fw_security_enabled)
3722 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3723 				gaudi2_pb_psoc, ARRAY_SIZE(gaudi2_pb_psoc));
3724 
3725 	/* PMMU */
3726 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3727 			gaudi2_pb_pmmu, ARRAY_SIZE(gaudi2_pb_pmmu));
3728 
3729 	/* PLL.
3730 	 * Skip PSOC/XFT PLL when security is enabled in F/W, because these blocks are protected by
3731 	 * privileged RR.
3732 	 */
3733 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3734 			gaudi2_pb_pmmu_pll, ARRAY_SIZE(gaudi2_pb_pmmu_pll));
3735 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3736 			gaudi2_pb_xbar_pll, ARRAY_SIZE(gaudi2_pb_xbar_pll));
3737 	if (!hdev->asic_prop.fw_security_enabled) {
3738 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3739 				gaudi2_pb_psoc_pll, ARRAY_SIZE(gaudi2_pb_psoc_pll));
3740 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3741 				gaudi2_pb_xft_pll, ARRAY_SIZE(gaudi2_pb_xft_pll));
3742 	}
3743 
3744 	/* PCIE */
3745 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3746 			gaudi2_pb_pcie, ARRAY_SIZE(gaudi2_pb_pcie));
3747 
3748 	/* Thermal Sensor.
3749 	 * Skip when security is enabled in F/W, because the blocks are protected by privileged RR.
3750 	 */
3751 	if (!hdev->asic_prop.fw_security_enabled) {
3752 		instance_offset = mmDCORE1_XFT_BASE - mmDCORE0_XFT_BASE;
3753 		hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, 4, instance_offset,
3754 				gaudi2_pb_thermal_sensor0, ARRAY_SIZE(gaudi2_pb_thermal_sensor0));
3755 	}
3756 
3757 	/* HBM */
3758 	instance_offset = mmHBM1_MC0_BASE - mmHBM0_MC0_BASE;
3759 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, GAUDI2_HBM_NUM,
3760 			instance_offset, gaudi2_pb_hbm,
3761 			ARRAY_SIZE(gaudi2_pb_hbm), prop->dram_enabled_mask);
3762 
3763 	/* Scheduler ARCs */
3764 	instance_offset = mmARC_FARM_ARC1_AUX_BASE - mmARC_FARM_ARC0_AUX_BASE;
3765 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ARC_FARMS_ARC,
3766 			instance_offset, gaudi2_pb_arc_sched,
3767 			ARRAY_SIZE(gaudi2_pb_arc_sched));
3768 
3769 	/* XBAR MIDs */
3770 	instance_offset = mmXBAR_MID_1_BASE - mmXBAR_MID_0_BASE;
3771 	hl_ack_pb(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3772 			instance_offset, gaudi2_pb_xbar_mid,
3773 			ARRAY_SIZE(gaudi2_pb_xbar_mid));
3774 
3775 	/* XBAR EDGEs */
3776 	instance_offset = mmXBAR_EDGE_1_BASE - mmXBAR_EDGE_0_BASE;
3777 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_XBAR,
3778 			instance_offset, gaudi2_pb_xbar_edge,
3779 			ARRAY_SIZE(gaudi2_pb_xbar_edge), prop->xbar_edge_enabled_mask);
3780 
3781 	/* NIC */
3782 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, HL_PB_SINGLE_INSTANCE, HL_PB_NA,
3783 			gaudi2_pb_nic0, ARRAY_SIZE(gaudi2_pb_nic0), hdev->nic_ports_mask);
3784 
3785 	/* NIC QM and QPC */
3786 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3787 			NIC_QM_OFFSET, gaudi2_pb_nic0_qm_qpc, ARRAY_SIZE(gaudi2_pb_nic0_qm_qpc),
3788 			hdev->nic_ports_mask);
3789 
3790 	/* NIC QM ARC */
3791 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3792 			NIC_QM_OFFSET, gaudi2_pb_nic0_qm_arc_aux0,
3793 			ARRAY_SIZE(gaudi2_pb_nic0_qm_arc_aux0), hdev->nic_ports_mask);
3794 
3795 	/* NIC UMR */
3796 	hl_ack_pb_with_mask(hdev, NIC_NUMBER_OF_MACROS, NIC_OFFSET, NIC_NUMBER_OF_QM_PER_MACRO,
3797 			NIC_QM_OFFSET, gaudi2_pb_nic0_umr, ARRAY_SIZE(gaudi2_pb_nic0_umr),
3798 			hdev->nic_ports_mask);
3799 
3800 	/* Rotators */
3801 	instance_offset = mmROT1_BASE - mmROT0_BASE;
3802 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3803 			gaudi2_pb_rot0, ARRAY_SIZE(gaudi2_pb_rot0), (BIT(NUM_OF_ROT) - 1));
3804 
3805 	/* Rotators ARCS */
3806 	hl_ack_pb_with_mask(hdev, HL_PB_SHARED, HL_PB_NA, NUM_OF_ROT, instance_offset,
3807 			gaudi2_pb_rot0_arc, ARRAY_SIZE(gaudi2_pb_rot0_arc), (BIT(NUM_OF_ROT) - 1));
3808 }
3809 
3810 /*
3811  * Print PB security errors
3812  */
3813 
3814 void gaudi2_pb_print_security_errors(struct hl_device *hdev, u32 block_addr, u32 cause,
3815 					u32 offended_addr)
3816 {
3817 	int i = 0;
3818 	const char *error_format =
3819 		"Security error at block 0x%x, offending address 0x%x\n"
3820 		"Cause 0x%x: %s %s %s %s %s %s %s %s\n";
3821 	char *mcause[8] = {"Unknown", "", "", "", "", "", "", "" };
3822 
3823 	if (!cause)
3824 		return;
3825 
3826 	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD)
3827 		mcause[i++] = "APB_PRIV_RD";
3828 
3829 	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD)
3830 		mcause[i++] = "APB_SEC_RD";
3831 
3832 	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD)
3833 		mcause[i++] = "APB_UNMAPPED_RD";
3834 
3835 	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR)
3836 		mcause[i++] = "APB_PRIV_WR";
3837 
3838 	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR)
3839 		mcause[i++] = "APB_SEC_WR";
3840 
3841 	if (cause & SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR)
3842 		mcause[i++] = "APB_UNMAPPED_WR";
3843 
3844 	if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR)
3845 		mcause[i++] = "EXT_SEC_WR";
3846 
3847 	if (cause & SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR)
3848 		mcause[i++] = "APB_EXT_UNMAPPED_WR";
3849 
3850 	dev_err_ratelimited(hdev->dev, error_format, block_addr, offended_addr,
3851 			cause, mcause[0], mcause[1], mcause[2], mcause[3],
3852 			mcause[4], mcause[5], mcause[6], mcause[7]);
3853 }
3854