1*e65e175bSOded Gabbay /* SPDX-License-Identifier: GPL-2.0 2*e65e175bSOded Gabbay * 3*e65e175bSOded Gabbay * Copyright 2020-2022 HabanaLabs, Ltd. 4*e65e175bSOded Gabbay * All Rights Reserved. 5*e65e175bSOded Gabbay * 6*e65e175bSOded Gabbay */ 7*e65e175bSOded Gabbay 8*e65e175bSOded Gabbay #ifndef GAUDI2_MASKS_H_ 9*e65e175bSOded Gabbay #define GAUDI2_MASKS_H_ 10*e65e175bSOded Gabbay 11*e65e175bSOded Gabbay #include "../include/gaudi2/asic_reg/gaudi2_regs.h" 12*e65e175bSOded Gabbay 13*e65e175bSOded Gabbay /* Useful masks for bits in various registers */ 14*e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG_MSG_EN_MASK \ 15*e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_ERR_MSG_EN_SHIFT) | \ 16*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_ERR_MSG_EN_SHIFT) | \ 17*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_ERR_MSG_EN_SHIFT)) 18*e65e175bSOded Gabbay 19*e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG_STOP_ON_ERR_EN_MASK \ 20*e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_ERR_CFG_PQF_STOP_ON_ERR_SHIFT) | \ 21*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CQF_STOP_ON_ERR_SHIFT) | \ 22*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_ERR_CFG_CP_STOP_ON_ERR_SHIFT) | \ 23*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_ERR_CFG_ARB_STOP_ON_ERR_SHIFT)) 24*e65e175bSOded Gabbay 25*e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG1_MSG_EN_MASK \ 26*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_ERR_MSG_EN_SHIFT) 27*e65e175bSOded Gabbay 28*e65e175bSOded Gabbay #define QMAN_GLBL_ERR_CFG1_STOP_ON_ERR_EN_MASK \ 29*e65e175bSOded Gabbay ((0x1 << PDMA0_QM_GLBL_ERR_CFG1_CQF_STOP_ON_ERR_SHIFT) | \ 30*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_ERR_CFG1_ARC_STOP_ON_ERR_SHIFT)) 31*e65e175bSOded Gabbay 32*e65e175bSOded Gabbay #define QM_PQC_LBW_WDATA \ 33*e65e175bSOded Gabbay ((1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_VAL_SHIFT) | \ 34*e65e175bSOded Gabbay (1 << DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_INC_SHIFT)) 35*e65e175bSOded Gabbay 36*e65e175bSOded Gabbay #define QMAN_MAKE_TRUSTED \ 37*e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \ 38*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \ 39*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT)) 40*e65e175bSOded Gabbay 41*e65e175bSOded Gabbay #define QMAN_MAKE_TRUSTED_TEST_MODE \ 42*e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_PROT_PQF_SHIFT) | \ 43*e65e175bSOded Gabbay (0xF << PDMA0_QM_GLBL_PROT_CQF_SHIFT) | \ 44*e65e175bSOded Gabbay (0xF << PDMA0_QM_GLBL_PROT_CP_SHIFT) | \ 45*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_ERR_SHIFT) | \ 46*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_PROT_PQC_SHIFT)) 47*e65e175bSOded Gabbay 48*e65e175bSOded Gabbay #define QMAN_ENABLE \ 49*e65e175bSOded Gabbay ((0xF << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 50*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 51*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ 52*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) 53*e65e175bSOded Gabbay 54*e65e175bSOded Gabbay #define PDMA0_QMAN_ENABLE \ 55*e65e175bSOded Gabbay ((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 56*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 57*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ 58*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) 59*e65e175bSOded Gabbay 60*e65e175bSOded Gabbay #define PDMA1_QMAN_ENABLE \ 61*e65e175bSOded Gabbay ((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \ 62*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \ 63*e65e175bSOded Gabbay (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT) | \ 64*e65e175bSOded Gabbay (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT)) 65*e65e175bSOded Gabbay 66*e65e175bSOded Gabbay /* QM_IDLE_MASK is valid for all engines QM idle check */ 67*e65e175bSOded Gabbay #define QM_IDLE_MASK (DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \ 68*e65e175bSOded Gabbay DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \ 69*e65e175bSOded Gabbay DCORE0_EDMA0_QM_GLBL_STS0_CP_IDLE_MASK) 70*e65e175bSOded Gabbay 71*e65e175bSOded Gabbay #define QM_ARC_IDLE_MASK DCORE0_EDMA0_QM_GLBL_STS1_ARC_CQF_IDLE_MASK 72*e65e175bSOded Gabbay 73*e65e175bSOded Gabbay #define MME_ARCH_IDLE_MASK \ 74*e65e175bSOded Gabbay (DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_EMPTY_MASK | \ 75*e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_AGU_COUT_SM_IDLE_MASK | \ 76*e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_WBC_AXI_IDLE_MASK | \ 77*e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_SB_IN_AXI_IDLE_MASK | \ 78*e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_IDLE_MASK | \ 79*e65e175bSOded Gabbay DCORE0_MME_CTRL_LO_ARCH_STATUS_QM_RDY_MASK) 80*e65e175bSOded Gabbay 81*e65e175bSOded Gabbay #define TPC_IDLE_MASK (DCORE0_TPC0_CFG_STATUS_SCALAR_PIPE_EMPTY_MASK | \ 82*e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_VECTOR_PIPE_EMPTY_MASK | \ 83*e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_IQ_EMPTY_MASK | \ 84*e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_SB_EMPTY_MASK | \ 85*e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_QM_IDLE_MASK | \ 86*e65e175bSOded Gabbay DCORE0_TPC0_CFG_STATUS_QM_RDY_MASK) 87*e65e175bSOded Gabbay 88*e65e175bSOded Gabbay #define DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 0x100 89*e65e175bSOded Gabbay 90*e65e175bSOded Gabbay /* CGM_IDLE_MASK is valid for all engines CGM idle check */ 91*e65e175bSOded Gabbay #define CGM_IDLE_MASK DCORE0_TPC0_QM_CGM_STS_AGENT_IDLE_MASK 92*e65e175bSOded Gabbay 93*e65e175bSOded Gabbay #define QM_GLBL_CFG1_PQF_STOP PDMA0_QM_GLBL_CFG1_PQF_STOP_MASK 94*e65e175bSOded Gabbay #define QM_GLBL_CFG1_CQF_STOP PDMA0_QM_GLBL_CFG1_CQF_STOP_MASK 95*e65e175bSOded Gabbay #define QM_GLBL_CFG1_CP_STOP PDMA0_QM_GLBL_CFG1_CP_STOP_MASK 96*e65e175bSOded Gabbay #define QM_GLBL_CFG1_PQF_FLUSH PDMA0_QM_GLBL_CFG1_PQF_FLUSH_MASK 97*e65e175bSOded Gabbay #define QM_GLBL_CFG1_CQF_FLUSH PDMA0_QM_GLBL_CFG1_CQF_FLUSH_MASK 98*e65e175bSOded Gabbay #define QM_GLBL_CFG1_CP_FLUSH PDMA0_QM_GLBL_CFG1_CP_FLUSH_MASK 99*e65e175bSOded Gabbay 100*e65e175bSOded Gabbay #define QM_GLBL_CFG2_ARC_CQF_STOP PDMA0_QM_GLBL_CFG2_ARC_CQF_STOP_MASK 101*e65e175bSOded Gabbay #define QM_GLBL_CFG2_ARC_CQF_FLUSH PDMA0_QM_GLBL_CFG2_ARC_CQF_FLUSH_MASK 102*e65e175bSOded Gabbay 103*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK 0x1 104*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK 0x2 105*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK 0x4 106*e65e175bSOded Gabbay 107*e65e175bSOded Gabbay #define QM_ARB_ERR_MSG_EN_MASK (\ 108*e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_CHOISE_OVF_MASK |\ 109*e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_CHOISE_WDT_MASK |\ 110*e65e175bSOded Gabbay QM_ARB_ERR_MSG_EN_AXI_LBW_ERR_MASK) 111*e65e175bSOded Gabbay 112*e65e175bSOded Gabbay #define PCIE_AUX_FLR_CTRL_HW_CTRL_MASK 0x1 113*e65e175bSOded Gabbay #define PCIE_AUX_FLR_CTRL_INT_MASK_MASK 0x2 114*e65e175bSOded Gabbay 115*e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_WBC_ERR_RESP_MASK GENMASK(1, 0) 116*e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_SRC_POS_INF_MASK BIT(2) 117*e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_SRC_NEG_INF_MASK BIT(3) 118*e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_SRC_NAN_MASK BIT(4) 119*e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_RESULT_POS_INF_MASK BIT(5) 120*e65e175bSOded Gabbay #define MME_ACC_INTR_MASK_AP_RESULT_NEG_INF_MASK BIT(6) 121*e65e175bSOded Gabbay 122*e65e175bSOded Gabbay #define SM_CQ_L2H_MASK_VAL 0xFFFFFFFFFC000000ull 123*e65e175bSOded Gabbay #define SM_CQ_L2H_CMPR_VAL 0x1000007FFC000000ull 124*e65e175bSOded Gabbay #define SM_CQ_L2H_LOW_MASK GENMASK(31, 20) 125*e65e175bSOded Gabbay #define SM_CQ_L2H_LOW_SHIFT 20 126*e65e175bSOded Gabbay 127*e65e175bSOded Gabbay #define MMU_STATIC_MULTI_PAGE_SIZE_HOP4_PAGE_SIZE_MASK \ 128*e65e175bSOded Gabbay REG_FIELD_MASK(DCORE0_HMMU0_MMU_STATIC_MULTI_PAGE_SIZE, HOP4_PAGE_SIZE) 129*e65e175bSOded Gabbay #define STLB_HOP_CONFIGURATION_ONLY_LARGE_PAGE_MASK \ 130*e65e175bSOded Gabbay REG_FIELD_MASK(DCORE0_HMMU0_STLB_HOP_CONFIGURATION, ONLY_LARGE_PAGE) 131*e65e175bSOded Gabbay 132*e65e175bSOded Gabbay #define AXUSER_HB_SEC_ASID_MASK 0x3FF 133*e65e175bSOded Gabbay #define AXUSER_HB_SEC_MMBP_MASK 0x400 134*e65e175bSOded Gabbay 135*e65e175bSOded Gabbay #define MMUBP_ASID_MASK (AXUSER_HB_SEC_ASID_MASK | AXUSER_HB_SEC_MMBP_MASK) 136*e65e175bSOded Gabbay 137*e65e175bSOded Gabbay #define ROT_MSS_HALT_WBC_MASK BIT(0) 138*e65e175bSOded Gabbay #define ROT_MSS_HALT_RSB_MASK BIT(1) 139*e65e175bSOded Gabbay #define ROT_MSS_HALT_MRSB_MASK BIT(2) 140*e65e175bSOded Gabbay 141*e65e175bSOded Gabbay #define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_SHIFT 0 142*e65e175bSOded Gabbay #define PCIE_DBI_MSIX_ADDRESS_MATCH_LOW_OFF_MSIX_ADDRESS_MATCH_EN_MASK 0x1 143*e65e175bSOded Gabbay 144*e65e175bSOded Gabbay #define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_SHIFT 15 145*e65e175bSOded Gabbay #define DCORE0_SYNC_MNGR_OBJS_SOB_OBJ_SIGN_MASK 0x8000 146*e65e175bSOded Gabbay 147*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_SHIFT 0 148*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK 0x1 149*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_SHIFT 1 150*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK 0x2 151*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_SHIFT 2 152*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK 0x4 153*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_SHIFT 3 154*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_ERR_INTR_MASK_MASK 0x8 155*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_SHIFT 4 156*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_AXI_LBW_ERR_INTR_MASK_MASK 0x10 157*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_SHIFT 5 158*e65e175bSOded Gabbay #define PCIE_WRAP_PCIE_IC_SEI_INTR_IND_BAD_ACCESS_INTR_MASK_MASK 0x20 159*e65e175bSOded Gabbay 160*e65e175bSOded Gabbay #endif /* GAUDI2_MASKS_H_ */ 161