1ca55b2feSMax Filippov /* 2ca55b2feSMax Filippov * tie-asm.h -- compile-time HAL assembler definitions dependent on CORE & TIE 3ca55b2feSMax Filippov * 4ca55b2feSMax Filippov * NOTE: This header file is not meant to be included directly. 5ca55b2feSMax Filippov */ 6ca55b2feSMax Filippov 7ca55b2feSMax Filippov /* This header file contains assembly-language definitions (assembly 8ca55b2feSMax Filippov macros, etc.) for this specific Xtensa processor's TIE extensions 9ca55b2feSMax Filippov and options. It is customized to this Xtensa processor configuration. 10ca55b2feSMax Filippov 11ca55b2feSMax Filippov Copyright (c) 1999-2015 Cadence Design Systems Inc. 12ca55b2feSMax Filippov 13ca55b2feSMax Filippov Permission is hereby granted, free of charge, to any person obtaining 14ca55b2feSMax Filippov a copy of this software and associated documentation files (the 15ca55b2feSMax Filippov "Software"), to deal in the Software without restriction, including 16ca55b2feSMax Filippov without limitation the rights to use, copy, modify, merge, publish, 17ca55b2feSMax Filippov distribute, sublicense, and/or sell copies of the Software, and to 18ca55b2feSMax Filippov permit persons to whom the Software is furnished to do so, subject to 19ca55b2feSMax Filippov the following conditions: 20ca55b2feSMax Filippov 21ca55b2feSMax Filippov The above copyright notice and this permission notice shall be included 22ca55b2feSMax Filippov in all copies or substantial portions of the Software. 23ca55b2feSMax Filippov 24ca55b2feSMax Filippov THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 25ca55b2feSMax Filippov EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 26ca55b2feSMax Filippov MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 27ca55b2feSMax Filippov IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY 28ca55b2feSMax Filippov CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 29ca55b2feSMax Filippov TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 30ca55b2feSMax Filippov SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */ 31ca55b2feSMax Filippov 32ca55b2feSMax Filippov #ifndef _XTENSA_CORE_TIE_ASM_H 33ca55b2feSMax Filippov #define _XTENSA_CORE_TIE_ASM_H 34ca55b2feSMax Filippov 35ca55b2feSMax Filippov /* Selection parameter values for save-area save/restore macros: */ 36ca55b2feSMax Filippov /* Option vs. TIE: */ 37ca55b2feSMax Filippov #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 38ca55b2feSMax Filippov #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 39ca55b2feSMax Filippov #define XTHAL_SAS_ANYOT 0x0003 /* both of the above */ 40ca55b2feSMax Filippov /* Whether used automatically by compiler: */ 41ca55b2feSMax Filippov #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 42ca55b2feSMax Filippov #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 43ca55b2feSMax Filippov #define XTHAL_SAS_ANYCC 0x000C /* both of the above */ 44ca55b2feSMax Filippov /* ABI handling across function calls: */ 45ca55b2feSMax Filippov #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 46ca55b2feSMax Filippov #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 47ca55b2feSMax Filippov #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 48ca55b2feSMax Filippov #define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */ 49ca55b2feSMax Filippov /* Misc */ 50ca55b2feSMax Filippov #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 51ca55b2feSMax Filippov #define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \ 52ca55b2feSMax Filippov | ((ccuse) & XTHAL_SAS_ANYCC) \ 53ca55b2feSMax Filippov | ((abi) & XTHAL_SAS_ANYABI) ) 54ca55b2feSMax Filippov 55ca55b2feSMax Filippov 56ca55b2feSMax Filippov /* 57ca55b2feSMax Filippov * Macro to store all non-coprocessor (extra) custom TIE and optional state 58ca55b2feSMax Filippov * (not including zero-overhead loop registers). 59ca55b2feSMax Filippov * Required parameters: 60ca55b2feSMax Filippov * ptr Save area pointer address register (clobbered) 61ca55b2feSMax Filippov * (register must contain a 4 byte aligned address). 62ca55b2feSMax Filippov * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 63ca55b2feSMax Filippov * registers are clobbered, the remaining are unused). 64ca55b2feSMax Filippov * Optional parameters: 65ca55b2feSMax Filippov * continue If macro invoked as part of a larger store sequence, set to 1 66ca55b2feSMax Filippov * if this is not the first in the sequence. Defaults to 0. 67ca55b2feSMax Filippov * ofs Offset from start of larger sequence (from value of first ptr 68ca55b2feSMax Filippov * in sequence) at which to store. Defaults to next available space 69ca55b2feSMax Filippov * (or 0 if <continue> is 0). 70ca55b2feSMax Filippov * select Select what category(ies) of registers to store, as a bitmask 71ca55b2feSMax Filippov * (see XTHAL_SAS_xxx constants). Defaults to all registers. 72ca55b2feSMax Filippov * alloc Select what category(ies) of registers to allocate; if any 73ca55b2feSMax Filippov * category is selected here that is not in <select>, space for 74ca55b2feSMax Filippov * the corresponding registers is skipped without doing any store. 75ca55b2feSMax Filippov */ 76ca55b2feSMax Filippov .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 77ca55b2feSMax Filippov xchal_sa_start \continue, \ofs 78ca55b2feSMax Filippov // Optional caller-saved registers used by default by the compiler: 79ca55b2feSMax Filippov .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 80ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1016, 4, 4 81ca55b2feSMax Filippov rsr.ACCLO \at1 // MAC16 option 82ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+0 83ca55b2feSMax Filippov rsr.ACCHI \at1 // MAC16 option 84ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+4 85ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 86ca55b2feSMax Filippov .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 87ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1016, 4, 4 88ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 89ca55b2feSMax Filippov .endif 90ca55b2feSMax Filippov // Optional caller-saved registers not used by default by the compiler: 91ca55b2feSMax Filippov .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 92ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1004, 4, 4 93ca55b2feSMax Filippov rsr.SCOMPARE1 \at1 // conditional store option 94ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+0 95ca55b2feSMax Filippov rsr.M0 \at1 // MAC16 option 96ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+4 97ca55b2feSMax Filippov rsr.M1 \at1 // MAC16 option 98ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+8 99ca55b2feSMax Filippov rsr.M2 \at1 // MAC16 option 100ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+12 101ca55b2feSMax Filippov rsr.M3 \at1 // MAC16 option 102ca55b2feSMax Filippov s32i \at1, \ptr, .Lxchal_ofs_+16 103ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 104ca55b2feSMax Filippov .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 105ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1004, 4, 4 106ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 107ca55b2feSMax Filippov .endif 108ca55b2feSMax Filippov .endm // xchal_ncp_store 109ca55b2feSMax Filippov 110ca55b2feSMax Filippov /* 111ca55b2feSMax Filippov * Macro to load all non-coprocessor (extra) custom TIE and optional state 112ca55b2feSMax Filippov * (not including zero-overhead loop registers). 113ca55b2feSMax Filippov * Required parameters: 114ca55b2feSMax Filippov * ptr Save area pointer address register (clobbered) 115ca55b2feSMax Filippov * (register must contain a 4 byte aligned address). 116ca55b2feSMax Filippov * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS 117ca55b2feSMax Filippov * registers are clobbered, the remaining are unused). 118ca55b2feSMax Filippov * Optional parameters: 119ca55b2feSMax Filippov * continue If macro invoked as part of a larger load sequence, set to 1 120ca55b2feSMax Filippov * if this is not the first in the sequence. Defaults to 0. 121ca55b2feSMax Filippov * ofs Offset from start of larger sequence (from value of first ptr 122ca55b2feSMax Filippov * in sequence) at which to load. Defaults to next available space 123ca55b2feSMax Filippov * (or 0 if <continue> is 0). 124ca55b2feSMax Filippov * select Select what category(ies) of registers to load, as a bitmask 125ca55b2feSMax Filippov * (see XTHAL_SAS_xxx constants). Defaults to all registers. 126ca55b2feSMax Filippov * alloc Select what category(ies) of registers to allocate; if any 127ca55b2feSMax Filippov * category is selected here that is not in <select>, space for 128ca55b2feSMax Filippov * the corresponding registers is skipped without doing any load. 129ca55b2feSMax Filippov */ 130ca55b2feSMax Filippov .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0 131ca55b2feSMax Filippov xchal_sa_start \continue, \ofs 132ca55b2feSMax Filippov // Optional caller-saved registers used by default by the compiler: 133ca55b2feSMax Filippov .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select) 134ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1016, 4, 4 135ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+0 136ca55b2feSMax Filippov wsr.ACCLO \at1 // MAC16 option 137ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+4 138ca55b2feSMax Filippov wsr.ACCHI \at1 // MAC16 option 139ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 140ca55b2feSMax Filippov .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 141ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1016, 4, 4 142ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 8 143ca55b2feSMax Filippov .endif 144ca55b2feSMax Filippov // Optional caller-saved registers not used by default by the compiler: 145ca55b2feSMax Filippov .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select) 146ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1004, 4, 4 147ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+0 148ca55b2feSMax Filippov wsr.SCOMPARE1 \at1 // conditional store option 149ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+4 150ca55b2feSMax Filippov wsr.M0 \at1 // MAC16 option 151ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+8 152ca55b2feSMax Filippov wsr.M1 \at1 // MAC16 option 153ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+12 154ca55b2feSMax Filippov wsr.M2 \at1 // MAC16 option 155ca55b2feSMax Filippov l32i \at1, \ptr, .Lxchal_ofs_+16 156ca55b2feSMax Filippov wsr.M3 \at1 // MAC16 option 157ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 158ca55b2feSMax Filippov .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0 159ca55b2feSMax Filippov xchal_sa_align \ptr, 0, 1004, 4, 4 160ca55b2feSMax Filippov .set .Lxchal_ofs_, .Lxchal_ofs_ + 20 161ca55b2feSMax Filippov .endif 162ca55b2feSMax Filippov .endm // xchal_ncp_load 163ca55b2feSMax Filippov 164ca55b2feSMax Filippov 165ca55b2feSMax Filippov #define XCHAL_NCP_NUM_ATMPS 1 166ca55b2feSMax Filippov 167ca55b2feSMax Filippov #define XCHAL_SA_NUM_ATMPS 1 168ca55b2feSMax Filippov 169ca55b2feSMax Filippov #endif /*_XTENSA_CORE_TIE_ASM_H*/ 170ca55b2feSMax Filippov 171