1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  *
4  * arch/xtensa/platform/xtavnet/setup.c
5  *
6  * ...
7  *
8  * Authors:	Chris Zankel <chris@zankel.net>
9  *		Joe Taylor <joe@tensilica.com>
10  *
11  * Copyright 2001 - 2006 Tensilica Inc.
12  */
13 #include <linux/stddef.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/io.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/kdev_t.h>
20 #include <linux/types.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/of.h>
25 #include <linux/clk-provider.h>
26 #include <linux/of_address.h>
27 #include <linux/slab.h>
28 
29 #include <asm/timex.h>
30 #include <asm/processor.h>
31 #include <asm/platform.h>
32 #include <asm/bootparam.h>
33 #include <platform/lcd.h>
34 #include <platform/hardware.h>
35 
36 void platform_halt(void)
37 {
38 	lcd_disp_at_pos(" HALT ", 0);
39 	local_irq_disable();
40 	while (1)
41 		cpu_relax();
42 }
43 
44 void platform_power_off(void)
45 {
46 	lcd_disp_at_pos("POWEROFF", 0);
47 	local_irq_disable();
48 	while (1)
49 		cpu_relax();
50 }
51 
52 void platform_restart(void)
53 {
54 	/* Try software reset first. */
55 	WRITE_ONCE(*(u32 *)XTFPGA_SWRST_VADDR, 0xdead);
56 
57 	/* If software reset did not work, flush and reset the mmu,
58 	 * simulate a processor reset, and jump to the reset vector.
59 	 */
60 	cpu_reset();
61 	/* control never gets here */
62 }
63 
64 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
65 
66 void __init platform_calibrate_ccount(void)
67 {
68 	ccount_freq = *(long *)XTFPGA_CLKFRQ_VADDR;
69 }
70 
71 #endif
72 
73 #ifdef CONFIG_USE_OF
74 
75 static void __init xtfpga_clk_setup(struct device_node *np)
76 {
77 	void __iomem *base = of_iomap(np, 0);
78 	struct clk *clk;
79 	u32 freq;
80 
81 	if (!base) {
82 		pr_err("%pOFn: invalid address\n", np);
83 		return;
84 	}
85 
86 	freq = __raw_readl(base);
87 	iounmap(base);
88 	clk = clk_register_fixed_rate(NULL, np->name, NULL, 0, freq);
89 
90 	if (IS_ERR(clk)) {
91 		pr_err("%pOFn: clk registration failed\n", np);
92 		return;
93 	}
94 
95 	if (of_clk_add_provider(np, of_clk_src_simple_get, clk)) {
96 		pr_err("%pOFn: clk provider registration failed\n", np);
97 		return;
98 	}
99 }
100 CLK_OF_DECLARE(xtfpga_clk, "cdns,xtfpga-clock", xtfpga_clk_setup);
101 
102 #define MAC_LEN 6
103 static void __init update_local_mac(struct device_node *node)
104 {
105 	struct property *newmac;
106 	const u8* macaddr;
107 	int prop_len;
108 
109 	macaddr = of_get_property(node, "local-mac-address", &prop_len);
110 	if (macaddr == NULL || prop_len != MAC_LEN)
111 		return;
112 
113 	newmac = kzalloc(sizeof(*newmac) + MAC_LEN, GFP_KERNEL);
114 	if (newmac == NULL)
115 		return;
116 
117 	newmac->value = newmac + 1;
118 	newmac->length = MAC_LEN;
119 	newmac->name = kstrdup("local-mac-address", GFP_KERNEL);
120 	if (newmac->name == NULL) {
121 		kfree(newmac);
122 		return;
123 	}
124 
125 	memcpy(newmac->value, macaddr, MAC_LEN);
126 	((u8*)newmac->value)[5] = (*(u32*)DIP_SWITCHES_VADDR) & 0x3f;
127 	of_update_property(node, newmac);
128 }
129 
130 static int __init machine_setup(void)
131 {
132 	struct device_node *eth = NULL;
133 
134 	if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc")))
135 		update_local_mac(eth);
136 	return 0;
137 }
138 arch_initcall(machine_setup);
139 
140 #else
141 
142 #include <linux/serial_8250.h>
143 #include <linux/if.h>
144 #include <net/ethoc.h>
145 #include <linux/usb/c67x00.h>
146 
147 /*----------------------------------------------------------------------------
148  *  Ethernet -- OpenCores Ethernet MAC (ethoc driver)
149  */
150 
151 static struct resource ethoc_res[] = {
152 	[0] = { /* register space */
153 		.start = OETH_REGS_PADDR,
154 		.end   = OETH_REGS_PADDR + OETH_REGS_SIZE - 1,
155 		.flags = IORESOURCE_MEM,
156 	},
157 	[1] = { /* buffer space */
158 		.start = OETH_SRAMBUFF_PADDR,
159 		.end   = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1,
160 		.flags = IORESOURCE_MEM,
161 	},
162 	[2] = { /* IRQ number */
163 		.start = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
164 		.end   = XTENSA_PIC_LINUX_IRQ(OETH_IRQ),
165 		.flags = IORESOURCE_IRQ,
166 	},
167 };
168 
169 static struct ethoc_platform_data ethoc_pdata = {
170 	/*
171 	 * The MAC address for these boards is 00:50:c2:13:6f:xx.
172 	 * The last byte (here as zero) is read from the DIP switches on the
173 	 * board.
174 	 */
175 	.hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 },
176 	.phy_id = -1,
177 	.big_endian = XCHAL_HAVE_BE,
178 };
179 
180 static struct platform_device ethoc_device = {
181 	.name = "ethoc",
182 	.id = -1,
183 	.num_resources = ARRAY_SIZE(ethoc_res),
184 	.resource = ethoc_res,
185 	.dev = {
186 		.platform_data = &ethoc_pdata,
187 	},
188 };
189 
190 /*----------------------------------------------------------------------------
191  *  USB Host/Device -- Cypress CY7C67300
192  */
193 
194 static struct resource c67x00_res[] = {
195 	[0] = { /* register space */
196 		.start = C67X00_PADDR,
197 		.end   = C67X00_PADDR + C67X00_SIZE - 1,
198 		.flags = IORESOURCE_MEM,
199 	},
200 	[1] = { /* IRQ number */
201 		.start = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
202 		.end   = XTENSA_PIC_LINUX_IRQ(C67X00_IRQ),
203 		.flags = IORESOURCE_IRQ,
204 	},
205 };
206 
207 static struct c67x00_platform_data c67x00_pdata = {
208 	.sie_config = C67X00_SIE1_HOST | C67X00_SIE2_UNUSED,
209 	.hpi_regstep = 4,
210 };
211 
212 static struct platform_device c67x00_device = {
213 	.name = "c67x00",
214 	.id = -1,
215 	.num_resources = ARRAY_SIZE(c67x00_res),
216 	.resource = c67x00_res,
217 	.dev = {
218 		.platform_data = &c67x00_pdata,
219 	},
220 };
221 
222 /*----------------------------------------------------------------------------
223  *  UART
224  */
225 
226 static struct resource serial_resource = {
227 	.start	= DUART16552_PADDR,
228 	.end	= DUART16552_PADDR + 0x1f,
229 	.flags	= IORESOURCE_MEM,
230 };
231 
232 static struct plat_serial8250_port serial_platform_data[] = {
233 	[0] = {
234 		.mapbase	= DUART16552_PADDR,
235 		.irq		= XTENSA_PIC_LINUX_IRQ(DUART16552_INTNUM),
236 		.flags		= UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
237 				  UPF_IOREMAP,
238 		.iotype		= XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32,
239 		.regshift	= 2,
240 		.uartclk	= 0,    /* set in xtavnet_init() */
241 	},
242 	{ },
243 };
244 
245 static struct platform_device xtavnet_uart = {
246 	.name		= "serial8250",
247 	.id		= PLAT8250_DEV_PLATFORM,
248 	.dev		= {
249 		.platform_data	= serial_platform_data,
250 	},
251 	.num_resources	= 1,
252 	.resource	= &serial_resource,
253 };
254 
255 /* platform devices */
256 static struct platform_device *platform_devices[] __initdata = {
257 	&ethoc_device,
258 	&c67x00_device,
259 	&xtavnet_uart,
260 };
261 
262 
263 static int __init xtavnet_init(void)
264 {
265 	/* Ethernet MAC address.  */
266 	ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR;
267 
268 	/* Clock rate varies among FPGA bitstreams; board specific FPGA register
269 	 * reports the actual clock rate.
270 	 */
271 	serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR;
272 
273 
274 	/* register platform devices */
275 	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
276 
277 	/* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user
278 	 * knows whether they set it correctly on the DIP switches.
279 	 */
280 	pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr);
281 	ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR;
282 
283 	return 0;
284 }
285 
286 /*
287  * Register to be done during do_initcalls().
288  */
289 arch_initcall(xtavnet_init);
290 
291 #endif /* CONFIG_USE_OF */
292