1 /* 2 * 3 * arch/xtensa/platform/xtavnet/setup.c 4 * 5 * ... 6 * 7 * Authors: Chris Zankel <chris@zankel.net> 8 * Joe Taylor <joe@tensilica.com> 9 * 10 * Copyright 2001 - 2006 Tensilica Inc. 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms of the GNU General Public License as published by the 14 * Free Software Foundation; either version 2 of the License, or (at your 15 * option) any later version. 16 * 17 */ 18 #include <linux/stddef.h> 19 #include <linux/kernel.h> 20 #include <linux/init.h> 21 #include <linux/errno.h> 22 #include <linux/reboot.h> 23 #include <linux/kdev_t.h> 24 #include <linux/types.h> 25 #include <linux/major.h> 26 #include <linux/console.h> 27 #include <linux/delay.h> 28 #include <linux/of.h> 29 #include <linux/clk-provider.h> 30 #include <linux/of_address.h> 31 32 #include <asm/timex.h> 33 #include <asm/processor.h> 34 #include <asm/platform.h> 35 #include <asm/bootparam.h> 36 #include <platform/lcd.h> 37 #include <platform/hardware.h> 38 39 void platform_halt(void) 40 { 41 lcd_disp_at_pos(" HALT ", 0); 42 local_irq_disable(); 43 while (1) 44 cpu_relax(); 45 } 46 47 void platform_power_off(void) 48 { 49 lcd_disp_at_pos("POWEROFF", 0); 50 local_irq_disable(); 51 while (1) 52 cpu_relax(); 53 } 54 55 void platform_restart(void) 56 { 57 /* Flush and reset the mmu, simulate a processor reset, and 58 * jump to the reset vector. */ 59 cpu_reset(); 60 /* control never gets here */ 61 } 62 63 void __init platform_setup(char **cmdline) 64 { 65 } 66 67 #ifdef CONFIG_OF 68 69 static void __init update_clock_frequency(struct device_node *node) 70 { 71 struct property *newfreq; 72 u32 freq; 73 74 if (!of_property_read_u32(node, "clock-frequency", &freq) && freq != 0) 75 return; 76 77 newfreq = kzalloc(sizeof(*newfreq) + sizeof(u32), GFP_KERNEL); 78 if (!newfreq) 79 return; 80 newfreq->value = newfreq + 1; 81 newfreq->length = sizeof(freq); 82 newfreq->name = kstrdup("clock-frequency", GFP_KERNEL); 83 if (!newfreq->name) { 84 kfree(newfreq); 85 return; 86 } 87 88 *(u32 *)newfreq->value = cpu_to_be32(*(u32 *)XTFPGA_CLKFRQ_VADDR); 89 of_update_property(node, newfreq); 90 } 91 92 static void __init xtfpga_clk_setup(struct device_node *np) 93 { 94 void __iomem *base = of_iomap(np, 0); 95 struct clk *clk; 96 u32 freq; 97 98 if (!base) { 99 pr_err("%s: invalid address\n", np->name); 100 return; 101 } 102 103 freq = __raw_readl(base); 104 iounmap(base); 105 clk = clk_register_fixed_rate(NULL, np->name, NULL, 0, freq); 106 107 if (IS_ERR(clk)) { 108 pr_err("%s: clk registration failed\n", np->name); 109 return; 110 } 111 112 if (of_clk_add_provider(np, of_clk_src_simple_get, clk)) { 113 pr_err("%s: clk provider registration failed\n", np->name); 114 return; 115 } 116 } 117 CLK_OF_DECLARE(xtfpga_clk, "cdns,xtfpga-clock", xtfpga_clk_setup); 118 119 #define MAC_LEN 6 120 static void __init update_local_mac(struct device_node *node) 121 { 122 struct property *newmac; 123 const u8* macaddr; 124 int prop_len; 125 126 macaddr = of_get_property(node, "local-mac-address", &prop_len); 127 if (macaddr == NULL || prop_len != MAC_LEN) 128 return; 129 130 newmac = kzalloc(sizeof(*newmac) + MAC_LEN, GFP_KERNEL); 131 if (newmac == NULL) 132 return; 133 134 newmac->value = newmac + 1; 135 newmac->length = MAC_LEN; 136 newmac->name = kstrdup("local-mac-address", GFP_KERNEL); 137 if (newmac->name == NULL) { 138 kfree(newmac); 139 return; 140 } 141 142 memcpy(newmac->value, macaddr, MAC_LEN); 143 ((u8*)newmac->value)[5] = (*(u32*)DIP_SWITCHES_VADDR) & 0x3f; 144 of_update_property(node, newmac); 145 } 146 147 static int __init machine_setup(void) 148 { 149 struct device_node *eth = NULL; 150 151 if ((eth = of_find_compatible_node(eth, NULL, "opencores,ethoc"))) 152 update_local_mac(eth); 153 return 0; 154 } 155 arch_initcall(machine_setup); 156 157 #endif 158 159 /* early initialization */ 160 161 void __init platform_init(bp_tag_t *first) 162 { 163 } 164 165 /* Heartbeat. */ 166 167 void platform_heartbeat(void) 168 { 169 } 170 171 #ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 172 173 void __init platform_calibrate_ccount(void) 174 { 175 long clk_freq = 0; 176 #ifdef CONFIG_OF 177 struct device_node *cpu = 178 of_find_compatible_node(NULL, NULL, "cdns,xtensa-cpu"); 179 if (cpu) { 180 u32 freq; 181 update_clock_frequency(cpu); 182 if (!of_property_read_u32(cpu, "clock-frequency", &freq)) 183 clk_freq = freq; 184 } 185 #endif 186 if (!clk_freq) 187 clk_freq = *(long *)XTFPGA_CLKFRQ_VADDR; 188 189 ccount_freq = clk_freq; 190 } 191 192 #endif 193 194 #ifndef CONFIG_OF 195 196 #include <linux/serial_8250.h> 197 #include <linux/if.h> 198 #include <net/ethoc.h> 199 #include <linux/usb/c67x00.h> 200 201 /*---------------------------------------------------------------------------- 202 * Ethernet -- OpenCores Ethernet MAC (ethoc driver) 203 */ 204 205 static struct resource ethoc_res[] = { 206 [0] = { /* register space */ 207 .start = OETH_REGS_PADDR, 208 .end = OETH_REGS_PADDR + OETH_REGS_SIZE - 1, 209 .flags = IORESOURCE_MEM, 210 }, 211 [1] = { /* buffer space */ 212 .start = OETH_SRAMBUFF_PADDR, 213 .end = OETH_SRAMBUFF_PADDR + OETH_SRAMBUFF_SIZE - 1, 214 .flags = IORESOURCE_MEM, 215 }, 216 [2] = { /* IRQ number */ 217 .start = OETH_IRQ, 218 .end = OETH_IRQ, 219 .flags = IORESOURCE_IRQ, 220 }, 221 }; 222 223 static struct ethoc_platform_data ethoc_pdata = { 224 /* 225 * The MAC address for these boards is 00:50:c2:13:6f:xx. 226 * The last byte (here as zero) is read from the DIP switches on the 227 * board. 228 */ 229 .hwaddr = { 0x00, 0x50, 0xc2, 0x13, 0x6f, 0 }, 230 .phy_id = -1, 231 .big_endian = XCHAL_HAVE_BE, 232 }; 233 234 static struct platform_device ethoc_device = { 235 .name = "ethoc", 236 .id = -1, 237 .num_resources = ARRAY_SIZE(ethoc_res), 238 .resource = ethoc_res, 239 .dev = { 240 .platform_data = ðoc_pdata, 241 }, 242 }; 243 244 /*---------------------------------------------------------------------------- 245 * USB Host/Device -- Cypress CY7C67300 246 */ 247 248 static struct resource c67x00_res[] = { 249 [0] = { /* register space */ 250 .start = C67X00_PADDR, 251 .end = C67X00_PADDR + C67X00_SIZE - 1, 252 .flags = IORESOURCE_MEM, 253 }, 254 [1] = { /* IRQ number */ 255 .start = C67X00_IRQ, 256 .end = C67X00_IRQ, 257 .flags = IORESOURCE_IRQ, 258 }, 259 }; 260 261 static struct c67x00_platform_data c67x00_pdata = { 262 .sie_config = C67X00_SIE1_HOST | C67X00_SIE2_UNUSED, 263 .hpi_regstep = 4, 264 }; 265 266 static struct platform_device c67x00_device = { 267 .name = "c67x00", 268 .id = -1, 269 .num_resources = ARRAY_SIZE(c67x00_res), 270 .resource = c67x00_res, 271 .dev = { 272 .platform_data = &c67x00_pdata, 273 }, 274 }; 275 276 /*---------------------------------------------------------------------------- 277 * UART 278 */ 279 280 static struct resource serial_resource = { 281 .start = DUART16552_PADDR, 282 .end = DUART16552_PADDR + 0x1f, 283 .flags = IORESOURCE_MEM, 284 }; 285 286 static struct plat_serial8250_port serial_platform_data[] = { 287 [0] = { 288 .mapbase = DUART16552_PADDR, 289 .irq = DUART16552_INTNUM, 290 .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | 291 UPF_IOREMAP, 292 .iotype = XCHAL_HAVE_BE ? UPIO_MEM32BE : UPIO_MEM32, 293 .regshift = 2, 294 .uartclk = 0, /* set in xtavnet_init() */ 295 }, 296 { }, 297 }; 298 299 static struct platform_device xtavnet_uart = { 300 .name = "serial8250", 301 .id = PLAT8250_DEV_PLATFORM, 302 .dev = { 303 .platform_data = serial_platform_data, 304 }, 305 .num_resources = 1, 306 .resource = &serial_resource, 307 }; 308 309 /* platform devices */ 310 static struct platform_device *platform_devices[] __initdata = { 311 ðoc_device, 312 &c67x00_device, 313 &xtavnet_uart, 314 }; 315 316 317 static int __init xtavnet_init(void) 318 { 319 /* Ethernet MAC address. */ 320 ethoc_pdata.hwaddr[5] = *(u32 *)DIP_SWITCHES_VADDR; 321 322 /* Clock rate varies among FPGA bitstreams; board specific FPGA register 323 * reports the actual clock rate. 324 */ 325 serial_platform_data[0].uartclk = *(long *)XTFPGA_CLKFRQ_VADDR; 326 327 328 /* register platform devices */ 329 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 330 331 /* ETHOC driver is a bit quiet; at least display Ethernet MAC, so user 332 * knows whether they set it correctly on the DIP switches. 333 */ 334 pr_info("XTFPGA: Ethernet MAC %pM\n", ethoc_pdata.hwaddr); 335 ethoc_pdata.eth_clkfreq = *(long *)XTFPGA_CLKFRQ_VADDR; 336 337 return 0; 338 } 339 340 /* 341 * Register to be done during do_initcalls(). 342 */ 343 arch_initcall(xtavnet_init); 344 345 #endif /* CONFIG_OF */ 346