1 /* 2 * arch/xtensa/mm/tlb.c 3 * 4 * Logic that manipulates the Xtensa MMU. Derived from MIPS. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 2001 - 2003 Tensilica Inc. 11 * 12 * Joe Taylor 13 * Chris Zankel <chris@zankel.net> 14 * Marc Gauthier 15 */ 16 17 #include <linux/mm.h> 18 #include <asm/processor.h> 19 #include <asm/mmu_context.h> 20 #include <asm/tlbflush.h> 21 #include <asm/cacheflush.h> 22 23 24 static inline void __flush_itlb_all (void) 25 { 26 int w, i; 27 28 for (w = 0; w < ITLB_ARF_WAYS; w++) { 29 for (i = 0; i < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); i++) { 30 int e = w + (i << PAGE_SHIFT); 31 invalidate_itlb_entry_no_isync(e); 32 } 33 } 34 asm volatile ("isync\n"); 35 } 36 37 static inline void __flush_dtlb_all (void) 38 { 39 int w, i; 40 41 for (w = 0; w < DTLB_ARF_WAYS; w++) { 42 for (i = 0; i < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); i++) { 43 int e = w + (i << PAGE_SHIFT); 44 invalidate_dtlb_entry_no_isync(e); 45 } 46 } 47 asm volatile ("isync\n"); 48 } 49 50 51 void local_flush_tlb_all(void) 52 { 53 __flush_itlb_all(); 54 __flush_dtlb_all(); 55 } 56 57 /* If mm is current, we simply assign the current task a new ASID, thus, 58 * invalidating all previous tlb entries. If mm is someone else's user mapping, 59 * wie invalidate the context, thus, when that user mapping is swapped in, 60 * a new context will be assigned to it. 61 */ 62 63 void local_flush_tlb_mm(struct mm_struct *mm) 64 { 65 int cpu = smp_processor_id(); 66 67 if (mm == current->active_mm) { 68 unsigned long flags; 69 local_irq_save(flags); 70 mm->context.asid[cpu] = NO_CONTEXT; 71 activate_context(mm, cpu); 72 local_irq_restore(flags); 73 } else { 74 mm->context.asid[cpu] = NO_CONTEXT; 75 mm->context.cpu = -1; 76 } 77 } 78 79 80 #define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2) 81 #define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2) 82 #if _ITLB_ENTRIES > _DTLB_ENTRIES 83 # define _TLB_ENTRIES _ITLB_ENTRIES 84 #else 85 # define _TLB_ENTRIES _DTLB_ENTRIES 86 #endif 87 88 void local_flush_tlb_range(struct vm_area_struct *vma, 89 unsigned long start, unsigned long end) 90 { 91 int cpu = smp_processor_id(); 92 struct mm_struct *mm = vma->vm_mm; 93 unsigned long flags; 94 95 if (mm->context.asid[cpu] == NO_CONTEXT) 96 return; 97 98 #if 0 99 printk("[tlbrange<%02lx,%08lx,%08lx>]\n", 100 (unsigned long)mm->context.asid[cpu], start, end); 101 #endif 102 local_irq_save(flags); 103 104 if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) { 105 int oldpid = get_rasid_register(); 106 107 set_rasid_register(ASID_INSERT(mm->context.asid[cpu])); 108 start &= PAGE_MASK; 109 if (vma->vm_flags & VM_EXEC) 110 while(start < end) { 111 invalidate_itlb_mapping(start); 112 invalidate_dtlb_mapping(start); 113 start += PAGE_SIZE; 114 } 115 else 116 while(start < end) { 117 invalidate_dtlb_mapping(start); 118 start += PAGE_SIZE; 119 } 120 121 set_rasid_register(oldpid); 122 } else { 123 local_flush_tlb_mm(mm); 124 } 125 local_irq_restore(flags); 126 } 127 128 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long page) 129 { 130 int cpu = smp_processor_id(); 131 struct mm_struct* mm = vma->vm_mm; 132 unsigned long flags; 133 int oldpid; 134 135 if (mm->context.asid[cpu] == NO_CONTEXT) 136 return; 137 138 local_irq_save(flags); 139 140 oldpid = get_rasid_register(); 141 set_rasid_register(ASID_INSERT(mm->context.asid[cpu])); 142 143 if (vma->vm_flags & VM_EXEC) 144 invalidate_itlb_mapping(page); 145 invalidate_dtlb_mapping(page); 146 147 set_rasid_register(oldpid); 148 149 local_irq_restore(flags); 150 } 151 152 #ifdef CONFIG_DEBUG_TLB_SANITY 153 154 static unsigned get_pte_for_vaddr(unsigned vaddr) 155 { 156 struct task_struct *task = get_current(); 157 struct mm_struct *mm = task->mm; 158 pgd_t *pgd; 159 pmd_t *pmd; 160 pte_t *pte; 161 162 if (!mm) 163 mm = task->active_mm; 164 pgd = pgd_offset(mm, vaddr); 165 if (pgd_none_or_clear_bad(pgd)) 166 return 0; 167 pmd = pmd_offset(pgd, vaddr); 168 if (pmd_none_or_clear_bad(pmd)) 169 return 0; 170 pte = pte_offset_map(pmd, vaddr); 171 if (!pte) 172 return 0; 173 return pte_val(*pte); 174 } 175 176 enum { 177 TLB_SUSPICIOUS = 1, 178 TLB_INSANE = 2, 179 }; 180 181 static void tlb_insane(void) 182 { 183 BUG_ON(1); 184 } 185 186 static void tlb_suspicious(void) 187 { 188 WARN_ON(1); 189 } 190 191 /* 192 * Check that TLB entries with kernel ASID (1) have kernel VMA (>= TASK_SIZE), 193 * and TLB entries with user ASID (>=4) have VMA < TASK_SIZE. 194 * 195 * Check that valid TLB entries either have the same PA as the PTE, or PTE is 196 * marked as non-present. Non-present PTE and the page with non-zero refcount 197 * and zero mapcount is normal for batched TLB flush operation. Zero refcount 198 * means that the page was freed prematurely. Non-zero mapcount is unusual, 199 * but does not necessary means an error, thus marked as suspicious. 200 */ 201 static int check_tlb_entry(unsigned w, unsigned e, bool dtlb) 202 { 203 unsigned tlbidx = w | (e << PAGE_SHIFT); 204 unsigned r0 = dtlb ? 205 read_dtlb_virtual(tlbidx) : read_itlb_virtual(tlbidx); 206 unsigned vpn = (r0 & PAGE_MASK) | (e << PAGE_SHIFT); 207 unsigned pte = get_pte_for_vaddr(vpn); 208 unsigned mm_asid = (get_rasid_register() >> 8) & ASID_MASK; 209 unsigned tlb_asid = r0 & ASID_MASK; 210 bool kernel = tlb_asid == 1; 211 int rc = 0; 212 213 if (tlb_asid > 0 && ((vpn < TASK_SIZE) == kernel)) { 214 pr_err("%cTLB: way: %u, entry: %u, VPN %08x in %s PTE\n", 215 dtlb ? 'D' : 'I', w, e, vpn, 216 kernel ? "kernel" : "user"); 217 rc |= TLB_INSANE; 218 } 219 220 if (tlb_asid == mm_asid) { 221 unsigned r1 = dtlb ? read_dtlb_translation(tlbidx) : 222 read_itlb_translation(tlbidx); 223 if ((pte ^ r1) & PAGE_MASK) { 224 pr_err("%cTLB: way: %u, entry: %u, mapping: %08x->%08x, PTE: %08x\n", 225 dtlb ? 'D' : 'I', w, e, r0, r1, pte); 226 if (pte == 0 || !pte_present(__pte(pte))) { 227 struct page *p = pfn_to_page(r1 >> PAGE_SHIFT); 228 pr_err("page refcount: %d, mapcount: %d\n", 229 page_count(p), 230 page_mapcount(p)); 231 if (!page_count(p)) 232 rc |= TLB_INSANE; 233 else if (page_mapped(p)) 234 rc |= TLB_SUSPICIOUS; 235 } else { 236 rc |= TLB_INSANE; 237 } 238 } 239 } 240 return rc; 241 } 242 243 void check_tlb_sanity(void) 244 { 245 unsigned long flags; 246 unsigned w, e; 247 int bug = 0; 248 249 local_irq_save(flags); 250 for (w = 0; w < DTLB_ARF_WAYS; ++w) 251 for (e = 0; e < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); ++e) 252 bug |= check_tlb_entry(w, e, true); 253 for (w = 0; w < ITLB_ARF_WAYS; ++w) 254 for (e = 0; e < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); ++e) 255 bug |= check_tlb_entry(w, e, false); 256 if (bug & TLB_INSANE) 257 tlb_insane(); 258 if (bug & TLB_SUSPICIOUS) 259 tlb_suspicious(); 260 local_irq_restore(flags); 261 } 262 263 #endif /* CONFIG_DEBUG_TLB_SANITY */ 264