1 /* 2 * xtensa mmu stuff 3 * 4 * Extracted from init.c 5 */ 6 #include <linux/percpu.h> 7 #include <linux/init.h> 8 #include <linux/string.h> 9 #include <linux/slab.h> 10 #include <linux/cache.h> 11 12 #include <asm/tlb.h> 13 #include <asm/tlbflush.h> 14 #include <asm/mmu_context.h> 15 #include <asm/page.h> 16 17 void __init paging_init(void) 18 { 19 memset(swapper_pg_dir, 0, PAGE_SIZE); 20 } 21 22 /* 23 * Flush the mmu and reset associated register to default values. 24 */ 25 void __init init_mmu(void) 26 { 27 /* Writing zeros to the <t>TLBCFG special registers ensure 28 * that valid values exist in the register. For existing 29 * PGSZID<w> fields, zero selects the first element of the 30 * page-size array. For nonexistent PGSZID<w> fields, zero is 31 * the best value to write. Also, when changing PGSZID<w> 32 * fields, the corresponding TLB must be flushed. 33 */ 34 set_itlbcfg_register(0); 35 set_dtlbcfg_register(0); 36 flush_tlb_all(); 37 38 /* Set rasid register to a known value. */ 39 40 set_rasid_register(ASID_USER_FIRST); 41 42 /* Set PTEVADDR special register to the start of the page 43 * table, which is in kernel mappable space (ie. not 44 * statically mapped). This register's value is undefined on 45 * reset. 46 */ 47 set_ptevaddr_register(PGTABLE_START); 48 } 49 50 struct kmem_cache *pgtable_cache __read_mostly; 51 52 static void pgd_ctor(void *addr) 53 { 54 pte_t *ptep = (pte_t *)addr; 55 int i; 56 57 for (i = 0; i < 1024; i++, ptep++) 58 pte_clear(NULL, 0, ptep); 59 60 } 61 62 void __init pgtable_cache_init(void) 63 { 64 pgtable_cache = kmem_cache_create("pgd", 65 PAGE_SIZE, PAGE_SIZE, 66 SLAB_HWCACHE_ALIGN, 67 pgd_ctor); 68 } 69