xref: /openbmc/linux/arch/xtensa/kernel/setup.c (revision 8a10bc9d) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  *
11  * Chris Zankel	<chris@zankel.net>
12  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
13  * Kevin Chea
14  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
15  */
16 
17 #include <linux/errno.h>
18 #include <linux/init.h>
19 #include <linux/mm.h>
20 #include <linux/proc_fs.h>
21 #include <linux/screen_info.h>
22 #include <linux/bootmem.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/cpu.h>
26 #include <linux/of_fdt.h>
27 #include <linux/of_platform.h>
28 
29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
30 # include <linux/console.h>
31 #endif
32 
33 #ifdef CONFIG_RTC
34 # include <linux/timex.h>
35 #endif
36 
37 #ifdef CONFIG_PROC_FS
38 # include <linux/seq_file.h>
39 #endif
40 
41 #include <asm/bootparam.h>
42 #include <asm/mmu_context.h>
43 #include <asm/pgtable.h>
44 #include <asm/processor.h>
45 #include <asm/timex.h>
46 #include <asm/platform.h>
47 #include <asm/page.h>
48 #include <asm/setup.h>
49 #include <asm/param.h>
50 #include <asm/traps.h>
51 #include <asm/smp.h>
52 
53 #include <platform/hardware.h>
54 
55 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
56 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
57 #endif
58 
59 #ifdef CONFIG_BLK_DEV_FD
60 extern struct fd_ops no_fd_ops;
61 struct fd_ops *fd_ops;
62 #endif
63 
64 extern struct rtc_ops no_rtc_ops;
65 struct rtc_ops *rtc_ops;
66 
67 #ifdef CONFIG_BLK_DEV_INITRD
68 extern unsigned long initrd_start;
69 extern unsigned long initrd_end;
70 int initrd_is_mapped = 0;
71 extern int initrd_below_start_ok;
72 #endif
73 
74 #ifdef CONFIG_OF
75 extern u32 __dtb_start[];
76 void *dtb_start = __dtb_start;
77 #endif
78 
79 unsigned char aux_device_present;
80 extern unsigned long loops_per_jiffy;
81 
82 /* Command line specified as configuration option. */
83 
84 static char __initdata command_line[COMMAND_LINE_SIZE];
85 
86 #ifdef CONFIG_CMDLINE_BOOL
87 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
88 #endif
89 
90 sysmem_info_t __initdata sysmem;
91 
92 extern int mem_reserve(unsigned long, unsigned long, int);
93 extern void bootmem_init(void);
94 extern void zones_init(void);
95 
96 /*
97  * Boot parameter parsing.
98  *
99  * The Xtensa port uses a list of variable-sized tags to pass data to
100  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
101  * to be recognised. The list is terminated with a zero-sized
102  * BP_TAG_LAST tag.
103  */
104 
105 typedef struct tagtable {
106 	u32 tag;
107 	int (*parse)(const bp_tag_t*);
108 } tagtable_t;
109 
110 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
111 	__attribute__((used, section(".taglist"))) = { tag, fn }
112 
113 /* parse current tag */
114 
115 static int __init add_sysmem_bank(unsigned long type, unsigned long start,
116 		unsigned long end)
117 {
118 	if (sysmem.nr_banks >= SYSMEM_BANKS_MAX) {
119 		printk(KERN_WARNING
120 				"Ignoring memory bank 0x%08lx size %ldKB\n",
121 				start, end - start);
122 		return -EINVAL;
123 	}
124 	sysmem.bank[sysmem.nr_banks].type  = type;
125 	sysmem.bank[sysmem.nr_banks].start = PAGE_ALIGN(start);
126 	sysmem.bank[sysmem.nr_banks].end   = end & PAGE_MASK;
127 	sysmem.nr_banks++;
128 
129 	return 0;
130 }
131 
132 static int __init parse_tag_mem(const bp_tag_t *tag)
133 {
134 	meminfo_t *mi = (meminfo_t *)(tag->data);
135 
136 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
137 		return -1;
138 
139 	return add_sysmem_bank(mi->type, mi->start, mi->end);
140 }
141 
142 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
143 
144 #ifdef CONFIG_BLK_DEV_INITRD
145 
146 static int __init parse_tag_initrd(const bp_tag_t* tag)
147 {
148 	meminfo_t* mi;
149 	mi = (meminfo_t*)(tag->data);
150 	initrd_start = (unsigned long)__va(mi->start);
151 	initrd_end = (unsigned long)__va(mi->end);
152 
153 	return 0;
154 }
155 
156 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
157 
158 #ifdef CONFIG_OF
159 
160 static int __init parse_tag_fdt(const bp_tag_t *tag)
161 {
162 	dtb_start = __va(tag->data[0]);
163 	return 0;
164 }
165 
166 __tagtable(BP_TAG_FDT, parse_tag_fdt);
167 
168 #endif /* CONFIG_OF */
169 
170 #endif /* CONFIG_BLK_DEV_INITRD */
171 
172 static int __init parse_tag_cmdline(const bp_tag_t* tag)
173 {
174 	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
175 	return 0;
176 }
177 
178 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
179 
180 static int __init parse_bootparam(const bp_tag_t* tag)
181 {
182 	extern tagtable_t __tagtable_begin, __tagtable_end;
183 	tagtable_t *t;
184 
185 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
186 
187 	if (tag->id != BP_TAG_FIRST) {
188 		printk(KERN_WARNING "Invalid boot parameters!\n");
189 		return 0;
190 	}
191 
192 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
193 
194 	/* Parse all tags. */
195 
196 	while (tag != NULL && tag->id != BP_TAG_LAST) {
197 	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
198 			if (tag->id == t->tag) {
199 				t->parse(tag);
200 				break;
201 			}
202 		}
203 		if (t == &__tagtable_end)
204 			printk(KERN_WARNING "Ignoring tag "
205 			       "0x%08x\n", tag->id);
206 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
207 	}
208 
209 	return 0;
210 }
211 
212 #ifdef CONFIG_OF
213 bool __initdata dt_memory_scan = false;
214 
215 #if XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
216 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
217 EXPORT_SYMBOL(xtensa_kio_paddr);
218 
219 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
220 		int depth, void *data)
221 {
222 	const __be32 *ranges;
223 	unsigned long len;
224 
225 	if (depth > 1)
226 		return 0;
227 
228 	if (!of_flat_dt_is_compatible(node, "simple-bus"))
229 		return 0;
230 
231 	ranges = of_get_flat_dt_prop(node, "ranges", &len);
232 	if (!ranges)
233 		return 1;
234 	if (len == 0)
235 		return 1;
236 
237 	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
238 	/* round down to nearest 256MB boundary */
239 	xtensa_kio_paddr &= 0xf0000000;
240 
241 	return 1;
242 }
243 #else
244 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
245 		int depth, void *data)
246 {
247 	return 1;
248 }
249 #endif
250 
251 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
252 {
253 	if (!dt_memory_scan)
254 		return;
255 
256 	size &= PAGE_MASK;
257 	add_sysmem_bank(MEMORY_TYPE_CONVENTIONAL, base, base + size);
258 }
259 
260 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
261 {
262 	return __alloc_bootmem(size, align, 0);
263 }
264 
265 void __init early_init_devtree(void *params)
266 {
267 	if (sysmem.nr_banks == 0)
268 		dt_memory_scan = true;
269 
270 	early_init_dt_scan(params);
271 	of_scan_flat_dt(xtensa_dt_io_area, NULL);
272 
273 	if (!command_line[0])
274 		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
275 }
276 
277 static int __init xtensa_device_probe(void)
278 {
279 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
280 	return 0;
281 }
282 
283 device_initcall(xtensa_device_probe);
284 
285 #endif /* CONFIG_OF */
286 
287 /*
288  * Initialize architecture. (Early stage)
289  */
290 
291 void __init init_arch(bp_tag_t *bp_start)
292 {
293 	sysmem.nr_banks = 0;
294 
295 	/* Parse boot parameters */
296 
297 	if (bp_start)
298 		parse_bootparam(bp_start);
299 
300 #ifdef CONFIG_OF
301 	early_init_devtree(dtb_start);
302 #endif
303 
304 	if (sysmem.nr_banks == 0) {
305 		sysmem.nr_banks = 1;
306 		sysmem.bank[0].start = PLATFORM_DEFAULT_MEM_START;
307 		sysmem.bank[0].end = PLATFORM_DEFAULT_MEM_START
308 				     + PLATFORM_DEFAULT_MEM_SIZE;
309 	}
310 
311 #ifdef CONFIG_CMDLINE_BOOL
312 	if (!command_line[0])
313 		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
314 #endif
315 
316 	/* Early hook for platforms */
317 
318 	platform_init(bp_start);
319 
320 	/* Initialize MMU. */
321 
322 	init_mmu();
323 }
324 
325 /*
326  * Initialize system. Setup memory and reserve regions.
327  */
328 
329 extern char _end;
330 extern char _stext;
331 extern char _WindowVectors_text_start;
332 extern char _WindowVectors_text_end;
333 extern char _DebugInterruptVector_literal_start;
334 extern char _DebugInterruptVector_text_end;
335 extern char _KernelExceptionVector_literal_start;
336 extern char _KernelExceptionVector_text_end;
337 extern char _UserExceptionVector_literal_start;
338 extern char _UserExceptionVector_text_end;
339 extern char _DoubleExceptionVector_literal_start;
340 extern char _DoubleExceptionVector_text_end;
341 #if XCHAL_EXCM_LEVEL >= 2
342 extern char _Level2InterruptVector_text_start;
343 extern char _Level2InterruptVector_text_end;
344 #endif
345 #if XCHAL_EXCM_LEVEL >= 3
346 extern char _Level3InterruptVector_text_start;
347 extern char _Level3InterruptVector_text_end;
348 #endif
349 #if XCHAL_EXCM_LEVEL >= 4
350 extern char _Level4InterruptVector_text_start;
351 extern char _Level4InterruptVector_text_end;
352 #endif
353 #if XCHAL_EXCM_LEVEL >= 5
354 extern char _Level5InterruptVector_text_start;
355 extern char _Level5InterruptVector_text_end;
356 #endif
357 #if XCHAL_EXCM_LEVEL >= 6
358 extern char _Level6InterruptVector_text_start;
359 extern char _Level6InterruptVector_text_end;
360 #endif
361 
362 
363 
364 #ifdef CONFIG_S32C1I_SELFTEST
365 #if XCHAL_HAVE_S32C1I
366 
367 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
368 
369 /*
370  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
371  *
372  * If *v == cmp, set *v = set.  Return previous *v.
373  */
374 static inline int probed_compare_swap(int *v, int cmp, int set)
375 {
376 	int tmp;
377 
378 	__asm__ __volatile__(
379 			"	movi	%1, 1f\n"
380 			"	s32i	%1, %4, 0\n"
381 			"	wsr	%2, scompare1\n"
382 			"1:	s32c1i	%0, %3, 0\n"
383 			: "=a" (set), "=&a" (tmp)
384 			: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
385 			: "memory"
386 			);
387 	return set;
388 }
389 
390 /* Handle probed exception */
391 
392 static void __init do_probed_exception(struct pt_regs *regs,
393 		unsigned long exccause)
394 {
395 	if (regs->pc == rcw_probe_pc) {	/* exception on s32c1i ? */
396 		regs->pc += 3;		/* skip the s32c1i instruction */
397 		rcw_exc = exccause;
398 	} else {
399 		do_unhandled(regs, exccause);
400 	}
401 }
402 
403 /* Simple test of S32C1I (soc bringup assist) */
404 
405 static int __init check_s32c1i(void)
406 {
407 	int n, cause1, cause2;
408 	void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
409 
410 	rcw_probe_pc = 0;
411 	handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
412 			do_probed_exception);
413 	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
414 			do_probed_exception);
415 	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
416 			do_probed_exception);
417 
418 	/* First try an S32C1I that does not store: */
419 	rcw_exc = 0;
420 	rcw_word = 1;
421 	n = probed_compare_swap(&rcw_word, 0, 2);
422 	cause1 = rcw_exc;
423 
424 	/* took exception? */
425 	if (cause1 != 0) {
426 		/* unclean exception? */
427 		if (n != 2 || rcw_word != 1)
428 			panic("S32C1I exception error");
429 	} else if (rcw_word != 1 || n != 1) {
430 		panic("S32C1I compare error");
431 	}
432 
433 	/* Then an S32C1I that stores: */
434 	rcw_exc = 0;
435 	rcw_word = 0x1234567;
436 	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
437 	cause2 = rcw_exc;
438 
439 	if (cause2 != 0) {
440 		/* unclean exception? */
441 		if (n != 0xabcde || rcw_word != 0x1234567)
442 			panic("S32C1I exception error (b)");
443 	} else if (rcw_word != 0xabcde || n != 0x1234567) {
444 		panic("S32C1I store error");
445 	}
446 
447 	/* Verify consistency of exceptions: */
448 	if (cause1 || cause2) {
449 		pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
450 		/* If emulation of S32C1I upon bus error gets implemented,
451 		   we can get rid of this panic for single core (not SMP) */
452 		panic("S32C1I exceptions not currently supported");
453 	}
454 	if (cause1 != cause2)
455 		panic("inconsistent S32C1I exceptions");
456 
457 	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
458 	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
459 	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
460 	return 0;
461 }
462 
463 #else /* XCHAL_HAVE_S32C1I */
464 
465 /* This condition should not occur with a commercially deployed processor.
466    Display reminder for early engr test or demo chips / FPGA bitstreams */
467 static int __init check_s32c1i(void)
468 {
469 	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
470 	return 0;
471 }
472 
473 #endif /* XCHAL_HAVE_S32C1I */
474 early_initcall(check_s32c1i);
475 #endif /* CONFIG_S32C1I_SELFTEST */
476 
477 
478 void __init setup_arch(char **cmdline_p)
479 {
480 	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
481 	*cmdline_p = command_line;
482 
483 	/* Reserve some memory regions */
484 
485 #ifdef CONFIG_BLK_DEV_INITRD
486 	if (initrd_start < initrd_end) {
487 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
488 					       __pa(initrd_end), 0);
489 		initrd_below_start_ok = 1;
490 	} else {
491 		initrd_start = 0;
492 	}
493 #endif
494 
495 	mem_reserve(__pa(&_stext),__pa(&_end), 1);
496 
497 	mem_reserve(__pa(&_WindowVectors_text_start),
498 		    __pa(&_WindowVectors_text_end), 0);
499 
500 	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
501 		    __pa(&_DebugInterruptVector_text_end), 0);
502 
503 	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
504 		    __pa(&_KernelExceptionVector_text_end), 0);
505 
506 	mem_reserve(__pa(&_UserExceptionVector_literal_start),
507 		    __pa(&_UserExceptionVector_text_end), 0);
508 
509 	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
510 		    __pa(&_DoubleExceptionVector_text_end), 0);
511 
512 #if XCHAL_EXCM_LEVEL >= 2
513 	mem_reserve(__pa(&_Level2InterruptVector_text_start),
514 		    __pa(&_Level2InterruptVector_text_end), 0);
515 #endif
516 #if XCHAL_EXCM_LEVEL >= 3
517 	mem_reserve(__pa(&_Level3InterruptVector_text_start),
518 		    __pa(&_Level3InterruptVector_text_end), 0);
519 #endif
520 #if XCHAL_EXCM_LEVEL >= 4
521 	mem_reserve(__pa(&_Level4InterruptVector_text_start),
522 		    __pa(&_Level4InterruptVector_text_end), 0);
523 #endif
524 #if XCHAL_EXCM_LEVEL >= 5
525 	mem_reserve(__pa(&_Level5InterruptVector_text_start),
526 		    __pa(&_Level5InterruptVector_text_end), 0);
527 #endif
528 #if XCHAL_EXCM_LEVEL >= 6
529 	mem_reserve(__pa(&_Level6InterruptVector_text_start),
530 		    __pa(&_Level6InterruptVector_text_end), 0);
531 #endif
532 
533 	bootmem_init();
534 
535 	unflatten_and_copy_device_tree();
536 
537 	platform_setup(cmdline_p);
538 
539 #ifdef CONFIG_SMP
540 	smp_init_cpus();
541 #endif
542 
543 	paging_init();
544 	zones_init();
545 
546 #ifdef CONFIG_VT
547 # if defined(CONFIG_VGA_CONSOLE)
548 	conswitchp = &vga_con;
549 # elif defined(CONFIG_DUMMY_CONSOLE)
550 	conswitchp = &dummy_con;
551 # endif
552 #endif
553 
554 #ifdef CONFIG_PCI
555 	platform_pcibios_init();
556 #endif
557 }
558 
559 static DEFINE_PER_CPU(struct cpu, cpu_data);
560 
561 static int __init topology_init(void)
562 {
563 	int i;
564 
565 	for_each_possible_cpu(i) {
566 		struct cpu *cpu = &per_cpu(cpu_data, i);
567 		cpu->hotpluggable = !!i;
568 		register_cpu(cpu, i);
569 	}
570 
571 	return 0;
572 }
573 subsys_initcall(topology_init);
574 
575 void machine_restart(char * cmd)
576 {
577 	platform_restart();
578 }
579 
580 void machine_halt(void)
581 {
582 	platform_halt();
583 	while (1);
584 }
585 
586 void machine_power_off(void)
587 {
588 	platform_power_off();
589 	while (1);
590 }
591 #ifdef CONFIG_PROC_FS
592 
593 /*
594  * Display some core information through /proc/cpuinfo.
595  */
596 
597 static int
598 c_show(struct seq_file *f, void *slot)
599 {
600 	char buf[NR_CPUS * 5];
601 
602 	cpulist_scnprintf(buf, sizeof(buf), cpu_online_mask);
603 	/* high-level stuff */
604 	seq_printf(f, "CPU count\t: %u\n"
605 		      "CPU list\t: %s\n"
606 		      "vendor_id\t: Tensilica\n"
607 		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
608 		      "core ID\t\t: " XCHAL_CORE_ID "\n"
609 		      "build ID\t: 0x%x\n"
610 		      "byte order\t: %s\n"
611 		      "cpu MHz\t\t: %lu.%02lu\n"
612 		      "bogomips\t: %lu.%02lu\n",
613 		      num_online_cpus(),
614 		      buf,
615 		      XCHAL_BUILD_UNIQUE_ID,
616 		      XCHAL_HAVE_BE ?  "big" : "little",
617 		      ccount_freq/1000000,
618 		      (ccount_freq/10000) % 100,
619 		      loops_per_jiffy/(500000/HZ),
620 		      (loops_per_jiffy/(5000/HZ)) % 100);
621 
622 	seq_printf(f,"flags\t\t: "
623 #if XCHAL_HAVE_NMI
624 		     "nmi "
625 #endif
626 #if XCHAL_HAVE_DEBUG
627 		     "debug "
628 # if XCHAL_HAVE_OCD
629 		     "ocd "
630 # endif
631 #endif
632 #if XCHAL_HAVE_DENSITY
633 	    	     "density "
634 #endif
635 #if XCHAL_HAVE_BOOLEANS
636 		     "boolean "
637 #endif
638 #if XCHAL_HAVE_LOOPS
639 		     "loop "
640 #endif
641 #if XCHAL_HAVE_NSA
642 		     "nsa "
643 #endif
644 #if XCHAL_HAVE_MINMAX
645 		     "minmax "
646 #endif
647 #if XCHAL_HAVE_SEXT
648 		     "sext "
649 #endif
650 #if XCHAL_HAVE_CLAMPS
651 		     "clamps "
652 #endif
653 #if XCHAL_HAVE_MAC16
654 		     "mac16 "
655 #endif
656 #if XCHAL_HAVE_MUL16
657 		     "mul16 "
658 #endif
659 #if XCHAL_HAVE_MUL32
660 		     "mul32 "
661 #endif
662 #if XCHAL_HAVE_MUL32_HIGH
663 		     "mul32h "
664 #endif
665 #if XCHAL_HAVE_FP
666 		     "fpu "
667 #endif
668 #if XCHAL_HAVE_S32C1I
669 		     "s32c1i "
670 #endif
671 		     "\n");
672 
673 	/* Registers. */
674 	seq_printf(f,"physical aregs\t: %d\n"
675 		     "misc regs\t: %d\n"
676 		     "ibreak\t\t: %d\n"
677 		     "dbreak\t\t: %d\n",
678 		     XCHAL_NUM_AREGS,
679 		     XCHAL_NUM_MISC_REGS,
680 		     XCHAL_NUM_IBREAK,
681 		     XCHAL_NUM_DBREAK);
682 
683 
684 	/* Interrupt. */
685 	seq_printf(f,"num ints\t: %d\n"
686 		     "ext ints\t: %d\n"
687 		     "int levels\t: %d\n"
688 		     "timers\t\t: %d\n"
689 		     "debug level\t: %d\n",
690 		     XCHAL_NUM_INTERRUPTS,
691 		     XCHAL_NUM_EXTINTERRUPTS,
692 		     XCHAL_NUM_INTLEVELS,
693 		     XCHAL_NUM_TIMERS,
694 		     XCHAL_DEBUGLEVEL);
695 
696 	/* Cache */
697 	seq_printf(f,"icache line size: %d\n"
698 		     "icache ways\t: %d\n"
699 		     "icache size\t: %d\n"
700 		     "icache flags\t: "
701 #if XCHAL_ICACHE_LINE_LOCKABLE
702 		     "lock "
703 #endif
704 		     "\n"
705 		     "dcache line size: %d\n"
706 		     "dcache ways\t: %d\n"
707 		     "dcache size\t: %d\n"
708 		     "dcache flags\t: "
709 #if XCHAL_DCACHE_IS_WRITEBACK
710 		     "writeback "
711 #endif
712 #if XCHAL_DCACHE_LINE_LOCKABLE
713 		     "lock "
714 #endif
715 		     "\n",
716 		     XCHAL_ICACHE_LINESIZE,
717 		     XCHAL_ICACHE_WAYS,
718 		     XCHAL_ICACHE_SIZE,
719 		     XCHAL_DCACHE_LINESIZE,
720 		     XCHAL_DCACHE_WAYS,
721 		     XCHAL_DCACHE_SIZE);
722 
723 	return 0;
724 }
725 
726 /*
727  * We show only CPU #0 info.
728  */
729 static void *
730 c_start(struct seq_file *f, loff_t *pos)
731 {
732 	return (*pos == 0) ? (void *)1 : NULL;
733 }
734 
735 static void *
736 c_next(struct seq_file *f, void *v, loff_t *pos)
737 {
738 	return NULL;
739 }
740 
741 static void
742 c_stop(struct seq_file *f, void *v)
743 {
744 }
745 
746 const struct seq_operations cpuinfo_op =
747 {
748 	.start	= c_start,
749 	.next	= c_next,
750 	.stop	= c_stop,
751 	.show	= c_show,
752 };
753 
754 #endif /* CONFIG_PROC_FS */
755