xref: /openbmc/linux/arch/xtensa/kernel/setup.c (revision 7561dfbf) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  * Copyright (C) 2014 - 2016  Cadence Design Systems Inc.
11  *
12  * Chris Zankel	<chris@zankel.net>
13  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
14  * Kevin Chea
15  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16  */
17 
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/kernel.h>
24 #include <linux/percpu.h>
25 #include <linux/reboot.h>
26 #include <linux/cpu.h>
27 #include <linux/of.h>
28 #include <linux/of_fdt.h>
29 
30 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
31 # include <linux/console.h>
32 #endif
33 
34 #ifdef CONFIG_PROC_FS
35 # include <linux/seq_file.h>
36 #endif
37 
38 #include <asm/bootparam.h>
39 #include <asm/kasan.h>
40 #include <asm/mmu_context.h>
41 #include <asm/page.h>
42 #include <asm/param.h>
43 #include <asm/platform.h>
44 #include <asm/processor.h>
45 #include <asm/sections.h>
46 #include <asm/setup.h>
47 #include <asm/smp.h>
48 #include <asm/sysmem.h>
49 #include <asm/timex.h>
50 
51 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
52 struct screen_info screen_info = {
53 	.orig_x = 0,
54 	.orig_y = 24,
55 	.orig_video_cols = 80,
56 	.orig_video_lines = 24,
57 	.orig_video_isVGA = 1,
58 	.orig_video_points = 16,
59 };
60 #endif
61 
62 #ifdef CONFIG_BLK_DEV_INITRD
63 extern unsigned long initrd_start;
64 extern unsigned long initrd_end;
65 extern int initrd_below_start_ok;
66 #endif
67 
68 #ifdef CONFIG_USE_OF
69 void *dtb_start = __dtb_start;
70 #endif
71 
72 extern unsigned long loops_per_jiffy;
73 
74 /* Command line specified as configuration option. */
75 
76 static char __initdata command_line[COMMAND_LINE_SIZE];
77 
78 #ifdef CONFIG_CMDLINE_BOOL
79 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
80 #endif
81 
82 #ifdef CONFIG_PARSE_BOOTPARAM
83 /*
84  * Boot parameter parsing.
85  *
86  * The Xtensa port uses a list of variable-sized tags to pass data to
87  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
88  * to be recognised. The list is terminated with a zero-sized
89  * BP_TAG_LAST tag.
90  */
91 
92 typedef struct tagtable {
93 	u32 tag;
94 	int (*parse)(const bp_tag_t*);
95 } tagtable_t;
96 
97 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
98 	__section(".taglist") __attribute__((used)) = { tag, fn }
99 
100 /* parse current tag */
101 
102 static int __init parse_tag_mem(const bp_tag_t *tag)
103 {
104 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
105 
106 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
107 		return -1;
108 
109 	return memblock_add(mi->start, mi->end - mi->start);
110 }
111 
112 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
113 
114 #ifdef CONFIG_BLK_DEV_INITRD
115 
116 static int __init parse_tag_initrd(const bp_tag_t* tag)
117 {
118 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
119 
120 	initrd_start = (unsigned long)__va(mi->start);
121 	initrd_end = (unsigned long)__va(mi->end);
122 
123 	return 0;
124 }
125 
126 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
127 
128 #endif /* CONFIG_BLK_DEV_INITRD */
129 
130 #ifdef CONFIG_USE_OF
131 
132 static int __init parse_tag_fdt(const bp_tag_t *tag)
133 {
134 	dtb_start = __va(tag->data[0]);
135 	return 0;
136 }
137 
138 __tagtable(BP_TAG_FDT, parse_tag_fdt);
139 
140 #endif /* CONFIG_USE_OF */
141 
142 static int __init parse_tag_cmdline(const bp_tag_t* tag)
143 {
144 	strscpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
145 	return 0;
146 }
147 
148 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
149 
150 static int __init parse_bootparam(const bp_tag_t* tag)
151 {
152 	extern tagtable_t __tagtable_begin, __tagtable_end;
153 	tagtable_t *t;
154 
155 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
156 
157 	if (tag->id != BP_TAG_FIRST) {
158 		pr_warn("Invalid boot parameters!\n");
159 		return 0;
160 	}
161 
162 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
163 
164 	/* Parse all tags. */
165 
166 	while (tag != NULL && tag->id != BP_TAG_LAST) {
167 		for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
168 			if (tag->id == t->tag) {
169 				t->parse(tag);
170 				break;
171 			}
172 		}
173 		if (t == &__tagtable_end)
174 			pr_warn("Ignoring tag 0x%08x\n", tag->id);
175 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
176 	}
177 
178 	return 0;
179 }
180 #else
181 static int __init parse_bootparam(const bp_tag_t *tag)
182 {
183 	pr_info("Ignoring boot parameters at %p\n", tag);
184 	return 0;
185 }
186 #endif
187 
188 #ifdef CONFIG_USE_OF
189 
190 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
191 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
192 EXPORT_SYMBOL(xtensa_kio_paddr);
193 
194 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
195 		int depth, void *data)
196 {
197 	const __be32 *ranges;
198 	int len;
199 
200 	if (depth > 1)
201 		return 0;
202 
203 	if (!of_flat_dt_is_compatible(node, "simple-bus"))
204 		return 0;
205 
206 	ranges = of_get_flat_dt_prop(node, "ranges", &len);
207 	if (!ranges)
208 		return 1;
209 	if (len == 0)
210 		return 1;
211 
212 	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
213 	/* round down to nearest 256MB boundary */
214 	xtensa_kio_paddr &= 0xf0000000;
215 
216 	init_kio();
217 
218 	return 1;
219 }
220 #else
221 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
222 		int depth, void *data)
223 {
224 	return 1;
225 }
226 #endif
227 
228 void __init early_init_devtree(void *params)
229 {
230 	early_init_dt_scan(params);
231 	of_scan_flat_dt(xtensa_dt_io_area, NULL);
232 
233 	if (!command_line[0])
234 		strscpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
235 }
236 
237 #endif /* CONFIG_USE_OF */
238 
239 /*
240  * Initialize architecture. (Early stage)
241  */
242 
243 void __init init_arch(bp_tag_t *bp_start)
244 {
245 	/* Initialize MMU. */
246 
247 	init_mmu();
248 
249 	/* Initialize initial KASAN shadow map */
250 
251 	kasan_early_init();
252 
253 	/* Parse boot parameters */
254 
255 	if (bp_start)
256 		parse_bootparam(bp_start);
257 
258 #ifdef CONFIG_USE_OF
259 	early_init_devtree(dtb_start);
260 #endif
261 
262 #ifdef CONFIG_CMDLINE_BOOL
263 	if (!command_line[0])
264 		strscpy(command_line, default_command_line, COMMAND_LINE_SIZE);
265 #endif
266 
267 	/* Early hook for platforms */
268 
269 	platform_init(bp_start);
270 }
271 
272 /*
273  * Initialize system. Setup memory and reserve regions.
274  */
275 
276 static inline int __init_memblock mem_reserve(unsigned long start,
277 					      unsigned long end)
278 {
279 	return memblock_reserve(start, end - start);
280 }
281 
282 void __init setup_arch(char **cmdline_p)
283 {
284 	pr_info("config ID: %08x:%08x\n",
285 		xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE));
286 	if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 ||
287 	    xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1)
288 		pr_info("built for config ID: %08x:%08x\n",
289 			XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1);
290 
291 	*cmdline_p = command_line;
292 	platform_setup(cmdline_p);
293 	strscpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE);
294 
295 	/* Reserve some memory regions */
296 
297 #ifdef CONFIG_BLK_DEV_INITRD
298 	if (initrd_start < initrd_end &&
299 	    !mem_reserve(__pa(initrd_start), __pa(initrd_end)))
300 		initrd_below_start_ok = 1;
301 	else
302 		initrd_start = 0;
303 #endif
304 
305 	mem_reserve(__pa(_stext), __pa(_end));
306 #ifdef CONFIG_XIP_KERNEL
307 	mem_reserve(__pa(_xip_start), __pa(_xip_end));
308 #endif
309 
310 #ifdef CONFIG_VECTORS_ADDR
311 #ifdef SUPPORT_WINDOWED
312 	mem_reserve(__pa(_WindowVectors_text_start),
313 		    __pa(_WindowVectors_text_end));
314 #endif
315 
316 	mem_reserve(__pa(_DebugInterruptVector_text_start),
317 		    __pa(_DebugInterruptVector_text_end));
318 
319 	mem_reserve(__pa(_KernelExceptionVector_text_start),
320 		    __pa(_KernelExceptionVector_text_end));
321 
322 	mem_reserve(__pa(_UserExceptionVector_text_start),
323 		    __pa(_UserExceptionVector_text_end));
324 
325 	mem_reserve(__pa(_DoubleExceptionVector_text_start),
326 		    __pa(_DoubleExceptionVector_text_end));
327 
328 	mem_reserve(__pa(_exception_text_start),
329 		    __pa(_exception_text_end));
330 #if XCHAL_EXCM_LEVEL >= 2
331 	mem_reserve(__pa(_Level2InterruptVector_text_start),
332 		    __pa(_Level2InterruptVector_text_end));
333 #endif
334 #if XCHAL_EXCM_LEVEL >= 3
335 	mem_reserve(__pa(_Level3InterruptVector_text_start),
336 		    __pa(_Level3InterruptVector_text_end));
337 #endif
338 #if XCHAL_EXCM_LEVEL >= 4
339 	mem_reserve(__pa(_Level4InterruptVector_text_start),
340 		    __pa(_Level4InterruptVector_text_end));
341 #endif
342 #if XCHAL_EXCM_LEVEL >= 5
343 	mem_reserve(__pa(_Level5InterruptVector_text_start),
344 		    __pa(_Level5InterruptVector_text_end));
345 #endif
346 #if XCHAL_EXCM_LEVEL >= 6
347 	mem_reserve(__pa(_Level6InterruptVector_text_start),
348 		    __pa(_Level6InterruptVector_text_end));
349 #endif
350 
351 #endif /* CONFIG_VECTORS_ADDR */
352 
353 #ifdef CONFIG_SECONDARY_RESET_VECTOR
354 	mem_reserve(__pa(_SecondaryResetVector_text_start),
355 		    __pa(_SecondaryResetVector_text_end));
356 #endif
357 	parse_early_param();
358 	bootmem_init();
359 	kasan_init();
360 	unflatten_and_copy_device_tree();
361 
362 #ifdef CONFIG_SMP
363 	smp_init_cpus();
364 #endif
365 
366 	paging_init();
367 	zones_init();
368 
369 #ifdef CONFIG_VT
370 # if defined(CONFIG_VGA_CONSOLE)
371 	conswitchp = &vga_con;
372 # endif
373 #endif
374 }
375 
376 static DEFINE_PER_CPU(struct cpu, cpu_data);
377 
378 static int __init topology_init(void)
379 {
380 	int i;
381 
382 	for_each_possible_cpu(i) {
383 		struct cpu *cpu = &per_cpu(cpu_data, i);
384 		cpu->hotpluggable = !!i;
385 		register_cpu(cpu, i);
386 	}
387 
388 	return 0;
389 }
390 subsys_initcall(topology_init);
391 
392 void cpu_reset(void)
393 {
394 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU)
395 	local_irq_disable();
396 	/*
397 	 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must
398 	 * be flushed.
399 	 * Way 4 is not currently used by linux.
400 	 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired.
401 	 * Way 5 shall be flushed and way 6 shall be set to identity mapping
402 	 * on MMUv3.
403 	 */
404 	local_flush_tlb_all();
405 	invalidate_page_directory();
406 #if XCHAL_HAVE_SPANNING_WAY
407 	/* MMU v3 */
408 	{
409 		unsigned long vaddr = (unsigned long)cpu_reset;
410 		unsigned long paddr = __pa(vaddr);
411 		unsigned long tmpaddr = vaddr + SZ_512M;
412 		unsigned long tmp0, tmp1, tmp2, tmp3;
413 
414 		/*
415 		 * Find a place for the temporary mapping. It must not be
416 		 * in the same 512MB region with vaddr or paddr, otherwise
417 		 * there may be multihit exception either on entry to the
418 		 * temporary mapping, or on entry to the identity mapping.
419 		 * (512MB is the biggest page size supported by TLB.)
420 		 */
421 		while (((tmpaddr ^ paddr) & -SZ_512M) == 0)
422 			tmpaddr += SZ_512M;
423 
424 		/* Invalidate mapping in the selected temporary area */
425 		if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT))
426 			invalidate_itlb_entry(itlb_probe(tmpaddr));
427 		if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT))
428 			invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE));
429 
430 		/*
431 		 * Map two consecutive pages starting at the physical address
432 		 * of this function to the temporary mapping area.
433 		 */
434 		write_itlb_entry(__pte((paddr & PAGE_MASK) |
435 				       _PAGE_HW_VALID |
436 				       _PAGE_HW_EXEC |
437 				       _PAGE_CA_BYPASS),
438 				 tmpaddr & PAGE_MASK);
439 		write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) |
440 				       _PAGE_HW_VALID |
441 				       _PAGE_HW_EXEC |
442 				       _PAGE_CA_BYPASS),
443 				 (tmpaddr & PAGE_MASK) + PAGE_SIZE);
444 
445 		/* Reinitialize TLB */
446 		__asm__ __volatile__ ("movi	%0, 1f\n\t"
447 				      "movi	%3, 2f\n\t"
448 				      "add	%0, %0, %4\n\t"
449 				      "add	%3, %3, %5\n\t"
450 				      "jx	%0\n"
451 				      /*
452 				       * No literal, data or stack access
453 				       * below this point
454 				       */
455 				      "1:\n\t"
456 				      /* Initialize *tlbcfg */
457 				      "movi	%0, 0\n\t"
458 				      "wsr	%0, itlbcfg\n\t"
459 				      "wsr	%0, dtlbcfg\n\t"
460 				      /* Invalidate TLB way 5 */
461 				      "movi	%0, 4\n\t"
462 				      "movi	%1, 5\n"
463 				      "1:\n\t"
464 				      "iitlb	%1\n\t"
465 				      "idtlb	%1\n\t"
466 				      "add	%1, %1, %6\n\t"
467 				      "addi	%0, %0, -1\n\t"
468 				      "bnez	%0, 1b\n\t"
469 				      /* Initialize TLB way 6 */
470 				      "movi	%0, 7\n\t"
471 				      "addi	%1, %9, 3\n\t"
472 				      "addi	%2, %9, 6\n"
473 				      "1:\n\t"
474 				      "witlb	%1, %2\n\t"
475 				      "wdtlb	%1, %2\n\t"
476 				      "add	%1, %1, %7\n\t"
477 				      "add	%2, %2, %7\n\t"
478 				      "addi	%0, %0, -1\n\t"
479 				      "bnez	%0, 1b\n\t"
480 				      "isync\n\t"
481 				      /* Jump to identity mapping */
482 				      "jx	%3\n"
483 				      "2:\n\t"
484 				      /* Complete way 6 initialization */
485 				      "witlb	%1, %2\n\t"
486 				      "wdtlb	%1, %2\n\t"
487 				      /* Invalidate temporary mapping */
488 				      "sub	%0, %9, %7\n\t"
489 				      "iitlb	%0\n\t"
490 				      "add	%0, %0, %8\n\t"
491 				      "iitlb	%0"
492 				      : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2),
493 					"=&a"(tmp3)
494 				      : "a"(tmpaddr - vaddr),
495 					"a"(paddr - vaddr),
496 					"a"(SZ_128M), "a"(SZ_512M),
497 					"a"(PAGE_SIZE),
498 					"a"((tmpaddr + SZ_512M) & PAGE_MASK)
499 				      : "memory");
500 	}
501 #endif
502 #endif
503 	__asm__ __volatile__ ("movi	a2, 0\n\t"
504 			      "wsr	a2, icountlevel\n\t"
505 			      "movi	a2, 0\n\t"
506 			      "wsr	a2, icount\n\t"
507 #if XCHAL_NUM_IBREAK > 0
508 			      "wsr	a2, ibreakenable\n\t"
509 #endif
510 #if XCHAL_HAVE_LOOPS
511 			      "wsr	a2, lcount\n\t"
512 #endif
513 			      "movi	a2, 0x1f\n\t"
514 			      "wsr	a2, ps\n\t"
515 			      "isync\n\t"
516 			      "jx	%0\n\t"
517 			      :
518 			      : "a" (XCHAL_RESET_VECTOR_VADDR)
519 			      : "a2");
520 	for (;;)
521 		;
522 }
523 
524 void machine_restart(char * cmd)
525 {
526 	local_irq_disable();
527 	smp_send_stop();
528 	do_kernel_restart(cmd);
529 	pr_err("Reboot failed -- System halted\n");
530 	while (1)
531 		cpu_relax();
532 }
533 
534 void machine_halt(void)
535 {
536 	local_irq_disable();
537 	smp_send_stop();
538 	do_kernel_power_off();
539 	while (1)
540 		cpu_relax();
541 }
542 
543 void machine_power_off(void)
544 {
545 	local_irq_disable();
546 	smp_send_stop();
547 	do_kernel_power_off();
548 	while (1)
549 		cpu_relax();
550 }
551 #ifdef CONFIG_PROC_FS
552 
553 /*
554  * Display some core information through /proc/cpuinfo.
555  */
556 
557 static int
558 c_show(struct seq_file *f, void *slot)
559 {
560 	/* high-level stuff */
561 	seq_printf(f, "CPU count\t: %u\n"
562 		      "CPU list\t: %*pbl\n"
563 		      "vendor_id\t: Tensilica\n"
564 		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
565 		      "core ID\t\t: " XCHAL_CORE_ID "\n"
566 		      "build ID\t: 0x%x\n"
567 		      "config ID\t: %08x:%08x\n"
568 		      "byte order\t: %s\n"
569 		      "cpu MHz\t\t: %lu.%02lu\n"
570 		      "bogomips\t: %lu.%02lu\n",
571 		      num_online_cpus(),
572 		      cpumask_pr_args(cpu_online_mask),
573 		      XCHAL_BUILD_UNIQUE_ID,
574 		      xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE),
575 		      XCHAL_HAVE_BE ?  "big" : "little",
576 		      ccount_freq/1000000,
577 		      (ccount_freq/10000) % 100,
578 		      loops_per_jiffy/(500000/HZ),
579 		      (loops_per_jiffy/(5000/HZ)) % 100);
580 	seq_puts(f, "flags\t\t: "
581 #if XCHAL_HAVE_NMI
582 		     "nmi "
583 #endif
584 #if XCHAL_HAVE_DEBUG
585 		     "debug "
586 # if XCHAL_HAVE_OCD
587 		     "ocd "
588 # endif
589 #endif
590 #if XCHAL_HAVE_DENSITY
591 	    	     "density "
592 #endif
593 #if XCHAL_HAVE_BOOLEANS
594 		     "boolean "
595 #endif
596 #if XCHAL_HAVE_LOOPS
597 		     "loop "
598 #endif
599 #if XCHAL_HAVE_NSA
600 		     "nsa "
601 #endif
602 #if XCHAL_HAVE_MINMAX
603 		     "minmax "
604 #endif
605 #if XCHAL_HAVE_SEXT
606 		     "sext "
607 #endif
608 #if XCHAL_HAVE_CLAMPS
609 		     "clamps "
610 #endif
611 #if XCHAL_HAVE_MAC16
612 		     "mac16 "
613 #endif
614 #if XCHAL_HAVE_MUL16
615 		     "mul16 "
616 #endif
617 #if XCHAL_HAVE_MUL32
618 		     "mul32 "
619 #endif
620 #if XCHAL_HAVE_MUL32_HIGH
621 		     "mul32h "
622 #endif
623 #if XCHAL_HAVE_FP
624 		     "fpu "
625 #endif
626 #if XCHAL_HAVE_S32C1I
627 		     "s32c1i "
628 #endif
629 #if XCHAL_HAVE_EXCLUSIVE
630 		     "exclusive "
631 #endif
632 		     "\n");
633 
634 	/* Registers. */
635 	seq_printf(f,"physical aregs\t: %d\n"
636 		     "misc regs\t: %d\n"
637 		     "ibreak\t\t: %d\n"
638 		     "dbreak\t\t: %d\n",
639 		     XCHAL_NUM_AREGS,
640 		     XCHAL_NUM_MISC_REGS,
641 		     XCHAL_NUM_IBREAK,
642 		     XCHAL_NUM_DBREAK);
643 
644 
645 	/* Interrupt. */
646 	seq_printf(f,"num ints\t: %d\n"
647 		     "ext ints\t: %d\n"
648 		     "int levels\t: %d\n"
649 		     "timers\t\t: %d\n"
650 		     "debug level\t: %d\n",
651 		     XCHAL_NUM_INTERRUPTS,
652 		     XCHAL_NUM_EXTINTERRUPTS,
653 		     XCHAL_NUM_INTLEVELS,
654 		     XCHAL_NUM_TIMERS,
655 		     XCHAL_DEBUGLEVEL);
656 
657 	/* Cache */
658 	seq_printf(f,"icache line size: %d\n"
659 		     "icache ways\t: %d\n"
660 		     "icache size\t: %d\n"
661 		     "icache flags\t: "
662 #if XCHAL_ICACHE_LINE_LOCKABLE
663 		     "lock "
664 #endif
665 		     "\n"
666 		     "dcache line size: %d\n"
667 		     "dcache ways\t: %d\n"
668 		     "dcache size\t: %d\n"
669 		     "dcache flags\t: "
670 #if XCHAL_DCACHE_IS_WRITEBACK
671 		     "writeback "
672 #endif
673 #if XCHAL_DCACHE_LINE_LOCKABLE
674 		     "lock "
675 #endif
676 		     "\n",
677 		     XCHAL_ICACHE_LINESIZE,
678 		     XCHAL_ICACHE_WAYS,
679 		     XCHAL_ICACHE_SIZE,
680 		     XCHAL_DCACHE_LINESIZE,
681 		     XCHAL_DCACHE_WAYS,
682 		     XCHAL_DCACHE_SIZE);
683 
684 	return 0;
685 }
686 
687 /*
688  * We show only CPU #0 info.
689  */
690 static void *
691 c_start(struct seq_file *f, loff_t *pos)
692 {
693 	return (*pos == 0) ? (void *)1 : NULL;
694 }
695 
696 static void *
697 c_next(struct seq_file *f, void *v, loff_t *pos)
698 {
699 	++*pos;
700 	return c_start(f, pos);
701 }
702 
703 static void
704 c_stop(struct seq_file *f, void *v)
705 {
706 }
707 
708 const struct seq_operations cpuinfo_op =
709 {
710 	.start	= c_start,
711 	.next	= c_next,
712 	.stop	= c_stop,
713 	.show	= c_show,
714 };
715 
716 #endif /* CONFIG_PROC_FS */
717