xref: /openbmc/linux/arch/xtensa/kernel/setup.c (revision 4f205687) 
1 /*
2  * arch/xtensa/kernel/setup.c
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 1995  Linus Torvalds
9  * Copyright (C) 2001 - 2005  Tensilica Inc.
10  * Copyright (C) 2014 - 2016  Cadence Design Systems Inc.
11  *
12  * Chris Zankel	<chris@zankel.net>
13  * Joe Taylor	<joe@tensilica.com, joetylr@yahoo.com>
14  * Kevin Chea
15  * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca>
16  */
17 
18 #include <linux/errno.h>
19 #include <linux/init.h>
20 #include <linux/mm.h>
21 #include <linux/proc_fs.h>
22 #include <linux/screen_info.h>
23 #include <linux/bootmem.h>
24 #include <linux/kernel.h>
25 #include <linux/percpu.h>
26 #include <linux/clk-provider.h>
27 #include <linux/cpu.h>
28 #include <linux/of.h>
29 #include <linux/of_fdt.h>
30 #include <linux/of_platform.h>
31 
32 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
33 # include <linux/console.h>
34 #endif
35 
36 #ifdef CONFIG_RTC
37 # include <linux/timex.h>
38 #endif
39 
40 #ifdef CONFIG_PROC_FS
41 # include <linux/seq_file.h>
42 #endif
43 
44 #include <asm/bootparam.h>
45 #include <asm/mmu_context.h>
46 #include <asm/pgtable.h>
47 #include <asm/processor.h>
48 #include <asm/timex.h>
49 #include <asm/platform.h>
50 #include <asm/page.h>
51 #include <asm/setup.h>
52 #include <asm/param.h>
53 #include <asm/traps.h>
54 #include <asm/smp.h>
55 #include <asm/sysmem.h>
56 
57 #include <platform/hardware.h>
58 
59 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
60 struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
61 #endif
62 
63 #ifdef CONFIG_BLK_DEV_FD
64 extern struct fd_ops no_fd_ops;
65 struct fd_ops *fd_ops;
66 #endif
67 
68 extern struct rtc_ops no_rtc_ops;
69 struct rtc_ops *rtc_ops;
70 
71 #ifdef CONFIG_BLK_DEV_INITRD
72 extern unsigned long initrd_start;
73 extern unsigned long initrd_end;
74 int initrd_is_mapped = 0;
75 extern int initrd_below_start_ok;
76 #endif
77 
78 #ifdef CONFIG_OF
79 void *dtb_start = __dtb_start;
80 #endif
81 
82 unsigned char aux_device_present;
83 extern unsigned long loops_per_jiffy;
84 
85 /* Command line specified as configuration option. */
86 
87 static char __initdata command_line[COMMAND_LINE_SIZE];
88 
89 #ifdef CONFIG_CMDLINE_BOOL
90 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE;
91 #endif
92 
93 /*
94  * Boot parameter parsing.
95  *
96  * The Xtensa port uses a list of variable-sized tags to pass data to
97  * the kernel. The first tag must be a BP_TAG_FIRST tag for the list
98  * to be recognised. The list is terminated with a zero-sized
99  * BP_TAG_LAST tag.
100  */
101 
102 typedef struct tagtable {
103 	u32 tag;
104 	int (*parse)(const bp_tag_t*);
105 } tagtable_t;
106 
107 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn 		\
108 	__attribute__((used, section(".taglist"))) = { tag, fn }
109 
110 /* parse current tag */
111 
112 static int __init parse_tag_mem(const bp_tag_t *tag)
113 {
114 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
115 
116 	if (mi->type != MEMORY_TYPE_CONVENTIONAL)
117 		return -1;
118 
119 	return memblock_add(mi->start, mi->end - mi->start);
120 }
121 
122 __tagtable(BP_TAG_MEMORY, parse_tag_mem);
123 
124 #ifdef CONFIG_BLK_DEV_INITRD
125 
126 static int __init parse_tag_initrd(const bp_tag_t* tag)
127 {
128 	struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data);
129 
130 	initrd_start = (unsigned long)__va(mi->start);
131 	initrd_end = (unsigned long)__va(mi->end);
132 
133 	return 0;
134 }
135 
136 __tagtable(BP_TAG_INITRD, parse_tag_initrd);
137 
138 #ifdef CONFIG_OF
139 
140 static int __init parse_tag_fdt(const bp_tag_t *tag)
141 {
142 	dtb_start = __va(tag->data[0]);
143 	return 0;
144 }
145 
146 __tagtable(BP_TAG_FDT, parse_tag_fdt);
147 
148 #endif /* CONFIG_OF */
149 
150 #endif /* CONFIG_BLK_DEV_INITRD */
151 
152 static int __init parse_tag_cmdline(const bp_tag_t* tag)
153 {
154 	strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE);
155 	return 0;
156 }
157 
158 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline);
159 
160 static int __init parse_bootparam(const bp_tag_t* tag)
161 {
162 	extern tagtable_t __tagtable_begin, __tagtable_end;
163 	tagtable_t *t;
164 
165 	/* Boot parameters must start with a BP_TAG_FIRST tag. */
166 
167 	if (tag->id != BP_TAG_FIRST) {
168 		printk(KERN_WARNING "Invalid boot parameters!\n");
169 		return 0;
170 	}
171 
172 	tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size);
173 
174 	/* Parse all tags. */
175 
176 	while (tag != NULL && tag->id != BP_TAG_LAST) {
177 	 	for (t = &__tagtable_begin; t < &__tagtable_end; t++) {
178 			if (tag->id == t->tag) {
179 				t->parse(tag);
180 				break;
181 			}
182 		}
183 		if (t == &__tagtable_end)
184 			printk(KERN_WARNING "Ignoring tag "
185 			       "0x%08x\n", tag->id);
186 		tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size);
187 	}
188 
189 	return 0;
190 }
191 
192 #ifdef CONFIG_OF
193 
194 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY
195 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR;
196 EXPORT_SYMBOL(xtensa_kio_paddr);
197 
198 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
199 		int depth, void *data)
200 {
201 	const __be32 *ranges;
202 	int len;
203 
204 	if (depth > 1)
205 		return 0;
206 
207 	if (!of_flat_dt_is_compatible(node, "simple-bus"))
208 		return 0;
209 
210 	ranges = of_get_flat_dt_prop(node, "ranges", &len);
211 	if (!ranges)
212 		return 1;
213 	if (len == 0)
214 		return 1;
215 
216 	xtensa_kio_paddr = of_read_ulong(ranges+1, 1);
217 	/* round down to nearest 256MB boundary */
218 	xtensa_kio_paddr &= 0xf0000000;
219 
220 	return 1;
221 }
222 #else
223 static int __init xtensa_dt_io_area(unsigned long node, const char *uname,
224 		int depth, void *data)
225 {
226 	return 1;
227 }
228 #endif
229 
230 void __init early_init_dt_add_memory_arch(u64 base, u64 size)
231 {
232 	size &= PAGE_MASK;
233 	memblock_add(base, size);
234 }
235 
236 void * __init early_init_dt_alloc_memory_arch(u64 size, u64 align)
237 {
238 	return __alloc_bootmem(size, align, 0);
239 }
240 
241 void __init early_init_devtree(void *params)
242 {
243 	early_init_dt_scan(params);
244 	of_scan_flat_dt(xtensa_dt_io_area, NULL);
245 
246 	if (!command_line[0])
247 		strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
248 }
249 
250 static int __init xtensa_device_probe(void)
251 {
252 	of_clk_init(NULL);
253 	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
254 	return 0;
255 }
256 
257 device_initcall(xtensa_device_probe);
258 
259 #endif /* CONFIG_OF */
260 
261 /*
262  * Initialize architecture. (Early stage)
263  */
264 
265 void __init init_arch(bp_tag_t *bp_start)
266 {
267 	/* Parse boot parameters */
268 
269 	if (bp_start)
270 		parse_bootparam(bp_start);
271 
272 #ifdef CONFIG_OF
273 	early_init_devtree(dtb_start);
274 #endif
275 
276 #ifdef CONFIG_CMDLINE_BOOL
277 	if (!command_line[0])
278 		strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE);
279 #endif
280 
281 	/* Early hook for platforms */
282 
283 	platform_init(bp_start);
284 
285 	/* Initialize MMU. */
286 
287 	init_mmu();
288 }
289 
290 /*
291  * Initialize system. Setup memory and reserve regions.
292  */
293 
294 extern char _end;
295 extern char _stext;
296 extern char _WindowVectors_text_start;
297 extern char _WindowVectors_text_end;
298 extern char _DebugInterruptVector_literal_start;
299 extern char _DebugInterruptVector_text_end;
300 extern char _KernelExceptionVector_literal_start;
301 extern char _KernelExceptionVector_text_end;
302 extern char _UserExceptionVector_literal_start;
303 extern char _UserExceptionVector_text_end;
304 extern char _DoubleExceptionVector_literal_start;
305 extern char _DoubleExceptionVector_text_end;
306 #if XCHAL_EXCM_LEVEL >= 2
307 extern char _Level2InterruptVector_text_start;
308 extern char _Level2InterruptVector_text_end;
309 #endif
310 #if XCHAL_EXCM_LEVEL >= 3
311 extern char _Level3InterruptVector_text_start;
312 extern char _Level3InterruptVector_text_end;
313 #endif
314 #if XCHAL_EXCM_LEVEL >= 4
315 extern char _Level4InterruptVector_text_start;
316 extern char _Level4InterruptVector_text_end;
317 #endif
318 #if XCHAL_EXCM_LEVEL >= 5
319 extern char _Level5InterruptVector_text_start;
320 extern char _Level5InterruptVector_text_end;
321 #endif
322 #if XCHAL_EXCM_LEVEL >= 6
323 extern char _Level6InterruptVector_text_start;
324 extern char _Level6InterruptVector_text_end;
325 #endif
326 #ifdef CONFIG_SMP
327 extern char _SecondaryResetVector_text_start;
328 extern char _SecondaryResetVector_text_end;
329 #endif
330 
331 
332 #ifdef CONFIG_S32C1I_SELFTEST
333 #if XCHAL_HAVE_S32C1I
334 
335 static int __initdata rcw_word, rcw_probe_pc, rcw_exc;
336 
337 /*
338  * Basic atomic compare-and-swap, that records PC of S32C1I for probing.
339  *
340  * If *v == cmp, set *v = set.  Return previous *v.
341  */
342 static inline int probed_compare_swap(int *v, int cmp, int set)
343 {
344 	int tmp;
345 
346 	__asm__ __volatile__(
347 			"	movi	%1, 1f\n"
348 			"	s32i	%1, %4, 0\n"
349 			"	wsr	%2, scompare1\n"
350 			"1:	s32c1i	%0, %3, 0\n"
351 			: "=a" (set), "=&a" (tmp)
352 			: "a" (cmp), "a" (v), "a" (&rcw_probe_pc), "0" (set)
353 			: "memory"
354 			);
355 	return set;
356 }
357 
358 /* Handle probed exception */
359 
360 static void __init do_probed_exception(struct pt_regs *regs,
361 		unsigned long exccause)
362 {
363 	if (regs->pc == rcw_probe_pc) {	/* exception on s32c1i ? */
364 		regs->pc += 3;		/* skip the s32c1i instruction */
365 		rcw_exc = exccause;
366 	} else {
367 		do_unhandled(regs, exccause);
368 	}
369 }
370 
371 /* Simple test of S32C1I (soc bringup assist) */
372 
373 static int __init check_s32c1i(void)
374 {
375 	int n, cause1, cause2;
376 	void *handbus, *handdata, *handaddr; /* temporarily saved handlers */
377 
378 	rcw_probe_pc = 0;
379 	handbus  = trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR,
380 			do_probed_exception);
381 	handdata = trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR,
382 			do_probed_exception);
383 	handaddr = trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR,
384 			do_probed_exception);
385 
386 	/* First try an S32C1I that does not store: */
387 	rcw_exc = 0;
388 	rcw_word = 1;
389 	n = probed_compare_swap(&rcw_word, 0, 2);
390 	cause1 = rcw_exc;
391 
392 	/* took exception? */
393 	if (cause1 != 0) {
394 		/* unclean exception? */
395 		if (n != 2 || rcw_word != 1)
396 			panic("S32C1I exception error");
397 	} else if (rcw_word != 1 || n != 1) {
398 		panic("S32C1I compare error");
399 	}
400 
401 	/* Then an S32C1I that stores: */
402 	rcw_exc = 0;
403 	rcw_word = 0x1234567;
404 	n = probed_compare_swap(&rcw_word, 0x1234567, 0xabcde);
405 	cause2 = rcw_exc;
406 
407 	if (cause2 != 0) {
408 		/* unclean exception? */
409 		if (n != 0xabcde || rcw_word != 0x1234567)
410 			panic("S32C1I exception error (b)");
411 	} else if (rcw_word != 0xabcde || n != 0x1234567) {
412 		panic("S32C1I store error");
413 	}
414 
415 	/* Verify consistency of exceptions: */
416 	if (cause1 || cause2) {
417 		pr_warn("S32C1I took exception %d, %d\n", cause1, cause2);
418 		/* If emulation of S32C1I upon bus error gets implemented,
419 		   we can get rid of this panic for single core (not SMP) */
420 		panic("S32C1I exceptions not currently supported");
421 	}
422 	if (cause1 != cause2)
423 		panic("inconsistent S32C1I exceptions");
424 
425 	trap_set_handler(EXCCAUSE_LOAD_STORE_ERROR, handbus);
426 	trap_set_handler(EXCCAUSE_LOAD_STORE_DATA_ERROR, handdata);
427 	trap_set_handler(EXCCAUSE_LOAD_STORE_ADDR_ERROR, handaddr);
428 	return 0;
429 }
430 
431 #else /* XCHAL_HAVE_S32C1I */
432 
433 /* This condition should not occur with a commercially deployed processor.
434    Display reminder for early engr test or demo chips / FPGA bitstreams */
435 static int __init check_s32c1i(void)
436 {
437 	pr_warn("Processor configuration lacks atomic compare-and-swap support!\n");
438 	return 0;
439 }
440 
441 #endif /* XCHAL_HAVE_S32C1I */
442 early_initcall(check_s32c1i);
443 #endif /* CONFIG_S32C1I_SELFTEST */
444 
445 static inline int mem_reserve(unsigned long start, unsigned long end)
446 {
447 	return memblock_reserve(start, end - start);
448 }
449 
450 void __init setup_arch(char **cmdline_p)
451 {
452 	strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE);
453 	*cmdline_p = command_line;
454 
455 	/* Reserve some memory regions */
456 
457 #ifdef CONFIG_BLK_DEV_INITRD
458 	if (initrd_start < initrd_end) {
459 		initrd_is_mapped = mem_reserve(__pa(initrd_start),
460 					       __pa(initrd_end)) == 0;
461 		initrd_below_start_ok = 1;
462 	} else {
463 		initrd_start = 0;
464 	}
465 #endif
466 
467 	mem_reserve(__pa(&_stext), __pa(&_end));
468 
469 	mem_reserve(__pa(&_WindowVectors_text_start),
470 		    __pa(&_WindowVectors_text_end));
471 
472 	mem_reserve(__pa(&_DebugInterruptVector_literal_start),
473 		    __pa(&_DebugInterruptVector_text_end));
474 
475 	mem_reserve(__pa(&_KernelExceptionVector_literal_start),
476 		    __pa(&_KernelExceptionVector_text_end));
477 
478 	mem_reserve(__pa(&_UserExceptionVector_literal_start),
479 		    __pa(&_UserExceptionVector_text_end));
480 
481 	mem_reserve(__pa(&_DoubleExceptionVector_literal_start),
482 		    __pa(&_DoubleExceptionVector_text_end));
483 
484 #if XCHAL_EXCM_LEVEL >= 2
485 	mem_reserve(__pa(&_Level2InterruptVector_text_start),
486 		    __pa(&_Level2InterruptVector_text_end));
487 #endif
488 #if XCHAL_EXCM_LEVEL >= 3
489 	mem_reserve(__pa(&_Level3InterruptVector_text_start),
490 		    __pa(&_Level3InterruptVector_text_end));
491 #endif
492 #if XCHAL_EXCM_LEVEL >= 4
493 	mem_reserve(__pa(&_Level4InterruptVector_text_start),
494 		    __pa(&_Level4InterruptVector_text_end));
495 #endif
496 #if XCHAL_EXCM_LEVEL >= 5
497 	mem_reserve(__pa(&_Level5InterruptVector_text_start),
498 		    __pa(&_Level5InterruptVector_text_end));
499 #endif
500 #if XCHAL_EXCM_LEVEL >= 6
501 	mem_reserve(__pa(&_Level6InterruptVector_text_start),
502 		    __pa(&_Level6InterruptVector_text_end));
503 #endif
504 
505 #ifdef CONFIG_SMP
506 	mem_reserve(__pa(&_SecondaryResetVector_text_start),
507 		    __pa(&_SecondaryResetVector_text_end));
508 #endif
509 	parse_early_param();
510 	bootmem_init();
511 
512 	unflatten_and_copy_device_tree();
513 
514 	platform_setup(cmdline_p);
515 
516 #ifdef CONFIG_SMP
517 	smp_init_cpus();
518 #endif
519 
520 	paging_init();
521 	zones_init();
522 
523 #ifdef CONFIG_VT
524 # if defined(CONFIG_VGA_CONSOLE)
525 	conswitchp = &vga_con;
526 # elif defined(CONFIG_DUMMY_CONSOLE)
527 	conswitchp = &dummy_con;
528 # endif
529 #endif
530 
531 #ifdef CONFIG_PCI
532 	platform_pcibios_init();
533 #endif
534 }
535 
536 static DEFINE_PER_CPU(struct cpu, cpu_data);
537 
538 static int __init topology_init(void)
539 {
540 	int i;
541 
542 	for_each_possible_cpu(i) {
543 		struct cpu *cpu = &per_cpu(cpu_data, i);
544 		cpu->hotpluggable = !!i;
545 		register_cpu(cpu, i);
546 	}
547 
548 	return 0;
549 }
550 subsys_initcall(topology_init);
551 
552 void cpu_reset(void)
553 {
554 	__asm__ __volatile__ ("movi	a2, 15\n\t"
555 			      "wsr	a2, icountlevel\n\t"
556 			      "movi	a2, 0\n\t"
557 			      "wsr	a2, icount\n\t"
558 #if XCHAL_NUM_IBREAK > 0
559 			      "wsr	a2, ibreakenable\n\t"
560 #endif
561 #if XCHAL_HAVE_LOOPS
562 			      "wsr	a2, lcount\n\t"
563 #endif
564 			      "movi	a2, 0x1f\n\t"
565 			      "wsr	a2, ps\n\t"
566 			      "isync\n\t"
567 			      "jx	%0\n\t"
568 			      :
569 			      : "a" (XCHAL_RESET_VECTOR_VADDR)
570 			      : "a2");
571 	for (;;)
572 		;
573 }
574 
575 void machine_restart(char * cmd)
576 {
577 	platform_restart();
578 }
579 
580 void machine_halt(void)
581 {
582 	platform_halt();
583 	while (1);
584 }
585 
586 void machine_power_off(void)
587 {
588 	platform_power_off();
589 	while (1);
590 }
591 #ifdef CONFIG_PROC_FS
592 
593 /*
594  * Display some core information through /proc/cpuinfo.
595  */
596 
597 static int
598 c_show(struct seq_file *f, void *slot)
599 {
600 	/* high-level stuff */
601 	seq_printf(f, "CPU count\t: %u\n"
602 		      "CPU list\t: %*pbl\n"
603 		      "vendor_id\t: Tensilica\n"
604 		      "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
605 		      "core ID\t\t: " XCHAL_CORE_ID "\n"
606 		      "build ID\t: 0x%x\n"
607 		      "byte order\t: %s\n"
608 		      "cpu MHz\t\t: %lu.%02lu\n"
609 		      "bogomips\t: %lu.%02lu\n",
610 		      num_online_cpus(),
611 		      cpumask_pr_args(cpu_online_mask),
612 		      XCHAL_BUILD_UNIQUE_ID,
613 		      XCHAL_HAVE_BE ?  "big" : "little",
614 		      ccount_freq/1000000,
615 		      (ccount_freq/10000) % 100,
616 		      loops_per_jiffy/(500000/HZ),
617 		      (loops_per_jiffy/(5000/HZ)) % 100);
618 
619 	seq_printf(f,"flags\t\t: "
620 #if XCHAL_HAVE_NMI
621 		     "nmi "
622 #endif
623 #if XCHAL_HAVE_DEBUG
624 		     "debug "
625 # if XCHAL_HAVE_OCD
626 		     "ocd "
627 # endif
628 #endif
629 #if XCHAL_HAVE_DENSITY
630 	    	     "density "
631 #endif
632 #if XCHAL_HAVE_BOOLEANS
633 		     "boolean "
634 #endif
635 #if XCHAL_HAVE_LOOPS
636 		     "loop "
637 #endif
638 #if XCHAL_HAVE_NSA
639 		     "nsa "
640 #endif
641 #if XCHAL_HAVE_MINMAX
642 		     "minmax "
643 #endif
644 #if XCHAL_HAVE_SEXT
645 		     "sext "
646 #endif
647 #if XCHAL_HAVE_CLAMPS
648 		     "clamps "
649 #endif
650 #if XCHAL_HAVE_MAC16
651 		     "mac16 "
652 #endif
653 #if XCHAL_HAVE_MUL16
654 		     "mul16 "
655 #endif
656 #if XCHAL_HAVE_MUL32
657 		     "mul32 "
658 #endif
659 #if XCHAL_HAVE_MUL32_HIGH
660 		     "mul32h "
661 #endif
662 #if XCHAL_HAVE_FP
663 		     "fpu "
664 #endif
665 #if XCHAL_HAVE_S32C1I
666 		     "s32c1i "
667 #endif
668 		     "\n");
669 
670 	/* Registers. */
671 	seq_printf(f,"physical aregs\t: %d\n"
672 		     "misc regs\t: %d\n"
673 		     "ibreak\t\t: %d\n"
674 		     "dbreak\t\t: %d\n",
675 		     XCHAL_NUM_AREGS,
676 		     XCHAL_NUM_MISC_REGS,
677 		     XCHAL_NUM_IBREAK,
678 		     XCHAL_NUM_DBREAK);
679 
680 
681 	/* Interrupt. */
682 	seq_printf(f,"num ints\t: %d\n"
683 		     "ext ints\t: %d\n"
684 		     "int levels\t: %d\n"
685 		     "timers\t\t: %d\n"
686 		     "debug level\t: %d\n",
687 		     XCHAL_NUM_INTERRUPTS,
688 		     XCHAL_NUM_EXTINTERRUPTS,
689 		     XCHAL_NUM_INTLEVELS,
690 		     XCHAL_NUM_TIMERS,
691 		     XCHAL_DEBUGLEVEL);
692 
693 	/* Cache */
694 	seq_printf(f,"icache line size: %d\n"
695 		     "icache ways\t: %d\n"
696 		     "icache size\t: %d\n"
697 		     "icache flags\t: "
698 #if XCHAL_ICACHE_LINE_LOCKABLE
699 		     "lock "
700 #endif
701 		     "\n"
702 		     "dcache line size: %d\n"
703 		     "dcache ways\t: %d\n"
704 		     "dcache size\t: %d\n"
705 		     "dcache flags\t: "
706 #if XCHAL_DCACHE_IS_WRITEBACK
707 		     "writeback "
708 #endif
709 #if XCHAL_DCACHE_LINE_LOCKABLE
710 		     "lock "
711 #endif
712 		     "\n",
713 		     XCHAL_ICACHE_LINESIZE,
714 		     XCHAL_ICACHE_WAYS,
715 		     XCHAL_ICACHE_SIZE,
716 		     XCHAL_DCACHE_LINESIZE,
717 		     XCHAL_DCACHE_WAYS,
718 		     XCHAL_DCACHE_SIZE);
719 
720 	return 0;
721 }
722 
723 /*
724  * We show only CPU #0 info.
725  */
726 static void *
727 c_start(struct seq_file *f, loff_t *pos)
728 {
729 	return (*pos == 0) ? (void *)1 : NULL;
730 }
731 
732 static void *
733 c_next(struct seq_file *f, void *v, loff_t *pos)
734 {
735 	return NULL;
736 }
737 
738 static void
739 c_stop(struct seq_file *f, void *v)
740 {
741 }
742 
743 const struct seq_operations cpuinfo_op =
744 {
745 	.start	= c_start,
746 	.next	= c_next,
747 	.stop	= c_stop,
748 	.show	= c_show,
749 };
750 
751 #endif /* CONFIG_PROC_FS */
752