1 /* 2 * arch/xtensa/kernel/setup.c 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 1995 Linus Torvalds 9 * Copyright (C) 2001 - 2005 Tensilica Inc. 10 * Copyright (C) 2014 - 2016 Cadence Design Systems Inc. 11 * 12 * Chris Zankel <chris@zankel.net> 13 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com> 14 * Kevin Chea 15 * Marc Gauthier<marc@tensilica.com> <marc@alumni.uwaterloo.ca> 16 */ 17 18 #include <linux/errno.h> 19 #include <linux/init.h> 20 #include <linux/mm.h> 21 #include <linux/proc_fs.h> 22 #include <linux/screen_info.h> 23 #include <linux/kernel.h> 24 #include <linux/percpu.h> 25 #include <linux/cpu.h> 26 #include <linux/of.h> 27 #include <linux/of_fdt.h> 28 29 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 30 # include <linux/console.h> 31 #endif 32 33 #ifdef CONFIG_PROC_FS 34 # include <linux/seq_file.h> 35 #endif 36 37 #include <asm/bootparam.h> 38 #include <asm/kasan.h> 39 #include <asm/mmu_context.h> 40 #include <asm/pgtable.h> 41 #include <asm/processor.h> 42 #include <asm/timex.h> 43 #include <asm/platform.h> 44 #include <asm/page.h> 45 #include <asm/setup.h> 46 #include <asm/param.h> 47 #include <asm/smp.h> 48 #include <asm/sysmem.h> 49 50 #if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 51 struct screen_info screen_info = { 52 .orig_x = 0, 53 .orig_y = 24, 54 .orig_video_cols = 80, 55 .orig_video_lines = 24, 56 .orig_video_isVGA = 1, 57 .orig_video_points = 16, 58 }; 59 #endif 60 61 #ifdef CONFIG_BLK_DEV_INITRD 62 extern unsigned long initrd_start; 63 extern unsigned long initrd_end; 64 extern int initrd_below_start_ok; 65 #endif 66 67 #ifdef CONFIG_OF 68 void *dtb_start = __dtb_start; 69 #endif 70 71 extern unsigned long loops_per_jiffy; 72 73 /* Command line specified as configuration option. */ 74 75 static char __initdata command_line[COMMAND_LINE_SIZE]; 76 77 #ifdef CONFIG_CMDLINE_BOOL 78 static char default_command_line[COMMAND_LINE_SIZE] __initdata = CONFIG_CMDLINE; 79 #endif 80 81 #ifdef CONFIG_PARSE_BOOTPARAM 82 /* 83 * Boot parameter parsing. 84 * 85 * The Xtensa port uses a list of variable-sized tags to pass data to 86 * the kernel. The first tag must be a BP_TAG_FIRST tag for the list 87 * to be recognised. The list is terminated with a zero-sized 88 * BP_TAG_LAST tag. 89 */ 90 91 typedef struct tagtable { 92 u32 tag; 93 int (*parse)(const bp_tag_t*); 94 } tagtable_t; 95 96 #define __tagtable(tag, fn) static tagtable_t __tagtable_##fn \ 97 __attribute__((used, section(".taglist"))) = { tag, fn } 98 99 /* parse current tag */ 100 101 static int __init parse_tag_mem(const bp_tag_t *tag) 102 { 103 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); 104 105 if (mi->type != MEMORY_TYPE_CONVENTIONAL) 106 return -1; 107 108 return memblock_add(mi->start, mi->end - mi->start); 109 } 110 111 __tagtable(BP_TAG_MEMORY, parse_tag_mem); 112 113 #ifdef CONFIG_BLK_DEV_INITRD 114 115 static int __init parse_tag_initrd(const bp_tag_t* tag) 116 { 117 struct bp_meminfo *mi = (struct bp_meminfo *)(tag->data); 118 119 initrd_start = (unsigned long)__va(mi->start); 120 initrd_end = (unsigned long)__va(mi->end); 121 122 return 0; 123 } 124 125 __tagtable(BP_TAG_INITRD, parse_tag_initrd); 126 127 #endif /* CONFIG_BLK_DEV_INITRD */ 128 129 #ifdef CONFIG_OF 130 131 static int __init parse_tag_fdt(const bp_tag_t *tag) 132 { 133 dtb_start = __va(tag->data[0]); 134 return 0; 135 } 136 137 __tagtable(BP_TAG_FDT, parse_tag_fdt); 138 139 #endif /* CONFIG_OF */ 140 141 static int __init parse_tag_cmdline(const bp_tag_t* tag) 142 { 143 strlcpy(command_line, (char *)(tag->data), COMMAND_LINE_SIZE); 144 return 0; 145 } 146 147 __tagtable(BP_TAG_COMMAND_LINE, parse_tag_cmdline); 148 149 static int __init parse_bootparam(const bp_tag_t* tag) 150 { 151 extern tagtable_t __tagtable_begin, __tagtable_end; 152 tagtable_t *t; 153 154 /* Boot parameters must start with a BP_TAG_FIRST tag. */ 155 156 if (tag->id != BP_TAG_FIRST) { 157 pr_warn("Invalid boot parameters!\n"); 158 return 0; 159 } 160 161 tag = (bp_tag_t*)((unsigned long)tag + sizeof(bp_tag_t) + tag->size); 162 163 /* Parse all tags. */ 164 165 while (tag != NULL && tag->id != BP_TAG_LAST) { 166 for (t = &__tagtable_begin; t < &__tagtable_end; t++) { 167 if (tag->id == t->tag) { 168 t->parse(tag); 169 break; 170 } 171 } 172 if (t == &__tagtable_end) 173 pr_warn("Ignoring tag 0x%08x\n", tag->id); 174 tag = (bp_tag_t*)((unsigned long)(tag + 1) + tag->size); 175 } 176 177 return 0; 178 } 179 #else 180 static int __init parse_bootparam(const bp_tag_t *tag) 181 { 182 pr_info("Ignoring boot parameters at %p\n", tag); 183 return 0; 184 } 185 #endif 186 187 #ifdef CONFIG_OF 188 189 #if !XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY 190 unsigned long xtensa_kio_paddr = XCHAL_KIO_DEFAULT_PADDR; 191 EXPORT_SYMBOL(xtensa_kio_paddr); 192 193 static int __init xtensa_dt_io_area(unsigned long node, const char *uname, 194 int depth, void *data) 195 { 196 const __be32 *ranges; 197 int len; 198 199 if (depth > 1) 200 return 0; 201 202 if (!of_flat_dt_is_compatible(node, "simple-bus")) 203 return 0; 204 205 ranges = of_get_flat_dt_prop(node, "ranges", &len); 206 if (!ranges) 207 return 1; 208 if (len == 0) 209 return 1; 210 211 xtensa_kio_paddr = of_read_ulong(ranges+1, 1); 212 /* round down to nearest 256MB boundary */ 213 xtensa_kio_paddr &= 0xf0000000; 214 215 init_kio(); 216 217 return 1; 218 } 219 #else 220 static int __init xtensa_dt_io_area(unsigned long node, const char *uname, 221 int depth, void *data) 222 { 223 return 1; 224 } 225 #endif 226 227 void __init early_init_devtree(void *params) 228 { 229 early_init_dt_scan(params); 230 of_scan_flat_dt(xtensa_dt_io_area, NULL); 231 232 if (!command_line[0]) 233 strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE); 234 } 235 236 #endif /* CONFIG_OF */ 237 238 /* 239 * Initialize architecture. (Early stage) 240 */ 241 242 void __init init_arch(bp_tag_t *bp_start) 243 { 244 /* Initialize MMU. */ 245 246 init_mmu(); 247 248 /* Initialize initial KASAN shadow map */ 249 250 kasan_early_init(); 251 252 /* Parse boot parameters */ 253 254 if (bp_start) 255 parse_bootparam(bp_start); 256 257 #ifdef CONFIG_OF 258 early_init_devtree(dtb_start); 259 #endif 260 261 #ifdef CONFIG_CMDLINE_BOOL 262 if (!command_line[0]) 263 strlcpy(command_line, default_command_line, COMMAND_LINE_SIZE); 264 #endif 265 266 /* Early hook for platforms */ 267 268 platform_init(bp_start); 269 } 270 271 /* 272 * Initialize system. Setup memory and reserve regions. 273 */ 274 275 extern char _end[]; 276 extern char _stext[]; 277 extern char _WindowVectors_text_start; 278 extern char _WindowVectors_text_end; 279 extern char _DebugInterruptVector_text_start; 280 extern char _DebugInterruptVector_text_end; 281 extern char _KernelExceptionVector_text_start; 282 extern char _KernelExceptionVector_text_end; 283 extern char _UserExceptionVector_text_start; 284 extern char _UserExceptionVector_text_end; 285 extern char _DoubleExceptionVector_text_start; 286 extern char _DoubleExceptionVector_text_end; 287 extern char _exception_text_start; 288 extern char _exception_text_end; 289 #if XCHAL_EXCM_LEVEL >= 2 290 extern char _Level2InterruptVector_text_start; 291 extern char _Level2InterruptVector_text_end; 292 #endif 293 #if XCHAL_EXCM_LEVEL >= 3 294 extern char _Level3InterruptVector_text_start; 295 extern char _Level3InterruptVector_text_end; 296 #endif 297 #if XCHAL_EXCM_LEVEL >= 4 298 extern char _Level4InterruptVector_text_start; 299 extern char _Level4InterruptVector_text_end; 300 #endif 301 #if XCHAL_EXCM_LEVEL >= 5 302 extern char _Level5InterruptVector_text_start; 303 extern char _Level5InterruptVector_text_end; 304 #endif 305 #if XCHAL_EXCM_LEVEL >= 6 306 extern char _Level6InterruptVector_text_start; 307 extern char _Level6InterruptVector_text_end; 308 #endif 309 #ifdef CONFIG_SMP 310 extern char _SecondaryResetVector_text_start; 311 extern char _SecondaryResetVector_text_end; 312 #endif 313 #ifdef CONFIG_XIP_KERNEL 314 extern char _xip_start[]; 315 extern char _xip_end[]; 316 #endif 317 318 static inline int __init_memblock mem_reserve(unsigned long start, 319 unsigned long end) 320 { 321 return memblock_reserve(start, end - start); 322 } 323 324 void __init setup_arch(char **cmdline_p) 325 { 326 pr_info("config ID: %08x:%08x\n", 327 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE)); 328 if (xtensa_get_sr(SREG_EPC) != XCHAL_HW_CONFIGID0 || 329 xtensa_get_sr(SREG_EXCSAVE) != XCHAL_HW_CONFIGID1) 330 pr_info("built for config ID: %08x:%08x\n", 331 XCHAL_HW_CONFIGID0, XCHAL_HW_CONFIGID1); 332 333 *cmdline_p = command_line; 334 platform_setup(cmdline_p); 335 strlcpy(boot_command_line, *cmdline_p, COMMAND_LINE_SIZE); 336 337 /* Reserve some memory regions */ 338 339 #ifdef CONFIG_BLK_DEV_INITRD 340 if (initrd_start < initrd_end && 341 !mem_reserve(__pa(initrd_start), __pa(initrd_end))) 342 initrd_below_start_ok = 1; 343 else 344 initrd_start = 0; 345 #endif 346 347 mem_reserve(__pa(_stext), __pa(_end)); 348 #ifdef CONFIG_XIP_KERNEL 349 mem_reserve(__pa(_xip_start), __pa(_xip_end)); 350 #endif 351 352 #ifdef CONFIG_VECTORS_ADDR 353 mem_reserve(__pa(&_WindowVectors_text_start), 354 __pa(&_WindowVectors_text_end)); 355 356 mem_reserve(__pa(&_DebugInterruptVector_text_start), 357 __pa(&_DebugInterruptVector_text_end)); 358 359 mem_reserve(__pa(&_KernelExceptionVector_text_start), 360 __pa(&_KernelExceptionVector_text_end)); 361 362 mem_reserve(__pa(&_UserExceptionVector_text_start), 363 __pa(&_UserExceptionVector_text_end)); 364 365 mem_reserve(__pa(&_DoubleExceptionVector_text_start), 366 __pa(&_DoubleExceptionVector_text_end)); 367 368 mem_reserve(__pa(&_exception_text_start), 369 __pa(&_exception_text_end)); 370 #if XCHAL_EXCM_LEVEL >= 2 371 mem_reserve(__pa(&_Level2InterruptVector_text_start), 372 __pa(&_Level2InterruptVector_text_end)); 373 #endif 374 #if XCHAL_EXCM_LEVEL >= 3 375 mem_reserve(__pa(&_Level3InterruptVector_text_start), 376 __pa(&_Level3InterruptVector_text_end)); 377 #endif 378 #if XCHAL_EXCM_LEVEL >= 4 379 mem_reserve(__pa(&_Level4InterruptVector_text_start), 380 __pa(&_Level4InterruptVector_text_end)); 381 #endif 382 #if XCHAL_EXCM_LEVEL >= 5 383 mem_reserve(__pa(&_Level5InterruptVector_text_start), 384 __pa(&_Level5InterruptVector_text_end)); 385 #endif 386 #if XCHAL_EXCM_LEVEL >= 6 387 mem_reserve(__pa(&_Level6InterruptVector_text_start), 388 __pa(&_Level6InterruptVector_text_end)); 389 #endif 390 391 #endif /* CONFIG_VECTORS_ADDR */ 392 393 #ifdef CONFIG_SMP 394 mem_reserve(__pa(&_SecondaryResetVector_text_start), 395 __pa(&_SecondaryResetVector_text_end)); 396 #endif 397 parse_early_param(); 398 bootmem_init(); 399 kasan_init(); 400 unflatten_and_copy_device_tree(); 401 402 #ifdef CONFIG_SMP 403 smp_init_cpus(); 404 #endif 405 406 paging_init(); 407 zones_init(); 408 409 #ifdef CONFIG_VT 410 # if defined(CONFIG_VGA_CONSOLE) 411 conswitchp = &vga_con; 412 # endif 413 #endif 414 } 415 416 static DEFINE_PER_CPU(struct cpu, cpu_data); 417 418 static int __init topology_init(void) 419 { 420 int i; 421 422 for_each_possible_cpu(i) { 423 struct cpu *cpu = &per_cpu(cpu_data, i); 424 cpu->hotpluggable = !!i; 425 register_cpu(cpu, i); 426 } 427 428 return 0; 429 } 430 subsys_initcall(topology_init); 431 432 void cpu_reset(void) 433 { 434 #if XCHAL_HAVE_PTP_MMU && IS_ENABLED(CONFIG_MMU) 435 local_irq_disable(); 436 /* 437 * We have full MMU: all autoload ways, ways 7, 8 and 9 of DTLB must 438 * be flushed. 439 * Way 4 is not currently used by linux. 440 * Ways 5 and 6 shall not be touched on MMUv2 as they are hardwired. 441 * Way 5 shall be flushed and way 6 shall be set to identity mapping 442 * on MMUv3. 443 */ 444 local_flush_tlb_all(); 445 invalidate_page_directory(); 446 #if XCHAL_HAVE_SPANNING_WAY 447 /* MMU v3 */ 448 { 449 unsigned long vaddr = (unsigned long)cpu_reset; 450 unsigned long paddr = __pa(vaddr); 451 unsigned long tmpaddr = vaddr + SZ_512M; 452 unsigned long tmp0, tmp1, tmp2, tmp3; 453 454 /* 455 * Find a place for the temporary mapping. It must not be 456 * in the same 512MB region with vaddr or paddr, otherwise 457 * there may be multihit exception either on entry to the 458 * temporary mapping, or on entry to the identity mapping. 459 * (512MB is the biggest page size supported by TLB.) 460 */ 461 while (((tmpaddr ^ paddr) & -SZ_512M) == 0) 462 tmpaddr += SZ_512M; 463 464 /* Invalidate mapping in the selected temporary area */ 465 if (itlb_probe(tmpaddr) & BIT(ITLB_HIT_BIT)) 466 invalidate_itlb_entry(itlb_probe(tmpaddr)); 467 if (itlb_probe(tmpaddr + PAGE_SIZE) & BIT(ITLB_HIT_BIT)) 468 invalidate_itlb_entry(itlb_probe(tmpaddr + PAGE_SIZE)); 469 470 /* 471 * Map two consecutive pages starting at the physical address 472 * of this function to the temporary mapping area. 473 */ 474 write_itlb_entry(__pte((paddr & PAGE_MASK) | 475 _PAGE_HW_VALID | 476 _PAGE_HW_EXEC | 477 _PAGE_CA_BYPASS), 478 tmpaddr & PAGE_MASK); 479 write_itlb_entry(__pte(((paddr & PAGE_MASK) + PAGE_SIZE) | 480 _PAGE_HW_VALID | 481 _PAGE_HW_EXEC | 482 _PAGE_CA_BYPASS), 483 (tmpaddr & PAGE_MASK) + PAGE_SIZE); 484 485 /* Reinitialize TLB */ 486 __asm__ __volatile__ ("movi %0, 1f\n\t" 487 "movi %3, 2f\n\t" 488 "add %0, %0, %4\n\t" 489 "add %3, %3, %5\n\t" 490 "jx %0\n" 491 /* 492 * No literal, data or stack access 493 * below this point 494 */ 495 "1:\n\t" 496 /* Initialize *tlbcfg */ 497 "movi %0, 0\n\t" 498 "wsr %0, itlbcfg\n\t" 499 "wsr %0, dtlbcfg\n\t" 500 /* Invalidate TLB way 5 */ 501 "movi %0, 4\n\t" 502 "movi %1, 5\n" 503 "1:\n\t" 504 "iitlb %1\n\t" 505 "idtlb %1\n\t" 506 "add %1, %1, %6\n\t" 507 "addi %0, %0, -1\n\t" 508 "bnez %0, 1b\n\t" 509 /* Initialize TLB way 6 */ 510 "movi %0, 7\n\t" 511 "addi %1, %9, 3\n\t" 512 "addi %2, %9, 6\n" 513 "1:\n\t" 514 "witlb %1, %2\n\t" 515 "wdtlb %1, %2\n\t" 516 "add %1, %1, %7\n\t" 517 "add %2, %2, %7\n\t" 518 "addi %0, %0, -1\n\t" 519 "bnez %0, 1b\n\t" 520 "isync\n\t" 521 /* Jump to identity mapping */ 522 "jx %3\n" 523 "2:\n\t" 524 /* Complete way 6 initialization */ 525 "witlb %1, %2\n\t" 526 "wdtlb %1, %2\n\t" 527 /* Invalidate temporary mapping */ 528 "sub %0, %9, %7\n\t" 529 "iitlb %0\n\t" 530 "add %0, %0, %8\n\t" 531 "iitlb %0" 532 : "=&a"(tmp0), "=&a"(tmp1), "=&a"(tmp2), 533 "=&a"(tmp3) 534 : "a"(tmpaddr - vaddr), 535 "a"(paddr - vaddr), 536 "a"(SZ_128M), "a"(SZ_512M), 537 "a"(PAGE_SIZE), 538 "a"((tmpaddr + SZ_512M) & PAGE_MASK) 539 : "memory"); 540 } 541 #endif 542 #endif 543 __asm__ __volatile__ ("movi a2, 0\n\t" 544 "wsr a2, icountlevel\n\t" 545 "movi a2, 0\n\t" 546 "wsr a2, icount\n\t" 547 #if XCHAL_NUM_IBREAK > 0 548 "wsr a2, ibreakenable\n\t" 549 #endif 550 #if XCHAL_HAVE_LOOPS 551 "wsr a2, lcount\n\t" 552 #endif 553 "movi a2, 0x1f\n\t" 554 "wsr a2, ps\n\t" 555 "isync\n\t" 556 "jx %0\n\t" 557 : 558 : "a" (XCHAL_RESET_VECTOR_VADDR) 559 : "a2"); 560 for (;;) 561 ; 562 } 563 564 void machine_restart(char * cmd) 565 { 566 platform_restart(); 567 } 568 569 void machine_halt(void) 570 { 571 platform_halt(); 572 while (1); 573 } 574 575 void machine_power_off(void) 576 { 577 platform_power_off(); 578 while (1); 579 } 580 #ifdef CONFIG_PROC_FS 581 582 /* 583 * Display some core information through /proc/cpuinfo. 584 */ 585 586 static int 587 c_show(struct seq_file *f, void *slot) 588 { 589 /* high-level stuff */ 590 seq_printf(f, "CPU count\t: %u\n" 591 "CPU list\t: %*pbl\n" 592 "vendor_id\t: Tensilica\n" 593 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n" 594 "core ID\t\t: " XCHAL_CORE_ID "\n" 595 "build ID\t: 0x%x\n" 596 "config ID\t: %08x:%08x\n" 597 "byte order\t: %s\n" 598 "cpu MHz\t\t: %lu.%02lu\n" 599 "bogomips\t: %lu.%02lu\n", 600 num_online_cpus(), 601 cpumask_pr_args(cpu_online_mask), 602 XCHAL_BUILD_UNIQUE_ID, 603 xtensa_get_sr(SREG_EPC), xtensa_get_sr(SREG_EXCSAVE), 604 XCHAL_HAVE_BE ? "big" : "little", 605 ccount_freq/1000000, 606 (ccount_freq/10000) % 100, 607 loops_per_jiffy/(500000/HZ), 608 (loops_per_jiffy/(5000/HZ)) % 100); 609 seq_puts(f, "flags\t\t: " 610 #if XCHAL_HAVE_NMI 611 "nmi " 612 #endif 613 #if XCHAL_HAVE_DEBUG 614 "debug " 615 # if XCHAL_HAVE_OCD 616 "ocd " 617 # endif 618 #endif 619 #if XCHAL_HAVE_DENSITY 620 "density " 621 #endif 622 #if XCHAL_HAVE_BOOLEANS 623 "boolean " 624 #endif 625 #if XCHAL_HAVE_LOOPS 626 "loop " 627 #endif 628 #if XCHAL_HAVE_NSA 629 "nsa " 630 #endif 631 #if XCHAL_HAVE_MINMAX 632 "minmax " 633 #endif 634 #if XCHAL_HAVE_SEXT 635 "sext " 636 #endif 637 #if XCHAL_HAVE_CLAMPS 638 "clamps " 639 #endif 640 #if XCHAL_HAVE_MAC16 641 "mac16 " 642 #endif 643 #if XCHAL_HAVE_MUL16 644 "mul16 " 645 #endif 646 #if XCHAL_HAVE_MUL32 647 "mul32 " 648 #endif 649 #if XCHAL_HAVE_MUL32_HIGH 650 "mul32h " 651 #endif 652 #if XCHAL_HAVE_FP 653 "fpu " 654 #endif 655 #if XCHAL_HAVE_S32C1I 656 "s32c1i " 657 #endif 658 #if XCHAL_HAVE_EXCLUSIVE 659 "exclusive " 660 #endif 661 "\n"); 662 663 /* Registers. */ 664 seq_printf(f,"physical aregs\t: %d\n" 665 "misc regs\t: %d\n" 666 "ibreak\t\t: %d\n" 667 "dbreak\t\t: %d\n", 668 XCHAL_NUM_AREGS, 669 XCHAL_NUM_MISC_REGS, 670 XCHAL_NUM_IBREAK, 671 XCHAL_NUM_DBREAK); 672 673 674 /* Interrupt. */ 675 seq_printf(f,"num ints\t: %d\n" 676 "ext ints\t: %d\n" 677 "int levels\t: %d\n" 678 "timers\t\t: %d\n" 679 "debug level\t: %d\n", 680 XCHAL_NUM_INTERRUPTS, 681 XCHAL_NUM_EXTINTERRUPTS, 682 XCHAL_NUM_INTLEVELS, 683 XCHAL_NUM_TIMERS, 684 XCHAL_DEBUGLEVEL); 685 686 /* Cache */ 687 seq_printf(f,"icache line size: %d\n" 688 "icache ways\t: %d\n" 689 "icache size\t: %d\n" 690 "icache flags\t: " 691 #if XCHAL_ICACHE_LINE_LOCKABLE 692 "lock " 693 #endif 694 "\n" 695 "dcache line size: %d\n" 696 "dcache ways\t: %d\n" 697 "dcache size\t: %d\n" 698 "dcache flags\t: " 699 #if XCHAL_DCACHE_IS_WRITEBACK 700 "writeback " 701 #endif 702 #if XCHAL_DCACHE_LINE_LOCKABLE 703 "lock " 704 #endif 705 "\n", 706 XCHAL_ICACHE_LINESIZE, 707 XCHAL_ICACHE_WAYS, 708 XCHAL_ICACHE_SIZE, 709 XCHAL_DCACHE_LINESIZE, 710 XCHAL_DCACHE_WAYS, 711 XCHAL_DCACHE_SIZE); 712 713 return 0; 714 } 715 716 /* 717 * We show only CPU #0 info. 718 */ 719 static void * 720 c_start(struct seq_file *f, loff_t *pos) 721 { 722 return (*pos == 0) ? (void *)1 : NULL; 723 } 724 725 static void * 726 c_next(struct seq_file *f, void *v, loff_t *pos) 727 { 728 return NULL; 729 } 730 731 static void 732 c_stop(struct seq_file *f, void *v) 733 { 734 } 735 736 const struct seq_operations cpuinfo_op = 737 { 738 .start = c_start, 739 .next = c_next, 740 .stop = c_stop, 741 .show = c_show, 742 }; 743 744 #endif /* CONFIG_PROC_FS */ 745