1 /* 2 * arch/xtensa/kernel/pci.c 3 * 4 * PCI bios-type initialisation for PCI machines 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License as published by the 8 * Free Software Foundation; either version 2 of the License, or (at your 9 * option) any later version. 10 * 11 * Copyright (C) 2001-2005 Tensilica Inc. 12 * 13 * Based largely on work from Cort (ppc/kernel/pci.c) 14 * IO functions copied from sparc. 15 * 16 * Chris Zankel <chris@zankel.net> 17 * 18 */ 19 20 #include <linux/kernel.h> 21 #include <linux/pci.h> 22 #include <linux/delay.h> 23 #include <linux/string.h> 24 #include <linux/init.h> 25 #include <linux/sched.h> 26 #include <linux/errno.h> 27 #include <linux/bootmem.h> 28 29 #include <asm/pci-bridge.h> 30 #include <asm/platform.h> 31 32 /* PCI Controller */ 33 34 35 /* 36 * pcibios_alloc_controller 37 * pcibios_enable_device 38 * pcibios_fixups 39 * pcibios_align_resource 40 * pcibios_fixup_bus 41 * pci_bus_add_device 42 */ 43 44 struct pci_controller* pci_ctrl_head; 45 struct pci_controller** pci_ctrl_tail = &pci_ctrl_head; 46 47 static int pci_bus_count; 48 49 /* 50 * We need to avoid collisions with `mirrored' VGA ports 51 * and other strange ISA hardware, so we always want the 52 * addresses to be allocated in the 0x000-0x0ff region 53 * modulo 0x400. 54 * 55 * Why? Because some silly external IO cards only decode 56 * the low 10 bits of the IO address. The 0x00-0xff region 57 * is reserved for motherboard devices that decode all 16 58 * bits, so it's ok to allocate at, say, 0x2800-0x28ff, 59 * but we want to try to avoid allocating at 0x2900-0x2bff 60 * which might have be mirrored at 0x0100-0x03ff.. 61 */ 62 resource_size_t 63 pcibios_align_resource(void *data, const struct resource *res, 64 resource_size_t size, resource_size_t align) 65 { 66 struct pci_dev *dev = data; 67 resource_size_t start = res->start; 68 69 if (res->flags & IORESOURCE_IO) { 70 if (size > 0x100) { 71 pr_err("PCI: I/O Region %s/%d too large (%u bytes)\n", 72 pci_name(dev), dev->resource - res, 73 size); 74 } 75 76 if (start & 0x300) 77 start = (start + 0x3ff) & ~0x3ff; 78 } 79 80 return start; 81 } 82 83 int 84 pcibios_enable_resources(struct pci_dev *dev, int mask) 85 { 86 u16 cmd, old_cmd; 87 int idx; 88 struct resource *r; 89 90 pci_read_config_word(dev, PCI_COMMAND, &cmd); 91 old_cmd = cmd; 92 for(idx=0; idx<6; idx++) { 93 r = &dev->resource[idx]; 94 if (!r->start && r->end) { 95 pr_err("PCI: Device %s not available because " 96 "of resource collisions\n", pci_name(dev)); 97 return -EINVAL; 98 } 99 if (r->flags & IORESOURCE_IO) 100 cmd |= PCI_COMMAND_IO; 101 if (r->flags & IORESOURCE_MEM) 102 cmd |= PCI_COMMAND_MEMORY; 103 } 104 if (dev->resource[PCI_ROM_RESOURCE].start) 105 cmd |= PCI_COMMAND_MEMORY; 106 if (cmd != old_cmd) { 107 pr_info("PCI: Enabling device %s (%04x -> %04x)\n", 108 pci_name(dev), old_cmd, cmd); 109 pci_write_config_word(dev, PCI_COMMAND, cmd); 110 } 111 return 0; 112 } 113 114 struct pci_controller * __init pcibios_alloc_controller(void) 115 { 116 struct pci_controller *pci_ctrl; 117 118 pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl)); 119 memset(pci_ctrl, 0, sizeof(struct pci_controller)); 120 121 *pci_ctrl_tail = pci_ctrl; 122 pci_ctrl_tail = &pci_ctrl->next; 123 124 return pci_ctrl; 125 } 126 127 static void __init pci_controller_apertures(struct pci_controller *pci_ctrl, 128 struct list_head *resources) 129 { 130 struct resource *res; 131 unsigned long io_offset; 132 int i; 133 134 io_offset = (unsigned long)pci_ctrl->io_space.base; 135 res = &pci_ctrl->io_resource; 136 if (!res->flags) { 137 if (io_offset) 138 pr_err("I/O resource not set for host bridge %d\n", 139 pci_ctrl->index); 140 res->start = 0; 141 res->end = IO_SPACE_LIMIT; 142 res->flags = IORESOURCE_IO; 143 } 144 res->start += io_offset; 145 res->end += io_offset; 146 pci_add_resource_offset(resources, res, io_offset); 147 148 for (i = 0; i < 3; i++) { 149 res = &pci_ctrl->mem_resources[i]; 150 if (!res->flags) { 151 if (i > 0) 152 continue; 153 pr_err("Memory resource not set for host bridge %d\n", 154 pci_ctrl->index); 155 res->start = 0; 156 res->end = ~0U; 157 res->flags = IORESOURCE_MEM; 158 } 159 pci_add_resource(resources, res); 160 } 161 } 162 163 static int __init pcibios_init(void) 164 { 165 struct pci_controller *pci_ctrl; 166 struct list_head resources; 167 struct pci_bus *bus; 168 int next_busno = 0, ret; 169 170 pr_info("PCI: Probing PCI hardware\n"); 171 172 /* Scan all of the recorded PCI controllers. */ 173 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { 174 pci_ctrl->last_busno = 0xff; 175 INIT_LIST_HEAD(&resources); 176 pci_controller_apertures(pci_ctrl, &resources); 177 bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno, 178 pci_ctrl->ops, pci_ctrl, &resources); 179 if (!bus) 180 continue; 181 182 pci_ctrl->bus = bus; 183 pci_ctrl->last_busno = bus->busn_res.end; 184 if (next_busno <= pci_ctrl->last_busno) 185 next_busno = pci_ctrl->last_busno+1; 186 } 187 pci_bus_count = next_busno; 188 ret = platform_pcibios_fixup(); 189 if (ret) 190 return ret; 191 192 for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) { 193 if (pci_ctrl->bus) 194 pci_bus_add_devices(pci_ctrl->bus); 195 } 196 197 return 0; 198 } 199 200 subsys_initcall(pcibios_init); 201 202 void pcibios_fixup_bus(struct pci_bus *bus) 203 { 204 if (bus->parent) { 205 /* This is a subordinate bridge */ 206 pci_read_bridge_bases(bus); 207 } 208 } 209 210 void pcibios_set_master(struct pci_dev *dev) 211 { 212 /* No special bus mastering setup handling */ 213 } 214 215 int pcibios_enable_device(struct pci_dev *dev, int mask) 216 { 217 u16 cmd, old_cmd; 218 int idx; 219 struct resource *r; 220 221 pci_read_config_word(dev, PCI_COMMAND, &cmd); 222 old_cmd = cmd; 223 for (idx=0; idx<6; idx++) { 224 r = &dev->resource[idx]; 225 if (!r->start && r->end) { 226 pr_err("PCI: Device %s not available because " 227 "of resource collisions\n", pci_name(dev)); 228 return -EINVAL; 229 } 230 if (r->flags & IORESOURCE_IO) 231 cmd |= PCI_COMMAND_IO; 232 if (r->flags & IORESOURCE_MEM) 233 cmd |= PCI_COMMAND_MEMORY; 234 } 235 if (cmd != old_cmd) { 236 pr_info("PCI: Enabling device %s (%04x -> %04x)\n", 237 pci_name(dev), old_cmd, cmd); 238 pci_write_config_word(dev, PCI_COMMAND, cmd); 239 } 240 241 return 0; 242 } 243 244 #ifdef CONFIG_PROC_FS 245 246 /* 247 * Return the index of the PCI controller for device pdev. 248 */ 249 250 int 251 pci_controller_num(struct pci_dev *dev) 252 { 253 struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata; 254 return pci_ctrl->index; 255 } 256 257 #endif /* CONFIG_PROC_FS */ 258 259 /* 260 * Platform support for /proc/bus/pci/X/Y mmap()s. 261 * -- paulus. 262 */ 263 264 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma) 265 { 266 struct pci_controller *pci_ctrl = (struct pci_controller*) pdev->sysdata; 267 resource_size_t ioaddr = pci_resource_start(pdev, bar); 268 269 if (pci_ctrl == 0) 270 return -EINVAL; /* should never happen */ 271 272 /* Convert to an offset within this PCI controller */ 273 ioaddr -= (unsigned long)pci_ctrl->io_space.base; 274 275 vma->vm_pgoff += (ioaddr + pci_ctrl->io_space.start) >> PAGE_SHIFT; 276 return 0; 277 } 278