xref: /openbmc/linux/arch/xtensa/kernel/pci.c (revision 1ab142d4) 
1 /*
2  * arch/xtensa/kernel/pci.c
3  *
4  * PCI bios-type initialisation for PCI machines
5  *
6  * This program is free software; you can redistribute  it and/or modify it
7  * under  the terms of  the GNU General  Public License as published by the
8  * Free Software Foundation;  either version 2 of the  License, or (at your
9  * option) any later version.
10  *
11  * Copyright (C) 2001-2005 Tensilica Inc.
12  *
13  * Based largely on work from Cort (ppc/kernel/pci.c)
14  * IO functions copied from sparc.
15  *
16  * Chris Zankel <chris@zankel.net>
17  *
18  */
19 
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/sched.h>
26 #include <linux/errno.h>
27 #include <linux/bootmem.h>
28 
29 #include <asm/pci-bridge.h>
30 #include <asm/platform.h>
31 
32 #undef DEBUG
33 
34 #ifdef DEBUG
35 #define DBG(x...) printk(x)
36 #else
37 #define DBG(x...)
38 #endif
39 
40 /* PCI Controller */
41 
42 
43 /*
44  * pcibios_alloc_controller
45  * pcibios_enable_device
46  * pcibios_fixups
47  * pcibios_align_resource
48  * pcibios_fixup_bus
49  * pcibios_setup
50  * pci_bus_add_device
51  * pci_mmap_page_range
52  */
53 
54 struct pci_controller* pci_ctrl_head;
55 struct pci_controller** pci_ctrl_tail = &pci_ctrl_head;
56 
57 static int pci_bus_count;
58 
59 /*
60  * We need to avoid collisions with `mirrored' VGA ports
61  * and other strange ISA hardware, so we always want the
62  * addresses to be allocated in the 0x000-0x0ff region
63  * modulo 0x400.
64  *
65  * Why? Because some silly external IO cards only decode
66  * the low 10 bits of the IO address. The 0x00-0xff region
67  * is reserved for motherboard devices that decode all 16
68  * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
69  * but we want to try to avoid allocating at 0x2900-0x2bff
70  * which might have be mirrored at 0x0100-0x03ff..
71  */
72 resource_size_t
73 pcibios_align_resource(void *data, const struct resource *res,
74 		       resource_size_t size, resource_size_t align)
75 {
76 	struct pci_dev *dev = data;
77 	resource_size_t start = res->start;
78 
79 	if (res->flags & IORESOURCE_IO) {
80 		if (size > 0x100) {
81 			printk(KERN_ERR "PCI: I/O Region %s/%d too large"
82 			       " (%ld bytes)\n", pci_name(dev),
83 			       dev->resource - res, size);
84 		}
85 
86 		if (start & 0x300)
87 			start = (start + 0x3ff) & ~0x3ff;
88 	}
89 
90 	return start;
91 }
92 
93 int
94 pcibios_enable_resources(struct pci_dev *dev, int mask)
95 {
96 	u16 cmd, old_cmd;
97 	int idx;
98 	struct resource *r;
99 
100 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
101 	old_cmd = cmd;
102 	for(idx=0; idx<6; idx++) {
103 		r = &dev->resource[idx];
104 		if (!r->start && r->end) {
105 			printk (KERN_ERR "PCI: Device %s not available because "
106 				"of resource collisions\n", pci_name(dev));
107 			return -EINVAL;
108 		}
109 		if (r->flags & IORESOURCE_IO)
110 			cmd |= PCI_COMMAND_IO;
111 		if (r->flags & IORESOURCE_MEM)
112 			cmd |= PCI_COMMAND_MEMORY;
113 	}
114 	if (dev->resource[PCI_ROM_RESOURCE].start)
115 		cmd |= PCI_COMMAND_MEMORY;
116 	if (cmd != old_cmd) {
117 		printk("PCI: Enabling device %s (%04x -> %04x)\n",
118 			pci_name(dev), old_cmd, cmd);
119 		pci_write_config_word(dev, PCI_COMMAND, cmd);
120 	}
121 	return 0;
122 }
123 
124 struct pci_controller * __init pcibios_alloc_controller(void)
125 {
126 	struct pci_controller *pci_ctrl;
127 
128 	pci_ctrl = (struct pci_controller *)alloc_bootmem(sizeof(*pci_ctrl));
129 	memset(pci_ctrl, 0, sizeof(struct pci_controller));
130 
131 	*pci_ctrl_tail = pci_ctrl;
132 	pci_ctrl_tail = &pci_ctrl->next;
133 
134 	return pci_ctrl;
135 }
136 
137 static void __init pci_controller_apertures(struct pci_controller *pci_ctrl,
138 					    struct list_head *resources)
139 {
140 	struct resource *res;
141 	unsigned long io_offset;
142 	int i;
143 
144 	io_offset = (unsigned long)pci_ctrl->io_space.base;
145 	res = &pci_ctrl->io_resource;
146 	if (!res->flags) {
147 		if (io_offset)
148 			printk (KERN_ERR "I/O resource not set for host"
149 				" bridge %d\n", pci_ctrl->index);
150 		res->start = 0;
151 		res->end = IO_SPACE_LIMIT;
152 		res->flags = IORESOURCE_IO;
153 	}
154 	res->start += io_offset;
155 	res->end += io_offset;
156 	pci_add_resource(resources, res);
157 
158 	for (i = 0; i < 3; i++) {
159 		res = &pci_ctrl->mem_resources[i];
160 		if (!res->flags) {
161 			if (i > 0)
162 				continue;
163 			printk(KERN_ERR "Memory resource not set for "
164 			       "host bridge %d\n", pci_ctrl->index);
165 			res->start = 0;
166 			res->end = ~0U;
167 			res->flags = IORESOURCE_MEM;
168 		}
169 		pci_add_resource(resources, res);
170 	}
171 }
172 
173 static int __init pcibios_init(void)
174 {
175 	struct pci_controller *pci_ctrl;
176 	struct list_head resources;
177 	struct pci_bus *bus;
178 	int next_busno = 0, i;
179 
180 	printk("PCI: Probing PCI hardware\n");
181 
182 	/* Scan all of the recorded PCI controllers.  */
183 	for (pci_ctrl = pci_ctrl_head; pci_ctrl; pci_ctrl = pci_ctrl->next) {
184 		pci_ctrl->last_busno = 0xff;
185 		INIT_LIST_HEAD(&resources);
186 		pci_controller_apertures(pci_ctrl, &resources);
187 		bus = pci_scan_root_bus(NULL, pci_ctrl->first_busno,
188 					pci_ctrl->ops, pci_ctrl, &resources);
189 		pci_ctrl->bus = bus;
190 		pci_ctrl->last_busno = bus->subordinate;
191 		if (next_busno <= pci_ctrl->last_busno)
192 			next_busno = pci_ctrl->last_busno+1;
193 	}
194 	pci_bus_count = next_busno;
195 
196 	return platform_pcibios_fixup();
197 }
198 
199 subsys_initcall(pcibios_init);
200 
201 void __init pcibios_fixup_bus(struct pci_bus *bus)
202 {
203 	struct pci_controller *pci_ctrl = bus->sysdata;
204 	struct resource *res;
205 	unsigned long io_offset;
206 	int i;
207 
208 	io_offset = (unsigned long)pci_ctrl->io_space.base;
209 	if (bus->parent) {
210 		/* This is a subordinate bridge */
211 		pci_read_bridge_bases(bus);
212 
213 		for (i = 0; i < 4; i++) {
214 			if ((res = bus->resource[i]) == NULL || !res->flags)
215 				continue;
216 			if (io_offset && (res->flags & IORESOURCE_IO)) {
217 				res->start += io_offset;
218 				res->end += io_offset;
219 			}
220 		}
221 	}
222 }
223 
224 char __init *pcibios_setup(char *str)
225 {
226 	return str;
227 }
228 
229 void pcibios_set_master(struct pci_dev *dev)
230 {
231 	/* No special bus mastering setup handling */
232 }
233 
234 /* the next one is stolen from the alpha port... */
235 
236 void __init
237 pcibios_update_irq(struct pci_dev *dev, int irq)
238 {
239 	pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
240 }
241 
242 int pcibios_enable_device(struct pci_dev *dev, int mask)
243 {
244 	u16 cmd, old_cmd;
245 	int idx;
246 	struct resource *r;
247 
248 	pci_read_config_word(dev, PCI_COMMAND, &cmd);
249 	old_cmd = cmd;
250 	for (idx=0; idx<6; idx++) {
251 		r = &dev->resource[idx];
252 		if (!r->start && r->end) {
253 			printk(KERN_ERR "PCI: Device %s not available because "
254 			       "of resource collisions\n", pci_name(dev));
255 			return -EINVAL;
256 		}
257 		if (r->flags & IORESOURCE_IO)
258 			cmd |= PCI_COMMAND_IO;
259 		if (r->flags & IORESOURCE_MEM)
260 			cmd |= PCI_COMMAND_MEMORY;
261 	}
262 	if (cmd != old_cmd) {
263 		printk("PCI: Enabling device %s (%04x -> %04x)\n",
264 		       pci_name(dev), old_cmd, cmd);
265 		pci_write_config_word(dev, PCI_COMMAND, cmd);
266 	}
267 
268 	return 0;
269 }
270 
271 #ifdef CONFIG_PROC_FS
272 
273 /*
274  * Return the index of the PCI controller for device pdev.
275  */
276 
277 int
278 pci_controller_num(struct pci_dev *dev)
279 {
280 	struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
281 	return pci_ctrl->index;
282 }
283 
284 #endif /* CONFIG_PROC_FS */
285 
286 /*
287  * Platform support for /proc/bus/pci/X/Y mmap()s,
288  * modelled on the sparc64 implementation by Dave Miller.
289  *  -- paulus.
290  */
291 
292 /*
293  * Adjust vm_pgoff of VMA such that it is the physical page offset
294  * corresponding to the 32-bit pci bus offset for DEV requested by the user.
295  *
296  * Basically, the user finds the base address for his device which he wishes
297  * to mmap.  They read the 32-bit value from the config space base register,
298  * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
299  * offset parameter of mmap on /proc/bus/pci/XXX for that device.
300  *
301  * Returns negative error code on failure, zero on success.
302  */
303 static __inline__ int
304 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
305 		       enum pci_mmap_state mmap_state)
306 {
307 	struct pci_controller *pci_ctrl = (struct pci_controller*) dev->sysdata;
308 	unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
309 	unsigned long io_offset = 0;
310 	int i, res_bit;
311 
312 	if (pci_ctrl == 0)
313 		return -EINVAL;		/* should never happen */
314 
315 	/* If memory, add on the PCI bridge address offset */
316 	if (mmap_state == pci_mmap_mem) {
317 		res_bit = IORESOURCE_MEM;
318 	} else {
319 		io_offset = (unsigned long)pci_ctrl->io_space.base;
320 		offset += io_offset;
321 		res_bit = IORESOURCE_IO;
322 	}
323 
324 	/*
325 	 * Check that the offset requested corresponds to one of the
326 	 * resources of the device.
327 	 */
328 	for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
329 		struct resource *rp = &dev->resource[i];
330 		int flags = rp->flags;
331 
332 		/* treat ROM as memory (should be already) */
333 		if (i == PCI_ROM_RESOURCE)
334 			flags |= IORESOURCE_MEM;
335 
336 		/* Active and same type? */
337 		if ((flags & res_bit) == 0)
338 			continue;
339 
340 		/* In the range of this resource? */
341 		if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
342 			continue;
343 
344 		/* found it! construct the final physical address */
345 		if (mmap_state == pci_mmap_io)
346 			offset += pci_ctrl->io_space.start - io_offset;
347 		vma->vm_pgoff = offset >> PAGE_SHIFT;
348 		return 0;
349 	}
350 
351 	return -EINVAL;
352 }
353 
354 /*
355  * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
356  * device mapping.
357  */
358 static __inline__ void
359 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
360 		      enum pci_mmap_state mmap_state, int write_combine)
361 {
362 	int prot = pgprot_val(vma->vm_page_prot);
363 
364 	/* Set to write-through */
365 	prot &= ~_PAGE_NO_CACHE;
366 #if 0
367 	if (!write_combine)
368 		prot |= _PAGE_WRITETHRU;
369 #endif
370 	vma->vm_page_prot = __pgprot(prot);
371 }
372 
373 /*
374  * Perform the actual remap of the pages for a PCI device mapping, as
375  * appropriate for this architecture.  The region in the process to map
376  * is described by vm_start and vm_end members of VMA, the base physical
377  * address is found in vm_pgoff.
378  * The pci device structure is provided so that architectures may make mapping
379  * decisions on a per-device or per-bus basis.
380  *
381  * Returns a negative error code on failure, zero on success.
382  */
383 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
384 			enum pci_mmap_state mmap_state,
385 			int write_combine)
386 {
387 	int ret;
388 
389 	ret = __pci_mmap_make_offset(dev, vma, mmap_state);
390 	if (ret < 0)
391 		return ret;
392 
393 	__pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
394 
395 	ret = io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
396 			         vma->vm_end - vma->vm_start,vma->vm_page_prot);
397 
398 	return ret;
399 }
400