1 /* 2 * linux/arch/xtensa/kernel/irq.c 3 * 4 * Xtensa built-in interrupt controller and some generic functions copied 5 * from i386. 6 * 7 * Copyright (C) 2002 - 2013 Tensilica, Inc. 8 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar 9 * 10 * 11 * Chris Zankel <chris@zankel.net> 12 * Kevin Chea 13 * 14 */ 15 16 #include <linux/module.h> 17 #include <linux/seq_file.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/kernel_stat.h> 21 #include <linux/irqchip.h> 22 #include <linux/irqchip/xtensa-mx.h> 23 #include <linux/irqchip/xtensa-pic.h> 24 #include <linux/irqdomain.h> 25 #include <linux/of.h> 26 27 #include <asm/mxregs.h> 28 #include <linux/uaccess.h> 29 #include <asm/platform.h> 30 31 DECLARE_PER_CPU(unsigned long, nmi_count); 32 33 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs) 34 { 35 int irq = irq_find_mapping(NULL, hwirq); 36 37 #ifdef CONFIG_DEBUG_STACKOVERFLOW 38 /* Debugging check for stack overflow: is there less than 1KB free? */ 39 { 40 unsigned long sp; 41 42 __asm__ __volatile__ ("mov %0, a1\n" : "=a" (sp)); 43 sp &= THREAD_SIZE - 1; 44 45 if (unlikely(sp < (sizeof(thread_info) + 1024))) 46 printk("Stack overflow in do_IRQ: %ld\n", 47 sp - sizeof(struct thread_info)); 48 } 49 #endif 50 generic_handle_irq(irq); 51 } 52 53 int arch_show_interrupts(struct seq_file *p, int prec) 54 { 55 unsigned cpu __maybe_unused; 56 #ifdef CONFIG_SMP 57 show_ipi_list(p, prec); 58 #endif 59 #if XTENSA_FAKE_NMI 60 seq_printf(p, "%*s:", prec, "NMI"); 61 for_each_online_cpu(cpu) 62 seq_printf(p, " %10lu", per_cpu(nmi_count, cpu)); 63 seq_puts(p, " Non-maskable interrupts\n"); 64 #endif 65 return 0; 66 } 67 68 int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize, 69 unsigned long int_irq, unsigned long ext_irq, 70 unsigned long *out_hwirq, unsigned int *out_type) 71 { 72 if (WARN_ON(intsize < 1 || intsize > 2)) 73 return -EINVAL; 74 if (intsize == 2 && intspec[1] == 1) { 75 int_irq = xtensa_map_ext_irq(ext_irq); 76 if (int_irq < XCHAL_NUM_INTERRUPTS) 77 *out_hwirq = int_irq; 78 else 79 return -EINVAL; 80 } else { 81 *out_hwirq = int_irq; 82 } 83 *out_type = IRQ_TYPE_NONE; 84 return 0; 85 } 86 87 int xtensa_irq_map(struct irq_domain *d, unsigned int irq, 88 irq_hw_number_t hw) 89 { 90 struct irq_chip *irq_chip = d->host_data; 91 u32 mask = 1 << hw; 92 93 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) { 94 irq_set_chip_and_handler_name(irq, irq_chip, 95 handle_simple_irq, "level"); 96 irq_set_status_flags(irq, IRQ_LEVEL); 97 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) { 98 irq_set_chip_and_handler_name(irq, irq_chip, 99 handle_edge_irq, "edge"); 100 irq_clear_status_flags(irq, IRQ_LEVEL); 101 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) { 102 irq_set_chip_and_handler_name(irq, irq_chip, 103 handle_level_irq, "level"); 104 irq_set_status_flags(irq, IRQ_LEVEL); 105 } else if (mask & XCHAL_INTTYPE_MASK_TIMER) { 106 irq_set_chip_and_handler_name(irq, irq_chip, 107 handle_percpu_irq, "timer"); 108 irq_clear_status_flags(irq, IRQ_LEVEL); 109 #ifdef XCHAL_INTTYPE_MASK_PROFILING 110 } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) { 111 irq_set_chip_and_handler_name(irq, irq_chip, 112 handle_percpu_irq, "profiling"); 113 irq_set_status_flags(irq, IRQ_LEVEL); 114 #endif 115 } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 116 /* XCHAL_INTTYPE_MASK_NMI */ 117 irq_set_chip_and_handler_name(irq, irq_chip, 118 handle_level_irq, "level"); 119 irq_set_status_flags(irq, IRQ_LEVEL); 120 } 121 return 0; 122 } 123 124 unsigned xtensa_map_ext_irq(unsigned ext_irq) 125 { 126 unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE | 127 XCHAL_INTTYPE_MASK_EXTERN_LEVEL; 128 unsigned i; 129 130 for (i = 0; mask; ++i, mask >>= 1) { 131 if ((mask & 1) && ext_irq-- == 0) 132 return i; 133 } 134 return XCHAL_NUM_INTERRUPTS; 135 } 136 137 unsigned xtensa_get_ext_irq_no(unsigned irq) 138 { 139 unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE | 140 XCHAL_INTTYPE_MASK_EXTERN_LEVEL) & 141 ((1u << irq) - 1); 142 return hweight32(mask); 143 } 144 145 void __init init_IRQ(void) 146 { 147 #ifdef CONFIG_OF 148 irqchip_init(); 149 #else 150 #ifdef CONFIG_HAVE_SMP 151 xtensa_mx_init_legacy(NULL); 152 #else 153 xtensa_pic_init_legacy(NULL); 154 #endif 155 #endif 156 157 #ifdef CONFIG_SMP 158 ipi_init(); 159 #endif 160 variant_init_irq(); 161 } 162 163 #ifdef CONFIG_HOTPLUG_CPU 164 /* 165 * The CPU has been marked offline. Migrate IRQs off this CPU. If 166 * the affinity settings do not allow other CPUs, force them onto any 167 * available CPU. 168 */ 169 void migrate_irqs(void) 170 { 171 unsigned int i, cpu = smp_processor_id(); 172 173 for_each_active_irq(i) { 174 struct irq_data *data = irq_get_irq_data(i); 175 struct cpumask *mask; 176 unsigned int newcpu; 177 178 if (irqd_is_per_cpu(data)) 179 continue; 180 181 mask = irq_data_get_affinity_mask(data); 182 if (!cpumask_test_cpu(cpu, mask)) 183 continue; 184 185 newcpu = cpumask_any_and(mask, cpu_online_mask); 186 187 if (newcpu >= nr_cpu_ids) { 188 pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n", 189 i, cpu); 190 191 cpumask_setall(mask); 192 } 193 irq_set_affinity(i, mask); 194 } 195 } 196 #endif /* CONFIG_HOTPLUG_CPU */ 197