1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * linux/arch/xtensa/kernel/irq.c 4 * 5 * Xtensa built-in interrupt controller and some generic functions copied 6 * from i386. 7 * 8 * Copyright (C) 2002 - 2013 Tensilica, Inc. 9 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar 10 * 11 * 12 * Chris Zankel <chris@zankel.net> 13 * Kevin Chea 14 * 15 */ 16 17 #include <linux/module.h> 18 #include <linux/seq_file.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/kernel_stat.h> 22 #include <linux/irqchip.h> 23 #include <linux/irqchip/xtensa-mx.h> 24 #include <linux/irqchip/xtensa-pic.h> 25 #include <linux/irqdomain.h> 26 #include <linux/of.h> 27 28 #include <asm/mxregs.h> 29 #include <linux/uaccess.h> 30 #include <asm/platform.h> 31 32 DECLARE_PER_CPU(unsigned long, nmi_count); 33 34 asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs) 35 { 36 #ifdef CONFIG_DEBUG_STACKOVERFLOW 37 /* Debugging check for stack overflow: is there less than 1KB free? */ 38 { 39 unsigned long sp = current_stack_pointer; 40 41 sp &= THREAD_SIZE - 1; 42 43 if (unlikely(sp < (sizeof(thread_info) + 1024))) 44 printk("Stack overflow in do_IRQ: %ld\n", 45 sp - sizeof(struct thread_info)); 46 } 47 #endif 48 generic_handle_domain_irq(NULL, hwirq); 49 } 50 51 int arch_show_interrupts(struct seq_file *p, int prec) 52 { 53 unsigned cpu __maybe_unused; 54 #ifdef CONFIG_SMP 55 show_ipi_list(p, prec); 56 #endif 57 #if XTENSA_FAKE_NMI 58 seq_printf(p, "%*s:", prec, "NMI"); 59 for_each_online_cpu(cpu) 60 seq_printf(p, " %10lu", per_cpu(nmi_count, cpu)); 61 seq_puts(p, " Non-maskable interrupts\n"); 62 #endif 63 return 0; 64 } 65 66 int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize, 67 unsigned long int_irq, unsigned long ext_irq, 68 unsigned long *out_hwirq, unsigned int *out_type) 69 { 70 if (WARN_ON(intsize < 1 || intsize > 2)) 71 return -EINVAL; 72 if (intsize == 2 && intspec[1] == 1) { 73 int_irq = xtensa_map_ext_irq(ext_irq); 74 if (int_irq < XCHAL_NUM_INTERRUPTS) 75 *out_hwirq = int_irq; 76 else 77 return -EINVAL; 78 } else { 79 *out_hwirq = int_irq; 80 } 81 *out_type = IRQ_TYPE_NONE; 82 return 0; 83 } 84 85 int xtensa_irq_map(struct irq_domain *d, unsigned int irq, 86 irq_hw_number_t hw) 87 { 88 struct irq_chip *irq_chip = d->host_data; 89 u32 mask = 1 << hw; 90 91 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) { 92 irq_set_chip_and_handler_name(irq, irq_chip, 93 handle_simple_irq, "level"); 94 irq_set_status_flags(irq, IRQ_LEVEL); 95 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) { 96 irq_set_chip_and_handler_name(irq, irq_chip, 97 handle_edge_irq, "edge"); 98 irq_clear_status_flags(irq, IRQ_LEVEL); 99 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) { 100 irq_set_chip_and_handler_name(irq, irq_chip, 101 handle_level_irq, "level"); 102 irq_set_status_flags(irq, IRQ_LEVEL); 103 } else if (mask & XCHAL_INTTYPE_MASK_TIMER) { 104 irq_set_chip_and_handler_name(irq, irq_chip, 105 handle_percpu_irq, "timer"); 106 irq_clear_status_flags(irq, IRQ_LEVEL); 107 #ifdef XCHAL_INTTYPE_MASK_PROFILING 108 } else if (mask & XCHAL_INTTYPE_MASK_PROFILING) { 109 irq_set_chip_and_handler_name(irq, irq_chip, 110 handle_percpu_irq, "profiling"); 111 irq_set_status_flags(irq, IRQ_LEVEL); 112 #endif 113 } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 114 /* XCHAL_INTTYPE_MASK_NMI */ 115 irq_set_chip_and_handler_name(irq, irq_chip, 116 handle_level_irq, "level"); 117 irq_set_status_flags(irq, IRQ_LEVEL); 118 } 119 return 0; 120 } 121 122 unsigned xtensa_map_ext_irq(unsigned ext_irq) 123 { 124 unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE | 125 XCHAL_INTTYPE_MASK_EXTERN_LEVEL; 126 unsigned i; 127 128 for (i = 0; mask; ++i, mask >>= 1) { 129 if ((mask & 1) && ext_irq-- == 0) 130 return i; 131 } 132 return XCHAL_NUM_INTERRUPTS; 133 } 134 135 unsigned xtensa_get_ext_irq_no(unsigned irq) 136 { 137 unsigned mask = (XCHAL_INTTYPE_MASK_EXTERN_EDGE | 138 XCHAL_INTTYPE_MASK_EXTERN_LEVEL) & 139 ((1u << irq) - 1); 140 return hweight32(mask); 141 } 142 143 void __init init_IRQ(void) 144 { 145 #ifdef CONFIG_USE_OF 146 irqchip_init(); 147 #else 148 #ifdef CONFIG_HAVE_SMP 149 xtensa_mx_init_legacy(NULL); 150 #else 151 xtensa_pic_init_legacy(NULL); 152 #endif 153 #endif 154 155 #ifdef CONFIG_SMP 156 ipi_init(); 157 #endif 158 } 159 160 #ifdef CONFIG_HOTPLUG_CPU 161 /* 162 * The CPU has been marked offline. Migrate IRQs off this CPU. If 163 * the affinity settings do not allow other CPUs, force them onto any 164 * available CPU. 165 */ 166 void migrate_irqs(void) 167 { 168 unsigned int i, cpu = smp_processor_id(); 169 170 for_each_active_irq(i) { 171 struct irq_data *data = irq_get_irq_data(i); 172 struct cpumask *mask; 173 unsigned int newcpu; 174 175 if (irqd_is_per_cpu(data)) 176 continue; 177 178 mask = irq_data_get_affinity_mask(data); 179 if (!cpumask_test_cpu(cpu, mask)) 180 continue; 181 182 newcpu = cpumask_any_and(mask, cpu_online_mask); 183 184 if (newcpu >= nr_cpu_ids) { 185 pr_info_ratelimited("IRQ%u no longer affine to CPU%u\n", 186 i, cpu); 187 188 cpumask_setall(mask); 189 } 190 irq_set_affinity(i, mask); 191 } 192 } 193 #endif /* CONFIG_HOTPLUG_CPU */ 194