1/* 2 * Low-level exception handling 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2004 - 2008 by Tensilica Inc. 9 * Copyright (C) 2015 Cadence Design Systems Inc. 10 * 11 * Chris Zankel <chris@zankel.net> 12 * 13 */ 14 15#include <linux/linkage.h> 16#include <asm/asm-offsets.h> 17#include <asm/asmmacro.h> 18#include <asm/processor.h> 19#include <asm/coprocessor.h> 20#include <asm/thread_info.h> 21#include <asm/asm-uaccess.h> 22#include <asm/unistd.h> 23#include <asm/ptrace.h> 24#include <asm/current.h> 25#include <asm/pgtable.h> 26#include <asm/page.h> 27#include <asm/signal.h> 28#include <asm/tlbflush.h> 29#include <variant/tie-asm.h> 30 31/* Unimplemented features. */ 32 33#undef KERNEL_STACK_OVERFLOW_CHECK 34 35/* Not well tested. 36 * 37 * - fast_coprocessor 38 */ 39 40/* 41 * Macro to find first bit set in WINDOWBASE from the left + 1 42 * 43 * 100....0 -> 1 44 * 010....0 -> 2 45 * 000....1 -> WSBITS 46 */ 47 48 .macro ffs_ws bit mask 49 50#if XCHAL_HAVE_NSA 51 nsau \bit, \mask # 32-WSBITS ... 31 (32 iff 0) 52 addi \bit, \bit, WSBITS - 32 + 1 # uppest bit set -> return 1 53#else 54 movi \bit, WSBITS 55#if WSBITS > 16 56 _bltui \mask, 0x10000, 99f 57 addi \bit, \bit, -16 58 extui \mask, \mask, 16, 16 59#endif 60#if WSBITS > 8 6199: _bltui \mask, 0x100, 99f 62 addi \bit, \bit, -8 63 srli \mask, \mask, 8 64#endif 6599: _bltui \mask, 0x10, 99f 66 addi \bit, \bit, -4 67 srli \mask, \mask, 4 6899: _bltui \mask, 0x4, 99f 69 addi \bit, \bit, -2 70 srli \mask, \mask, 2 7199: _bltui \mask, 0x2, 99f 72 addi \bit, \bit, -1 7399: 74 75#endif 76 .endm 77 78 79 .macro irq_save flags tmp 80#if XTENSA_FAKE_NMI 81#if defined(CONFIG_DEBUG_KERNEL) && (LOCKLEVEL | TOPLEVEL) >= XCHAL_DEBUGLEVEL 82 rsr \flags, ps 83 extui \tmp, \flags, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH 84 bgei \tmp, LOCKLEVEL, 99f 85 rsil \tmp, LOCKLEVEL 8699: 87#else 88 movi \tmp, LOCKLEVEL 89 rsr \flags, ps 90 or \flags, \flags, \tmp 91 xsr \flags, ps 92 rsync 93#endif 94#else 95 rsil \flags, LOCKLEVEL 96#endif 97 .endm 98 99/* ----------------- DEFAULT FIRST LEVEL EXCEPTION HANDLERS ----------------- */ 100 101/* 102 * First-level exception handler for user exceptions. 103 * Save some special registers, extra states and all registers in the AR 104 * register file that were in use in the user task, and jump to the common 105 * exception code. 106 * We save SAR (used to calculate WMASK), and WB and WS (we don't have to 107 * save them for kernel exceptions). 108 * 109 * Entry condition for user_exception: 110 * 111 * a0: trashed, original value saved on stack (PT_AREG0) 112 * a1: a1 113 * a2: new stack pointer, original value in depc 114 * a3: a3 115 * depc: a2, original value saved on stack (PT_DEPC) 116 * excsave1: dispatch table 117 * 118 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 119 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 120 * 121 * Entry condition for _user_exception: 122 * 123 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC 124 * excsave has been restored, and 125 * stack pointer (a1) has been set. 126 * 127 * Note: _user_exception might be at an odd address. Don't use call0..call12 128 */ 129 .literal_position 130 131ENTRY(user_exception) 132 133 /* Save a1, a2, a3, and set SP. */ 134 135 rsr a0, depc 136 s32i a1, a2, PT_AREG1 137 s32i a0, a2, PT_AREG2 138 s32i a3, a2, PT_AREG3 139 mov a1, a2 140 141 .globl _user_exception 142_user_exception: 143 144 /* Save SAR and turn off single stepping */ 145 146 movi a2, 0 147 wsr a2, depc # terminate user stack trace with 0 148 rsr a3, sar 149 xsr a2, icountlevel 150 s32i a3, a1, PT_SAR 151 s32i a2, a1, PT_ICOUNTLEVEL 152 153#if XCHAL_HAVE_THREADPTR 154 rur a2, threadptr 155 s32i a2, a1, PT_THREADPTR 156#endif 157 158 /* Rotate ws so that the current windowbase is at bit0. */ 159 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ 160 161 rsr a2, windowbase 162 rsr a3, windowstart 163 ssr a2 164 s32i a2, a1, PT_WINDOWBASE 165 s32i a3, a1, PT_WINDOWSTART 166 slli a2, a3, 32-WSBITS 167 src a2, a3, a2 168 srli a2, a2, 32-WSBITS 169 s32i a2, a1, PT_WMASK # needed for restoring registers 170 171 /* Save only live registers. */ 172 173 _bbsi.l a2, 1, 1f 174 s32i a4, a1, PT_AREG4 175 s32i a5, a1, PT_AREG5 176 s32i a6, a1, PT_AREG6 177 s32i a7, a1, PT_AREG7 178 _bbsi.l a2, 2, 1f 179 s32i a8, a1, PT_AREG8 180 s32i a9, a1, PT_AREG9 181 s32i a10, a1, PT_AREG10 182 s32i a11, a1, PT_AREG11 183 _bbsi.l a2, 3, 1f 184 s32i a12, a1, PT_AREG12 185 s32i a13, a1, PT_AREG13 186 s32i a14, a1, PT_AREG14 187 s32i a15, a1, PT_AREG15 188 _bnei a2, 1, 1f # only one valid frame? 189 190 /* Only one valid frame, skip saving regs. */ 191 192 j 2f 193 194 /* Save the remaining registers. 195 * We have to save all registers up to the first '1' from 196 * the right, except the current frame (bit 0). 197 * Assume a2 is: 001001000110001 198 * All register frames starting from the top field to the marked '1' 199 * must be saved. 200 */ 201 2021: addi a3, a2, -1 # eliminate '1' in bit 0: yyyyxxww0 203 neg a3, a3 # yyyyxxww0 -> YYYYXXWW1+1 204 and a3, a3, a2 # max. only one bit is set 205 206 /* Find number of frames to save */ 207 208 ffs_ws a0, a3 # number of frames to the '1' from left 209 210 /* Store information into WMASK: 211 * bits 0..3: xxx1 masked lower 4 bits of the rotated windowstart, 212 * bits 4...: number of valid 4-register frames 213 */ 214 215 slli a3, a0, 4 # number of frames to save in bits 8..4 216 extui a2, a2, 0, 4 # mask for the first 16 registers 217 or a2, a3, a2 218 s32i a2, a1, PT_WMASK # needed when we restore the reg-file 219 220 /* Save 4 registers at a time */ 221 2221: rotw -1 223 s32i a0, a5, PT_AREG_END - 16 224 s32i a1, a5, PT_AREG_END - 12 225 s32i a2, a5, PT_AREG_END - 8 226 s32i a3, a5, PT_AREG_END - 4 227 addi a0, a4, -1 228 addi a1, a5, -16 229 _bnez a0, 1b 230 231 /* WINDOWBASE still in SAR! */ 232 233 rsr a2, sar # original WINDOWBASE 234 movi a3, 1 235 ssl a2 236 sll a3, a3 237 wsr a3, windowstart # set corresponding WINDOWSTART bit 238 wsr a2, windowbase # and WINDOWSTART 239 rsync 240 241 /* We are back to the original stack pointer (a1) */ 242 2432: /* Now, jump to the common exception handler. */ 244 245 j common_exception 246 247ENDPROC(user_exception) 248 249/* 250 * First-level exit handler for kernel exceptions 251 * Save special registers and the live window frame. 252 * Note: Even though we changes the stack pointer, we don't have to do a 253 * MOVSP here, as we do that when we return from the exception. 254 * (See comment in the kernel exception exit code) 255 * 256 * Entry condition for kernel_exception: 257 * 258 * a0: trashed, original value saved on stack (PT_AREG0) 259 * a1: a1 260 * a2: new stack pointer, original in DEPC 261 * a3: a3 262 * depc: a2, original value saved on stack (PT_DEPC) 263 * excsave_1: dispatch table 264 * 265 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 266 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 267 * 268 * Entry condition for _kernel_exception: 269 * 270 * a0-a3 and depc have been saved to PT_AREG0...PT_AREG3 and PT_DEPC 271 * excsave has been restored, and 272 * stack pointer (a1) has been set. 273 * 274 * Note: _kernel_exception might be at an odd address. Don't use call0..call12 275 */ 276 277ENTRY(kernel_exception) 278 279 /* Save a1, a2, a3, and set SP. */ 280 281 rsr a0, depc # get a2 282 s32i a1, a2, PT_AREG1 283 s32i a0, a2, PT_AREG2 284 s32i a3, a2, PT_AREG3 285 mov a1, a2 286 287 .globl _kernel_exception 288_kernel_exception: 289 290 /* Save SAR and turn off single stepping */ 291 292 movi a2, 0 293 rsr a3, sar 294 xsr a2, icountlevel 295 s32i a3, a1, PT_SAR 296 s32i a2, a1, PT_ICOUNTLEVEL 297 298 /* Rotate ws so that the current windowbase is at bit0. */ 299 /* Assume ws = xxwww1yyyy. Rotate ws right, so that a2 = yyyyxxwww1 */ 300 301 rsr a2, windowbase # don't need to save these, we only 302 rsr a3, windowstart # need shifted windowstart: windowmask 303 ssr a2 304 slli a2, a3, 32-WSBITS 305 src a2, a3, a2 306 srli a2, a2, 32-WSBITS 307 s32i a2, a1, PT_WMASK # needed for kernel_exception_exit 308 309 /* Save only the live window-frame */ 310 311 _bbsi.l a2, 1, 1f 312 s32i a4, a1, PT_AREG4 313 s32i a5, a1, PT_AREG5 314 s32i a6, a1, PT_AREG6 315 s32i a7, a1, PT_AREG7 316 _bbsi.l a2, 2, 1f 317 s32i a8, a1, PT_AREG8 318 s32i a9, a1, PT_AREG9 319 s32i a10, a1, PT_AREG10 320 s32i a11, a1, PT_AREG11 321 _bbsi.l a2, 3, 1f 322 s32i a12, a1, PT_AREG12 323 s32i a13, a1, PT_AREG13 324 s32i a14, a1, PT_AREG14 325 s32i a15, a1, PT_AREG15 326 327 _bnei a2, 1, 1f 328 329 /* Copy spill slots of a0 and a1 to imitate movsp 330 * in order to keep exception stack continuous 331 */ 332 l32i a3, a1, PT_SIZE 333 l32i a0, a1, PT_SIZE + 4 334 s32e a3, a1, -16 335 s32e a0, a1, -12 3361: 337 l32i a0, a1, PT_AREG0 # restore saved a0 338 wsr a0, depc 339 340#ifdef KERNEL_STACK_OVERFLOW_CHECK 341 342 /* Stack overflow check, for debugging */ 343 extui a2, a1, TASK_SIZE_BITS,XX 344 movi a3, SIZE?? 345 _bge a2, a3, out_of_stack_panic 346 347#endif 348 349/* 350 * This is the common exception handler. 351 * We get here from the user exception handler or simply by falling through 352 * from the kernel exception handler. 353 * Save the remaining special registers, switch to kernel mode, and jump 354 * to the second-level exception handler. 355 * 356 */ 357 358common_exception: 359 360 /* Save some registers, disable loops and clear the syscall flag. */ 361 362 rsr a2, debugcause 363 rsr a3, epc1 364 s32i a2, a1, PT_DEBUGCAUSE 365 s32i a3, a1, PT_PC 366 367 movi a2, NO_SYSCALL 368 rsr a3, excvaddr 369 s32i a2, a1, PT_SYSCALL 370 movi a2, 0 371 s32i a3, a1, PT_EXCVADDR 372#if XCHAL_HAVE_LOOPS 373 xsr a2, lcount 374 s32i a2, a1, PT_LCOUNT 375#endif 376 377 /* It is now save to restore the EXC_TABLE_FIXUP variable. */ 378 379 rsr a2, exccause 380 movi a3, 0 381 rsr a0, excsave1 382 s32i a2, a1, PT_EXCCAUSE 383 s32i a3, a0, EXC_TABLE_FIXUP 384 385 /* All unrecoverable states are saved on stack, now, and a1 is valid. 386 * Now we can allow exceptions again. In case we've got an interrupt 387 * PS.INTLEVEL is set to LOCKLEVEL disabling furhter interrupts, 388 * otherwise it's left unchanged. 389 * 390 * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X) 391 */ 392 393 rsr a3, ps 394 s32i a3, a1, PT_PS # save ps 395 396#if XTENSA_FAKE_NMI 397 /* Correct PS needs to be saved in the PT_PS: 398 * - in case of exception or level-1 interrupt it's in the PS, 399 * and is already saved. 400 * - in case of medium level interrupt it's in the excsave2. 401 */ 402 movi a0, EXCCAUSE_MAPPED_NMI 403 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH 404 beq a2, a0, .Lmedium_level_irq 405 bnei a2, EXCCAUSE_LEVEL1_INTERRUPT, .Lexception 406 beqz a3, .Llevel1_irq # level-1 IRQ sets ps.intlevel to 0 407 408.Lmedium_level_irq: 409 rsr a0, excsave2 410 s32i a0, a1, PT_PS # save medium-level interrupt ps 411 bgei a3, LOCKLEVEL, .Lexception 412 413.Llevel1_irq: 414 movi a3, LOCKLEVEL 415 416.Lexception: 417 movi a0, PS_WOE_MASK 418 or a3, a3, a0 419#else 420 addi a2, a2, -EXCCAUSE_LEVEL1_INTERRUPT 421 movi a0, LOCKLEVEL 422 extui a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH 423 # a3 = PS.INTLEVEL 424 moveqz a3, a0, a2 # a3 = LOCKLEVEL iff interrupt 425 movi a2, PS_WOE_MASK 426 or a3, a3, a2 427 rsr a2, exccause 428#endif 429 430 /* restore return address (or 0 if return to userspace) */ 431 rsr a0, depc 432 wsr a3, ps 433 rsync # PS.WOE => rsync => overflow 434 435 /* Save lbeg, lend */ 436#if XCHAL_HAVE_LOOPS 437 rsr a4, lbeg 438 rsr a3, lend 439 s32i a4, a1, PT_LBEG 440 s32i a3, a1, PT_LEND 441#endif 442 443 /* Save SCOMPARE1 */ 444 445#if XCHAL_HAVE_S32C1I 446 rsr a3, scompare1 447 s32i a3, a1, PT_SCOMPARE1 448#endif 449 450 /* Save optional registers. */ 451 452 save_xtregs_opt a1 a3 a4 a5 a6 a7 PT_XTREGS_OPT 453 454 /* Go to second-level dispatcher. Set up parameters to pass to the 455 * exception handler and call the exception handler. 456 */ 457 458 rsr a4, excsave1 459 mov a6, a1 # pass stack frame 460 mov a7, a2 # pass EXCCAUSE 461 addx4 a4, a2, a4 462 l32i a4, a4, EXC_TABLE_DEFAULT # load handler 463 464 /* Call the second-level handler */ 465 466 callx4 a4 467 468 /* Jump here for exception exit */ 469 .global common_exception_return 470common_exception_return: 471 472#if XTENSA_FAKE_NMI 473 l32i a2, a1, PT_EXCCAUSE 474 movi a3, EXCCAUSE_MAPPED_NMI 475 beq a2, a3, .LNMIexit 476#endif 4771: 478 irq_save a2, a3 479#ifdef CONFIG_TRACE_IRQFLAGS 480 call4 trace_hardirqs_off 481#endif 482 483 /* Jump if we are returning from kernel exceptions. */ 484 485 l32i a3, a1, PT_PS 486 GET_THREAD_INFO(a2, a1) 487 l32i a4, a2, TI_FLAGS 488 _bbci.l a3, PS_UM_BIT, 6f 489 490 /* Specific to a user exception exit: 491 * We need to check some flags for signal handling and rescheduling, 492 * and have to restore WB and WS, extra states, and all registers 493 * in the register file that were in use in the user task. 494 * Note that we don't disable interrupts here. 495 */ 496 497 _bbsi.l a4, TIF_NEED_RESCHED, 3f 498 _bbsi.l a4, TIF_NOTIFY_RESUME, 2f 499 _bbci.l a4, TIF_SIGPENDING, 5f 500 5012: l32i a4, a1, PT_DEPC 502 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f 503 504 /* Call do_signal() */ 505 506#ifdef CONFIG_TRACE_IRQFLAGS 507 call4 trace_hardirqs_on 508#endif 509 rsil a2, 0 510 mov a6, a1 511 call4 do_notify_resume # int do_notify_resume(struct pt_regs*) 512 j 1b 513 5143: /* Reschedule */ 515 516#ifdef CONFIG_TRACE_IRQFLAGS 517 call4 trace_hardirqs_on 518#endif 519 rsil a2, 0 520 call4 schedule # void schedule (void) 521 j 1b 522 523#ifdef CONFIG_PREEMPTION 5246: 525 _bbci.l a4, TIF_NEED_RESCHED, 4f 526 527 /* Check current_thread_info->preempt_count */ 528 529 l32i a4, a2, TI_PRE_COUNT 530 bnez a4, 4f 531 call4 preempt_schedule_irq 532 j 4f 533#endif 534 535#if XTENSA_FAKE_NMI 536.LNMIexit: 537 l32i a3, a1, PT_PS 538 _bbci.l a3, PS_UM_BIT, 4f 539#endif 540 5415: 542#ifdef CONFIG_HAVE_HW_BREAKPOINT 543 _bbci.l a4, TIF_DB_DISABLED, 7f 544 call4 restore_dbreak 5457: 546#endif 547#ifdef CONFIG_DEBUG_TLB_SANITY 548 l32i a4, a1, PT_DEPC 549 bgeui a4, VALID_DOUBLE_EXCEPTION_ADDRESS, 4f 550 call4 check_tlb_sanity 551#endif 5526: 5534: 554#ifdef CONFIG_TRACE_IRQFLAGS 555 extui a4, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH 556 bgei a4, LOCKLEVEL, 1f 557 call4 trace_hardirqs_on 5581: 559#endif 560 /* Restore optional registers. */ 561 562 load_xtregs_opt a1 a2 a4 a5 a6 a7 PT_XTREGS_OPT 563 564 /* Restore SCOMPARE1 */ 565 566#if XCHAL_HAVE_S32C1I 567 l32i a2, a1, PT_SCOMPARE1 568 wsr a2, scompare1 569#endif 570 wsr a3, ps /* disable interrupts */ 571 572 _bbci.l a3, PS_UM_BIT, kernel_exception_exit 573 574user_exception_exit: 575 576 /* Restore the state of the task and return from the exception. */ 577 578 /* Switch to the user thread WINDOWBASE. Save SP temporarily in DEPC */ 579 580 l32i a2, a1, PT_WINDOWBASE 581 l32i a3, a1, PT_WINDOWSTART 582 wsr a1, depc # use DEPC as temp storage 583 wsr a3, windowstart # restore WINDOWSTART 584 ssr a2 # preserve user's WB in the SAR 585 wsr a2, windowbase # switch to user's saved WB 586 rsync 587 rsr a1, depc # restore stack pointer 588 l32i a2, a1, PT_WMASK # register frames saved (in bits 4...9) 589 rotw -1 # we restore a4..a7 590 _bltui a6, 16, 1f # only have to restore current window? 591 592 /* The working registers are a0 and a3. We are restoring to 593 * a4..a7. Be careful not to destroy what we have just restored. 594 * Note: wmask has the format YYYYM: 595 * Y: number of registers saved in groups of 4 596 * M: 4 bit mask of first 16 registers 597 */ 598 599 mov a2, a6 600 mov a3, a5 601 6022: rotw -1 # a0..a3 become a4..a7 603 addi a3, a7, -4*4 # next iteration 604 addi a2, a6, -16 # decrementing Y in WMASK 605 l32i a4, a3, PT_AREG_END + 0 606 l32i a5, a3, PT_AREG_END + 4 607 l32i a6, a3, PT_AREG_END + 8 608 l32i a7, a3, PT_AREG_END + 12 609 _bgeui a2, 16, 2b 610 611 /* Clear unrestored registers (don't leak anything to user-land */ 612 6131: rsr a0, windowbase 614 rsr a3, sar 615 sub a3, a0, a3 616 beqz a3, 2f 617 extui a3, a3, 0, WBBITS 618 6191: rotw -1 620 addi a3, a7, -1 621 movi a4, 0 622 movi a5, 0 623 movi a6, 0 624 movi a7, 0 625 bgei a3, 1, 1b 626 627 /* We are back were we were when we started. 628 * Note: a2 still contains WMASK (if we've returned to the original 629 * frame where we had loaded a2), or at least the lower 4 bits 630 * (if we have restored WSBITS-1 frames). 631 */ 632 6332: 634#if XCHAL_HAVE_THREADPTR 635 l32i a3, a1, PT_THREADPTR 636 wur a3, threadptr 637#endif 638 639 j common_exception_exit 640 641 /* This is the kernel exception exit. 642 * We avoided to do a MOVSP when we entered the exception, but we 643 * have to do it here. 644 */ 645 646kernel_exception_exit: 647 648 /* Check if we have to do a movsp. 649 * 650 * We only have to do a movsp if the previous window-frame has 651 * been spilled to the *temporary* exception stack instead of the 652 * task's stack. This is the case if the corresponding bit in 653 * WINDOWSTART for the previous window-frame was set before 654 * (not spilled) but is zero now (spilled). 655 * If this bit is zero, all other bits except the one for the 656 * current window frame are also zero. So, we can use a simple test: 657 * 'and' WINDOWSTART and WINDOWSTART-1: 658 * 659 * (XXXXXX1[0]* - 1) AND XXXXXX1[0]* = XXXXXX0[0]* 660 * 661 * The result is zero only if one bit was set. 662 * 663 * (Note: We might have gone through several task switches before 664 * we come back to the current task, so WINDOWBASE might be 665 * different from the time the exception occurred.) 666 */ 667 668 /* Test WINDOWSTART before and after the exception. 669 * We actually have WMASK, so we only have to test if it is 1 or not. 670 */ 671 672 l32i a2, a1, PT_WMASK 673 _beqi a2, 1, common_exception_exit # Spilled before exception,jump 674 675 /* Test WINDOWSTART now. If spilled, do the movsp */ 676 677 rsr a3, windowstart 678 addi a0, a3, -1 679 and a3, a3, a0 680 _bnez a3, common_exception_exit 681 682 /* Do a movsp (we returned from a call4, so we have at least a0..a7) */ 683 684 addi a0, a1, -16 685 l32i a3, a0, 0 686 l32i a4, a0, 4 687 s32i a3, a1, PT_SIZE+0 688 s32i a4, a1, PT_SIZE+4 689 l32i a3, a0, 8 690 l32i a4, a0, 12 691 s32i a3, a1, PT_SIZE+8 692 s32i a4, a1, PT_SIZE+12 693 694 /* Common exception exit. 695 * We restore the special register and the current window frame, and 696 * return from the exception. 697 * 698 * Note: We expect a2 to hold PT_WMASK 699 */ 700 701common_exception_exit: 702 703 /* Restore address registers. */ 704 705 _bbsi.l a2, 1, 1f 706 l32i a4, a1, PT_AREG4 707 l32i a5, a1, PT_AREG5 708 l32i a6, a1, PT_AREG6 709 l32i a7, a1, PT_AREG7 710 _bbsi.l a2, 2, 1f 711 l32i a8, a1, PT_AREG8 712 l32i a9, a1, PT_AREG9 713 l32i a10, a1, PT_AREG10 714 l32i a11, a1, PT_AREG11 715 _bbsi.l a2, 3, 1f 716 l32i a12, a1, PT_AREG12 717 l32i a13, a1, PT_AREG13 718 l32i a14, a1, PT_AREG14 719 l32i a15, a1, PT_AREG15 720 721 /* Restore PC, SAR */ 722 7231: l32i a2, a1, PT_PC 724 l32i a3, a1, PT_SAR 725 wsr a2, epc1 726 wsr a3, sar 727 728 /* Restore LBEG, LEND, LCOUNT */ 729#if XCHAL_HAVE_LOOPS 730 l32i a2, a1, PT_LBEG 731 l32i a3, a1, PT_LEND 732 wsr a2, lbeg 733 l32i a2, a1, PT_LCOUNT 734 wsr a3, lend 735 wsr a2, lcount 736#endif 737 738 /* We control single stepping through the ICOUNTLEVEL register. */ 739 740 l32i a2, a1, PT_ICOUNTLEVEL 741 movi a3, -2 742 wsr a2, icountlevel 743 wsr a3, icount 744 745 /* Check if it was double exception. */ 746 747 l32i a0, a1, PT_DEPC 748 l32i a3, a1, PT_AREG3 749 l32i a2, a1, PT_AREG2 750 _bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f 751 752 /* Restore a0...a3 and return */ 753 754 l32i a0, a1, PT_AREG0 755 l32i a1, a1, PT_AREG1 756 rfe 757 7581: wsr a0, depc 759 l32i a0, a1, PT_AREG0 760 l32i a1, a1, PT_AREG1 761 rfde 762 763ENDPROC(kernel_exception) 764 765/* 766 * Debug exception handler. 767 * 768 * Currently, we don't support KGDB, so only user application can be debugged. 769 * 770 * When we get here, a0 is trashed and saved to excsave[debuglevel] 771 */ 772 773 .literal_position 774 775ENTRY(debug_exception) 776 777 rsr a0, SREG_EPS + XCHAL_DEBUGLEVEL 778 bbsi.l a0, PS_EXCM_BIT, 1f # exception mode 779 780 /* Set EPC1 and EXCCAUSE */ 781 782 wsr a2, depc # save a2 temporarily 783 rsr a2, SREG_EPC + XCHAL_DEBUGLEVEL 784 wsr a2, epc1 785 786 movi a2, EXCCAUSE_MAPPED_DEBUG 787 wsr a2, exccause 788 789 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ 790 791 movi a2, 1 << PS_EXCM_BIT 792 or a2, a0, a2 793 wsr a2, ps 794 795 /* Switch to kernel/user stack, restore jump vector, and save a0 */ 796 797 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode 798 799 addi a2, a1, -16-PT_SIZE # assume kernel stack 8003: 801 l32i a0, a3, DT_DEBUG_SAVE 802 s32i a1, a2, PT_AREG1 803 s32i a0, a2, PT_AREG0 804 movi a0, 0 805 s32i a0, a2, PT_DEPC # mark it as a regular exception 806 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL 807 xsr a0, depc 808 s32i a3, a2, PT_AREG3 809 s32i a0, a2, PT_AREG2 810 mov a1, a2 811 812 /* Debug exception is handled as an exception, so interrupts will 813 * likely be enabled in the common exception handler. Disable 814 * preemption if we have HW breakpoints to preserve DEBUGCAUSE.DBNUM 815 * meaning. 816 */ 817#if defined(CONFIG_PREEMPT_COUNT) && defined(CONFIG_HAVE_HW_BREAKPOINT) 818 GET_THREAD_INFO(a2, a1) 819 l32i a3, a2, TI_PRE_COUNT 820 addi a3, a3, 1 821 s32i a3, a2, TI_PRE_COUNT 822#endif 823 824 rsr a2, ps 825 bbsi.l a2, PS_UM_BIT, _user_exception 826 j _kernel_exception 827 8282: rsr a2, excsave1 829 l32i a2, a2, EXC_TABLE_KSTK # load kernel stack pointer 830 j 3b 831 832#ifdef CONFIG_HAVE_HW_BREAKPOINT 833 /* Debug exception while in exception mode. This may happen when 834 * window overflow/underflow handler or fast exception handler hits 835 * data breakpoint, in which case save and disable all data 836 * breakpoints, single-step faulting instruction and restore data 837 * breakpoints. 838 */ 8391: 840 bbci.l a0, PS_UM_BIT, 1b # jump if kernel mode 841 842 rsr a0, debugcause 843 bbsi.l a0, DEBUGCAUSE_DBREAK_BIT, .Ldebug_save_dbreak 844 845 .set _index, 0 846 .rept XCHAL_NUM_DBREAK 847 l32i a0, a3, DT_DBREAKC_SAVE + _index * 4 848 wsr a0, SREG_DBREAKC + _index 849 .set _index, _index + 1 850 .endr 851 852 l32i a0, a3, DT_ICOUNT_LEVEL_SAVE 853 wsr a0, icountlevel 854 855 l32i a0, a3, DT_ICOUNT_SAVE 856 xsr a0, icount 857 858 l32i a0, a3, DT_DEBUG_SAVE 859 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL 860 rfi XCHAL_DEBUGLEVEL 861 862.Ldebug_save_dbreak: 863 .set _index, 0 864 .rept XCHAL_NUM_DBREAK 865 movi a0, 0 866 xsr a0, SREG_DBREAKC + _index 867 s32i a0, a3, DT_DBREAKC_SAVE + _index * 4 868 .set _index, _index + 1 869 .endr 870 871 movi a0, XCHAL_EXCM_LEVEL + 1 872 xsr a0, icountlevel 873 s32i a0, a3, DT_ICOUNT_LEVEL_SAVE 874 875 movi a0, 0xfffffffe 876 xsr a0, icount 877 s32i a0, a3, DT_ICOUNT_SAVE 878 879 l32i a0, a3, DT_DEBUG_SAVE 880 xsr a3, SREG_EXCSAVE + XCHAL_DEBUGLEVEL 881 rfi XCHAL_DEBUGLEVEL 882#else 883 /* Debug exception while in exception mode. Should not happen. */ 8841: j 1b // FIXME!! 885#endif 886 887ENDPROC(debug_exception) 888 889/* 890 * We get here in case of an unrecoverable exception. 891 * The only thing we can do is to be nice and print a panic message. 892 * We only produce a single stack frame for panic, so ??? 893 * 894 * 895 * Entry conditions: 896 * 897 * - a0 contains the caller address; original value saved in excsave1. 898 * - the original a0 contains a valid return address (backtrace) or 0. 899 * - a2 contains a valid stackpointer 900 * 901 * Notes: 902 * 903 * - If the stack pointer could be invalid, the caller has to setup a 904 * dummy stack pointer (e.g. the stack of the init_task) 905 * 906 * - If the return address could be invalid, the caller has to set it 907 * to 0, so the backtrace would stop. 908 * 909 */ 910 .align 4 911unrecoverable_text: 912 .ascii "Unrecoverable error in exception handler\0" 913 914 .literal_position 915 916ENTRY(unrecoverable_exception) 917 918 movi a0, 1 919 movi a1, 0 920 921 wsr a0, windowstart 922 wsr a1, windowbase 923 rsync 924 925 movi a1, PS_WOE_MASK | LOCKLEVEL 926 wsr a1, ps 927 rsync 928 929 movi a1, init_task 930 movi a0, 0 931 addi a1, a1, PT_REGS_OFFSET 932 933 movi a6, unrecoverable_text 934 call4 panic 935 9361: j 1b 937 938ENDPROC(unrecoverable_exception) 939 940/* -------------------------- FAST EXCEPTION HANDLERS ----------------------- */ 941 942 __XTENSA_HANDLER 943 .literal_position 944 945/* 946 * Fast-handler for alloca exceptions 947 * 948 * The ALLOCA handler is entered when user code executes the MOVSP 949 * instruction and the caller's frame is not in the register file. 950 * 951 * This algorithm was taken from the Ross Morley's RTOS Porting Layer: 952 * 953 * /home/ross/rtos/porting/XtensaRTOS-PortingLayer-20090507/xtensa_vectors.S 954 * 955 * It leverages the existing window spill/fill routines and their support for 956 * double exceptions. The 'movsp' instruction will only cause an exception if 957 * the next window needs to be loaded. In fact this ALLOCA exception may be 958 * replaced at some point by changing the hardware to do a underflow exception 959 * of the proper size instead. 960 * 961 * This algorithm simply backs out the register changes started by the user 962 * excpetion handler, makes it appear that we have started a window underflow 963 * by rotating the window back and then setting the old window base (OWB) in 964 * the 'ps' register with the rolled back window base. The 'movsp' instruction 965 * will be re-executed and this time since the next window frames is in the 966 * active AR registers it won't cause an exception. 967 * 968 * If the WindowUnderflow code gets a TLB miss the page will get mapped 969 * the the partial windeowUnderflow will be handeled in the double exception 970 * handler. 971 * 972 * Entry condition: 973 * 974 * a0: trashed, original value saved on stack (PT_AREG0) 975 * a1: a1 976 * a2: new stack pointer, original in DEPC 977 * a3: a3 978 * depc: a2, original value saved on stack (PT_DEPC) 979 * excsave_1: dispatch table 980 * 981 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 982 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 983 */ 984 985ENTRY(fast_alloca) 986 rsr a0, windowbase 987 rotw -1 988 rsr a2, ps 989 extui a3, a2, PS_OWB_SHIFT, PS_OWB_WIDTH 990 xor a3, a3, a4 991 l32i a4, a6, PT_AREG0 992 l32i a1, a6, PT_DEPC 993 rsr a6, depc 994 wsr a1, depc 995 slli a3, a3, PS_OWB_SHIFT 996 xor a2, a2, a3 997 wsr a2, ps 998 rsync 999 1000 _bbci.l a4, 31, 4f 1001 rotw -1 1002 _bbci.l a8, 30, 8f 1003 rotw -1 1004 j _WindowUnderflow12 10058: j _WindowUnderflow8 10064: j _WindowUnderflow4 1007ENDPROC(fast_alloca) 1008 1009#ifdef CONFIG_USER_ABI_CALL0_PROBE 1010/* 1011 * fast illegal instruction handler. 1012 * 1013 * This is used to fix up user PS.WOE on the exception caused 1014 * by the first opcode related to register window. If PS.WOE is 1015 * already set it goes directly to the common user exception handler. 1016 * 1017 * Entry condition: 1018 * 1019 * a0: trashed, original value saved on stack (PT_AREG0) 1020 * a1: a1 1021 * a2: new stack pointer, original in DEPC 1022 * a3: a3 1023 * depc: a2, original value saved on stack (PT_DEPC) 1024 * excsave_1: dispatch table 1025 */ 1026 1027ENTRY(fast_illegal_instruction_user) 1028 1029 rsr a0, ps 1030 bbsi.l a0, PS_WOE_BIT, 1f 1031 s32i a3, a2, PT_AREG3 1032 movi a3, PS_WOE_MASK 1033 or a0, a0, a3 1034 wsr a0, ps 1035 l32i a3, a2, PT_AREG3 1036 l32i a0, a2, PT_AREG0 1037 rsr a2, depc 1038 rfe 10391: 1040 call0 user_exception 1041 1042ENDPROC(fast_illegal_instruction_user) 1043#endif 1044 1045 /* 1046 * fast system calls. 1047 * 1048 * WARNING: The kernel doesn't save the entire user context before 1049 * handling a fast system call. These functions are small and short, 1050 * usually offering some functionality not available to user tasks. 1051 * 1052 * BE CAREFUL TO PRESERVE THE USER'S CONTEXT. 1053 * 1054 * Entry condition: 1055 * 1056 * a0: trashed, original value saved on stack (PT_AREG0) 1057 * a1: a1 1058 * a2: new stack pointer, original in DEPC 1059 * a3: a3 1060 * depc: a2, original value saved on stack (PT_DEPC) 1061 * excsave_1: dispatch table 1062 */ 1063 1064ENTRY(fast_syscall_user) 1065 1066 /* Skip syscall. */ 1067 1068 rsr a0, epc1 1069 addi a0, a0, 3 1070 wsr a0, epc1 1071 1072 l32i a0, a2, PT_DEPC 1073 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, fast_syscall_unrecoverable 1074 1075 rsr a0, depc # get syscall-nr 1076 _beqz a0, fast_syscall_spill_registers 1077 _beqi a0, __NR_xtensa, fast_syscall_xtensa 1078 1079 call0 user_exception 1080 1081ENDPROC(fast_syscall_user) 1082 1083ENTRY(fast_syscall_unrecoverable) 1084 1085 /* Restore all states. */ 1086 1087 l32i a0, a2, PT_AREG0 # restore a0 1088 xsr a2, depc # restore a2, depc 1089 1090 wsr a0, excsave1 1091 call0 unrecoverable_exception 1092 1093ENDPROC(fast_syscall_unrecoverable) 1094 1095/* 1096 * sysxtensa syscall handler 1097 * 1098 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused); 1099 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused); 1100 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused); 1101 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval); 1102 * a2 a6 a3 a4 a5 1103 * 1104 * Entry condition: 1105 * 1106 * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0) 1107 * a1: a1 1108 * a2: new stack pointer, original in a0 and DEPC 1109 * a3: a3 1110 * a4..a15: unchanged 1111 * depc: a2, original value saved on stack (PT_DEPC) 1112 * excsave_1: dispatch table 1113 * 1114 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 1115 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 1116 * 1117 * Note: we don't have to save a2; a2 holds the return value 1118 */ 1119 1120 .literal_position 1121 1122#ifdef CONFIG_FAST_SYSCALL_XTENSA 1123 1124ENTRY(fast_syscall_xtensa) 1125 1126 s32i a7, a2, PT_AREG7 # we need an additional register 1127 movi a7, 4 # sizeof(unsigned int) 1128 access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp 1129 1130 _bgeui a6, SYS_XTENSA_COUNT, .Lill 1131 _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP, .Lnswp 1132 1133 /* Fall through for ATOMIC_CMP_SWP. */ 1134 1135.Lswp: /* Atomic compare and swap */ 1136 1137EX(.Leac) l32i a0, a3, 0 # read old value 1138 bne a0, a4, 1f # same as old value? jump 1139EX(.Leac) s32i a5, a3, 0 # different, modify value 1140 l32i a7, a2, PT_AREG7 # restore a7 1141 l32i a0, a2, PT_AREG0 # restore a0 1142 movi a2, 1 # and return 1 1143 rfe 1144 11451: l32i a7, a2, PT_AREG7 # restore a7 1146 l32i a0, a2, PT_AREG0 # restore a0 1147 movi a2, 0 # return 0 (note that we cannot set 1148 rfe 1149 1150.Lnswp: /* Atomic set, add, and exg_add. */ 1151 1152EX(.Leac) l32i a7, a3, 0 # orig 1153 addi a6, a6, -SYS_XTENSA_ATOMIC_SET 1154 add a0, a4, a7 # + arg 1155 moveqz a0, a4, a6 # set 1156 addi a6, a6, SYS_XTENSA_ATOMIC_SET 1157EX(.Leac) s32i a0, a3, 0 # write new value 1158 1159 mov a0, a2 1160 mov a2, a7 1161 l32i a7, a0, PT_AREG7 # restore a7 1162 l32i a0, a0, PT_AREG0 # restore a0 1163 rfe 1164 1165.Leac: l32i a7, a2, PT_AREG7 # restore a7 1166 l32i a0, a2, PT_AREG0 # restore a0 1167 movi a2, -EFAULT 1168 rfe 1169 1170.Lill: l32i a7, a2, PT_AREG7 # restore a7 1171 l32i a0, a2, PT_AREG0 # restore a0 1172 movi a2, -EINVAL 1173 rfe 1174 1175ENDPROC(fast_syscall_xtensa) 1176 1177#else /* CONFIG_FAST_SYSCALL_XTENSA */ 1178 1179ENTRY(fast_syscall_xtensa) 1180 1181 l32i a0, a2, PT_AREG0 # restore a0 1182 movi a2, -ENOSYS 1183 rfe 1184 1185ENDPROC(fast_syscall_xtensa) 1186 1187#endif /* CONFIG_FAST_SYSCALL_XTENSA */ 1188 1189 1190/* fast_syscall_spill_registers. 1191 * 1192 * Entry condition: 1193 * 1194 * a0: trashed, original value saved on stack (PT_AREG0) 1195 * a1: a1 1196 * a2: new stack pointer, original in DEPC 1197 * a3: a3 1198 * depc: a2, original value saved on stack (PT_DEPC) 1199 * excsave_1: dispatch table 1200 * 1201 * Note: We assume the stack pointer is EXC_TABLE_KSTK in the fixup handler. 1202 */ 1203 1204#ifdef CONFIG_FAST_SYSCALL_SPILL_REGISTERS 1205 1206ENTRY(fast_syscall_spill_registers) 1207 1208 /* Register a FIXUP handler (pass current wb as a parameter) */ 1209 1210 xsr a3, excsave1 1211 movi a0, fast_syscall_spill_registers_fixup 1212 s32i a0, a3, EXC_TABLE_FIXUP 1213 rsr a0, windowbase 1214 s32i a0, a3, EXC_TABLE_PARAM 1215 xsr a3, excsave1 # restore a3 and excsave_1 1216 1217 /* Save a3, a4 and SAR on stack. */ 1218 1219 rsr a0, sar 1220 s32i a3, a2, PT_AREG3 1221 s32i a0, a2, PT_SAR 1222 1223 /* The spill routine might clobber a4, a7, a8, a11, a12, and a15. */ 1224 1225 s32i a4, a2, PT_AREG4 1226 s32i a7, a2, PT_AREG7 1227 s32i a8, a2, PT_AREG8 1228 s32i a11, a2, PT_AREG11 1229 s32i a12, a2, PT_AREG12 1230 s32i a15, a2, PT_AREG15 1231 1232 /* 1233 * Rotate ws so that the current windowbase is at bit 0. 1234 * Assume ws = xxxwww1yy (www1 current window frame). 1235 * Rotate ws right so that a4 = yyxxxwww1. 1236 */ 1237 1238 rsr a0, windowbase 1239 rsr a3, windowstart # a3 = xxxwww1yy 1240 ssr a0 # holds WB 1241 slli a0, a3, WSBITS 1242 or a3, a3, a0 # a3 = xxxwww1yyxxxwww1yy 1243 srl a3, a3 # a3 = 00xxxwww1yyxxxwww1 1244 1245 /* We are done if there are no more than the current register frame. */ 1246 1247 extui a3, a3, 1, WSBITS-1 # a3 = 0yyxxxwww 1248 movi a0, (1 << (WSBITS-1)) 1249 _beqz a3, .Lnospill # only one active frame? jump 1250 1251 /* We want 1 at the top, so that we return to the current windowbase */ 1252 1253 or a3, a3, a0 # 1yyxxxwww 1254 1255 /* Skip empty frames - get 'oldest' WINDOWSTART-bit. */ 1256 1257 wsr a3, windowstart # save shifted windowstart 1258 neg a0, a3 1259 and a3, a0, a3 # first bit set from right: 000010000 1260 1261 ffs_ws a0, a3 # a0: shifts to skip empty frames 1262 movi a3, WSBITS 1263 sub a0, a3, a0 # WSBITS-a0:number of 0-bits from right 1264 ssr a0 # save in SAR for later. 1265 1266 rsr a3, windowbase 1267 add a3, a3, a0 1268 wsr a3, windowbase 1269 rsync 1270 1271 rsr a3, windowstart 1272 srl a3, a3 # shift windowstart 1273 1274 /* WB is now just one frame below the oldest frame in the register 1275 window. WS is shifted so the oldest frame is in bit 0, thus, WB 1276 and WS differ by one 4-register frame. */ 1277 1278 /* Save frames. Depending what call was used (call4, call8, call12), 1279 * we have to save 4,8. or 12 registers. 1280 */ 1281 1282 1283.Lloop: _bbsi.l a3, 1, .Lc4 1284 _bbci.l a3, 2, .Lc12 1285 1286.Lc8: s32e a4, a13, -16 1287 l32e a4, a5, -12 1288 s32e a8, a4, -32 1289 s32e a5, a13, -12 1290 s32e a6, a13, -8 1291 s32e a7, a13, -4 1292 s32e a9, a4, -28 1293 s32e a10, a4, -24 1294 s32e a11, a4, -20 1295 srli a11, a3, 2 # shift windowbase by 2 1296 rotw 2 1297 _bnei a3, 1, .Lloop 1298 j .Lexit 1299 1300.Lc4: s32e a4, a9, -16 1301 s32e a5, a9, -12 1302 s32e a6, a9, -8 1303 s32e a7, a9, -4 1304 1305 srli a7, a3, 1 1306 rotw 1 1307 _bnei a3, 1, .Lloop 1308 j .Lexit 1309 1310.Lc12: _bbci.l a3, 3, .Linvalid_mask # bit 2 shouldn't be zero! 1311 1312 /* 12-register frame (call12) */ 1313 1314 l32e a0, a5, -12 1315 s32e a8, a0, -48 1316 mov a8, a0 1317 1318 s32e a9, a8, -44 1319 s32e a10, a8, -40 1320 s32e a11, a8, -36 1321 s32e a12, a8, -32 1322 s32e a13, a8, -28 1323 s32e a14, a8, -24 1324 s32e a15, a8, -20 1325 srli a15, a3, 3 1326 1327 /* The stack pointer for a4..a7 is out of reach, so we rotate the 1328 * window, grab the stackpointer, and rotate back. 1329 * Alternatively, we could also use the following approach, but that 1330 * makes the fixup routine much more complicated: 1331 * rotw 1 1332 * s32e a0, a13, -16 1333 * ... 1334 * rotw 2 1335 */ 1336 1337 rotw 1 1338 mov a4, a13 1339 rotw -1 1340 1341 s32e a4, a8, -16 1342 s32e a5, a8, -12 1343 s32e a6, a8, -8 1344 s32e a7, a8, -4 1345 1346 rotw 3 1347 1348 _beqi a3, 1, .Lexit 1349 j .Lloop 1350 1351.Lexit: 1352 1353 /* Done. Do the final rotation and set WS */ 1354 1355 rotw 1 1356 rsr a3, windowbase 1357 ssl a3 1358 movi a3, 1 1359 sll a3, a3 1360 wsr a3, windowstart 1361.Lnospill: 1362 1363 /* Advance PC, restore registers and SAR, and return from exception. */ 1364 1365 l32i a3, a2, PT_SAR 1366 l32i a0, a2, PT_AREG0 1367 wsr a3, sar 1368 l32i a3, a2, PT_AREG3 1369 1370 /* Restore clobbered registers. */ 1371 1372 l32i a4, a2, PT_AREG4 1373 l32i a7, a2, PT_AREG7 1374 l32i a8, a2, PT_AREG8 1375 l32i a11, a2, PT_AREG11 1376 l32i a12, a2, PT_AREG12 1377 l32i a15, a2, PT_AREG15 1378 1379 movi a2, 0 1380 rfe 1381 1382.Linvalid_mask: 1383 1384 /* We get here because of an unrecoverable error in the window 1385 * registers, so set up a dummy frame and kill the user application. 1386 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. 1387 */ 1388 1389 movi a0, 1 1390 movi a1, 0 1391 1392 wsr a0, windowstart 1393 wsr a1, windowbase 1394 rsync 1395 1396 movi a0, 0 1397 1398 rsr a3, excsave1 1399 l32i a1, a3, EXC_TABLE_KSTK 1400 1401 movi a4, PS_WOE_MASK | LOCKLEVEL 1402 wsr a4, ps 1403 rsync 1404 1405 movi a6, SIGSEGV 1406 call4 do_exit 1407 1408 /* shouldn't return, so panic */ 1409 1410 wsr a0, excsave1 1411 call0 unrecoverable_exception # should not return 14121: j 1b 1413 1414 1415ENDPROC(fast_syscall_spill_registers) 1416 1417/* Fixup handler. 1418 * 1419 * We get here if the spill routine causes an exception, e.g. tlb miss. 1420 * We basically restore WINDOWBASE and WINDOWSTART to the condition when 1421 * we entered the spill routine and jump to the user exception handler. 1422 * 1423 * Note that we only need to restore the bits in windowstart that have not 1424 * been spilled yet by the _spill_register routine. Luckily, a3 contains a 1425 * rotated windowstart with only those bits set for frames that haven't been 1426 * spilled yet. Because a3 is rotated such that bit 0 represents the register 1427 * frame for the current windowbase - 1, we need to rotate a3 left by the 1428 * value of the current windowbase + 1 and move it to windowstart. 1429 * 1430 * a0: value of depc, original value in depc 1431 * a2: trashed, original value in EXC_TABLE_DOUBLE_SAVE 1432 * a3: exctable, original value in excsave1 1433 */ 1434 1435ENTRY(fast_syscall_spill_registers_fixup) 1436 1437 rsr a2, windowbase # get current windowbase (a2 is saved) 1438 xsr a0, depc # restore depc and a0 1439 ssl a2 # set shift (32 - WB) 1440 1441 /* We need to make sure the current registers (a0-a3) are preserved. 1442 * To do this, we simply set the bit for the current window frame 1443 * in WS, so that the exception handlers save them to the task stack. 1444 * 1445 * Note: we use a3 to set the windowbase, so we take a special care 1446 * of it, saving it in the original _spill_registers frame across 1447 * the exception handler call. 1448 */ 1449 1450 xsr a3, excsave1 # get spill-mask 1451 slli a3, a3, 1 # shift left by one 1452 addi a3, a3, 1 # set the bit for the current window frame 1453 1454 slli a2, a3, 32-WSBITS 1455 src a2, a3, a2 # a2 = xxwww1yyxxxwww1yy...... 1456 wsr a2, windowstart # set corrected windowstart 1457 1458 srli a3, a3, 1 1459 rsr a2, excsave1 1460 l32i a2, a2, EXC_TABLE_DOUBLE_SAVE # restore a2 1461 xsr a2, excsave1 1462 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE # save a3 1463 l32i a3, a2, EXC_TABLE_PARAM # original WB (in user task) 1464 xsr a2, excsave1 1465 1466 /* Return to the original (user task) WINDOWBASE. 1467 * We leave the following frame behind: 1468 * a0, a1, a2 same 1469 * a3: trashed (saved in EXC_TABLE_DOUBLE_SAVE) 1470 * depc: depc (we have to return to that address) 1471 * excsave_1: exctable 1472 */ 1473 1474 wsr a3, windowbase 1475 rsync 1476 1477 /* We are now in the original frame when we entered _spill_registers: 1478 * a0: return address 1479 * a1: used, stack pointer 1480 * a2: kernel stack pointer 1481 * a3: available 1482 * depc: exception address 1483 * excsave: exctable 1484 * Note: This frame might be the same as above. 1485 */ 1486 1487 /* Setup stack pointer. */ 1488 1489 addi a2, a2, -PT_USER_SIZE 1490 s32i a0, a2, PT_AREG0 1491 1492 /* Make sure we return to this fixup handler. */ 1493 1494 movi a3, fast_syscall_spill_registers_fixup_return 1495 s32i a3, a2, PT_DEPC # setup depc 1496 1497 /* Jump to the exception handler. */ 1498 1499 rsr a3, excsave1 1500 rsr a0, exccause 1501 addx4 a0, a0, a3 # find entry in table 1502 l32i a0, a0, EXC_TABLE_FAST_USER # load handler 1503 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE 1504 jx a0 1505 1506ENDPROC(fast_syscall_spill_registers_fixup) 1507 1508ENTRY(fast_syscall_spill_registers_fixup_return) 1509 1510 /* When we return here, all registers have been restored (a2: DEPC) */ 1511 1512 wsr a2, depc # exception address 1513 1514 /* Restore fixup handler. */ 1515 1516 rsr a2, excsave1 1517 s32i a3, a2, EXC_TABLE_DOUBLE_SAVE 1518 movi a3, fast_syscall_spill_registers_fixup 1519 s32i a3, a2, EXC_TABLE_FIXUP 1520 rsr a3, windowbase 1521 s32i a3, a2, EXC_TABLE_PARAM 1522 l32i a2, a2, EXC_TABLE_KSTK 1523 1524 /* Load WB at the time the exception occurred. */ 1525 1526 rsr a3, sar # WB is still in SAR 1527 neg a3, a3 1528 wsr a3, windowbase 1529 rsync 1530 1531 rsr a3, excsave1 1532 l32i a3, a3, EXC_TABLE_DOUBLE_SAVE 1533 1534 rfde 1535 1536ENDPROC(fast_syscall_spill_registers_fixup_return) 1537 1538#else /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */ 1539 1540ENTRY(fast_syscall_spill_registers) 1541 1542 l32i a0, a2, PT_AREG0 # restore a0 1543 movi a2, -ENOSYS 1544 rfe 1545 1546ENDPROC(fast_syscall_spill_registers) 1547 1548#endif /* CONFIG_FAST_SYSCALL_SPILL_REGISTERS */ 1549 1550#ifdef CONFIG_MMU 1551/* 1552 * We should never get here. Bail out! 1553 */ 1554 1555ENTRY(fast_second_level_miss_double_kernel) 1556 15571: 1558 call0 unrecoverable_exception # should not return 15591: j 1b 1560 1561ENDPROC(fast_second_level_miss_double_kernel) 1562 1563/* First-level entry handler for user, kernel, and double 2nd-level 1564 * TLB miss exceptions. Note that for now, user and kernel miss 1565 * exceptions share the same entry point and are handled identically. 1566 * 1567 * An old, less-efficient C version of this function used to exist. 1568 * We include it below, interleaved as comments, for reference. 1569 * 1570 * Entry condition: 1571 * 1572 * a0: trashed, original value saved on stack (PT_AREG0) 1573 * a1: a1 1574 * a2: new stack pointer, original in DEPC 1575 * a3: a3 1576 * depc: a2, original value saved on stack (PT_DEPC) 1577 * excsave_1: dispatch table 1578 * 1579 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 1580 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 1581 */ 1582 1583ENTRY(fast_second_level_miss) 1584 1585 /* Save a1 and a3. Note: we don't expect a double exception. */ 1586 1587 s32i a1, a2, PT_AREG1 1588 s32i a3, a2, PT_AREG3 1589 1590 /* We need to map the page of PTEs for the user task. Find 1591 * the pointer to that page. Also, it's possible for tsk->mm 1592 * to be NULL while tsk->active_mm is nonzero if we faulted on 1593 * a vmalloc address. In that rare case, we must use 1594 * active_mm instead to avoid a fault in this handler. See 1595 * 1596 * http://mail.nl.linux.org/linux-mm/2002-08/msg00258.html 1597 * (or search Internet on "mm vs. active_mm") 1598 * 1599 * if (!mm) 1600 * mm = tsk->active_mm; 1601 * pgd = pgd_offset (mm, regs->excvaddr); 1602 * pmd = pmd_offset (pgd, regs->excvaddr); 1603 * pmdval = *pmd; 1604 */ 1605 1606 GET_CURRENT(a1,a2) 1607 l32i a0, a1, TASK_MM # tsk->mm 1608 beqz a0, 9f 1609 16108: rsr a3, excvaddr # fault address 1611 _PGD_OFFSET(a0, a3, a1) 1612 l32i a0, a0, 0 # read pmdval 1613 beqz a0, 2f 1614 1615 /* Read ptevaddr and convert to top of page-table page. 1616 * 1617 * vpnval = read_ptevaddr_register() & PAGE_MASK; 1618 * vpnval += DTLB_WAY_PGTABLE; 1619 * pteval = mk_pte (virt_to_page(pmd_val(pmdval)), PAGE_KERNEL); 1620 * write_dtlb_entry (pteval, vpnval); 1621 * 1622 * The messy computation for 'pteval' above really simplifies 1623 * into the following: 1624 * 1625 * pteval = ((pmdval - PAGE_OFFSET + PHYS_OFFSET) & PAGE_MASK) 1626 * | PAGE_DIRECTORY 1627 */ 1628 1629 movi a1, (PHYS_OFFSET - PAGE_OFFSET) & 0xffffffff 1630 add a0, a0, a1 # pmdval - PAGE_OFFSET 1631 extui a1, a0, 0, PAGE_SHIFT # ... & PAGE_MASK 1632 xor a0, a0, a1 1633 1634 movi a1, _PAGE_DIRECTORY 1635 or a0, a0, a1 # ... | PAGE_DIRECTORY 1636 1637 /* 1638 * We utilize all three wired-ways (7-9) to hold pmd translations. 1639 * Memory regions are mapped to the DTLBs according to bits 28 and 29. 1640 * This allows to map the three most common regions to three different 1641 * DTLBs: 1642 * 0,1 -> way 7 program (0040.0000) and virtual (c000.0000) 1643 * 2 -> way 8 shared libaries (2000.0000) 1644 * 3 -> way 0 stack (3000.0000) 1645 */ 1646 1647 extui a3, a3, 28, 2 # addr. bit 28 and 29 0,1,2,3 1648 rsr a1, ptevaddr 1649 addx2 a3, a3, a3 # -> 0,3,6,9 1650 srli a1, a1, PAGE_SHIFT 1651 extui a3, a3, 2, 2 # -> 0,0,1,2 1652 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK 1653 addi a3, a3, DTLB_WAY_PGD 1654 add a1, a1, a3 # ... + way_number 1655 16563: wdtlb a0, a1 1657 dsync 1658 1659 /* Exit critical section. */ 1660 16614: rsr a3, excsave1 1662 movi a0, 0 1663 s32i a0, a3, EXC_TABLE_FIXUP 1664 1665 /* Restore the working registers, and return. */ 1666 1667 l32i a0, a2, PT_AREG0 1668 l32i a1, a2, PT_AREG1 1669 l32i a3, a2, PT_AREG3 1670 l32i a2, a2, PT_DEPC 1671 1672 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f 1673 1674 /* Restore excsave1 and return. */ 1675 1676 rsr a2, depc 1677 rfe 1678 1679 /* Return from double exception. */ 1680 16811: xsr a2, depc 1682 esync 1683 rfde 1684 16859: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0 1686 bnez a0, 8b 1687 1688 /* Even more unlikely case active_mm == 0. 1689 * We can get here with NMI in the middle of context_switch that 1690 * touches vmalloc area. 1691 */ 1692 movi a0, init_mm 1693 j 8b 1694 1695#if (DCACHE_WAY_SIZE > PAGE_SIZE) 1696 16972: /* Special case for cache aliasing. 1698 * We (should) only get here if a clear_user_page, copy_user_page 1699 * or the aliased cache flush functions got preemptively interrupted 1700 * by another task. Re-establish temporary mapping to the 1701 * TLBTEMP_BASE areas. 1702 */ 1703 1704 /* We shouldn't be in a double exception */ 1705 1706 l32i a0, a2, PT_DEPC 1707 bgeui a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 2f 1708 1709 /* Make sure the exception originated in the special functions */ 1710 1711 movi a0, __tlbtemp_mapping_start 1712 rsr a3, epc1 1713 bltu a3, a0, 2f 1714 movi a0, __tlbtemp_mapping_end 1715 bgeu a3, a0, 2f 1716 1717 /* Check if excvaddr was in one of the TLBTEMP_BASE areas. */ 1718 1719 movi a3, TLBTEMP_BASE_1 1720 rsr a0, excvaddr 1721 bltu a0, a3, 2f 1722 1723 addi a1, a0, -TLBTEMP_SIZE 1724 bgeu a1, a3, 2f 1725 1726 /* Check if we have to restore an ITLB mapping. */ 1727 1728 movi a1, __tlbtemp_mapping_itlb 1729 rsr a3, epc1 1730 sub a3, a3, a1 1731 1732 /* Calculate VPN */ 1733 1734 movi a1, PAGE_MASK 1735 and a1, a1, a0 1736 1737 /* Jump for ITLB entry */ 1738 1739 bgez a3, 1f 1740 1741 /* We can use up to two TLBTEMP areas, one for src and one for dst. */ 1742 1743 extui a3, a0, PAGE_SHIFT + DCACHE_ALIAS_ORDER, 1 1744 add a1, a3, a1 1745 1746 /* PPN is in a6 for the first TLBTEMP area and in a7 for the second. */ 1747 1748 mov a0, a6 1749 movnez a0, a7, a3 1750 j 3b 1751 1752 /* ITLB entry. We only use dst in a6. */ 1753 17541: witlb a6, a1 1755 isync 1756 j 4b 1757 1758 1759#endif // DCACHE_WAY_SIZE > PAGE_SIZE 1760 1761 17622: /* Invalid PGD, default exception handling */ 1763 1764 rsr a1, depc 1765 s32i a1, a2, PT_AREG2 1766 mov a1, a2 1767 1768 rsr a2, ps 1769 bbsi.l a2, PS_UM_BIT, 1f 1770 call0 _kernel_exception 17711: call0 _user_exception 1772 1773ENDPROC(fast_second_level_miss) 1774 1775/* 1776 * StoreProhibitedException 1777 * 1778 * Update the pte and invalidate the itlb mapping for this pte. 1779 * 1780 * Entry condition: 1781 * 1782 * a0: trashed, original value saved on stack (PT_AREG0) 1783 * a1: a1 1784 * a2: new stack pointer, original in DEPC 1785 * a3: a3 1786 * depc: a2, original value saved on stack (PT_DEPC) 1787 * excsave_1: dispatch table 1788 * 1789 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 1790 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 1791 */ 1792 1793ENTRY(fast_store_prohibited) 1794 1795 /* Save a1 and a3. */ 1796 1797 s32i a1, a2, PT_AREG1 1798 s32i a3, a2, PT_AREG3 1799 1800 GET_CURRENT(a1,a2) 1801 l32i a0, a1, TASK_MM # tsk->mm 1802 beqz a0, 9f 1803 18048: rsr a1, excvaddr # fault address 1805 _PGD_OFFSET(a0, a1, a3) 1806 l32i a0, a0, 0 1807 beqz a0, 2f 1808 1809 /* 1810 * Note that we test _PAGE_WRITABLE_BIT only if PTE is present 1811 * and is not PAGE_NONE. See pgtable.h for possible PTE layouts. 1812 */ 1813 1814 _PTE_OFFSET(a0, a1, a3) 1815 l32i a3, a0, 0 # read pteval 1816 movi a1, _PAGE_CA_INVALID 1817 ball a3, a1, 2f 1818 bbci.l a3, _PAGE_WRITABLE_BIT, 2f 1819 1820 movi a1, _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_HW_WRITE 1821 or a3, a3, a1 1822 rsr a1, excvaddr 1823 s32i a3, a0, 0 1824 1825 /* We need to flush the cache if we have page coloring. */ 1826#if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK 1827 dhwb a0, 0 1828#endif 1829 pdtlb a0, a1 1830 wdtlb a3, a0 1831 1832 /* Exit critical section. */ 1833 1834 movi a0, 0 1835 rsr a3, excsave1 1836 s32i a0, a3, EXC_TABLE_FIXUP 1837 1838 /* Restore the working registers, and return. */ 1839 1840 l32i a3, a2, PT_AREG3 1841 l32i a1, a2, PT_AREG1 1842 l32i a0, a2, PT_AREG0 1843 l32i a2, a2, PT_DEPC 1844 1845 bgeui a2, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f 1846 1847 rsr a2, depc 1848 rfe 1849 1850 /* Double exception. Restore FIXUP handler and return. */ 1851 18521: xsr a2, depc 1853 esync 1854 rfde 1855 18569: l32i a0, a1, TASK_ACTIVE_MM # unlikely case mm == 0 1857 j 8b 1858 18592: /* If there was a problem, handle fault in C */ 1860 1861 rsr a3, depc # still holds a2 1862 s32i a3, a2, PT_AREG2 1863 mov a1, a2 1864 1865 rsr a2, ps 1866 bbsi.l a2, PS_UM_BIT, 1f 1867 call0 _kernel_exception 18681: call0 _user_exception 1869 1870ENDPROC(fast_store_prohibited) 1871 1872#endif /* CONFIG_MMU */ 1873 1874 .text 1875/* 1876 * System Calls. 1877 * 1878 * void system_call (struct pt_regs* regs, int exccause) 1879 * a2 a3 1880 */ 1881 .literal_position 1882 1883ENTRY(system_call) 1884 1885 abi_entry_default 1886 1887 /* regs->syscall = regs->areg[2] */ 1888 1889 l32i a7, a2, PT_AREG2 1890 s32i a7, a2, PT_SYSCALL 1891 1892 GET_THREAD_INFO(a4, a1) 1893 l32i a3, a4, TI_FLAGS 1894 movi a4, _TIF_WORK_MASK 1895 and a3, a3, a4 1896 beqz a3, 1f 1897 1898 mov a6, a2 1899 call4 do_syscall_trace_enter 1900 beqz a6, .Lsyscall_exit 1901 l32i a7, a2, PT_SYSCALL 1902 19031: 1904 /* syscall = sys_call_table[syscall_nr] */ 1905 1906 movi a4, sys_call_table 1907 movi a5, __NR_syscalls 1908 movi a6, -ENOSYS 1909 bgeu a7, a5, 1f 1910 1911 addx4 a4, a7, a4 1912 l32i a4, a4, 0 1913 1914 /* Load args: arg0 - arg5 are passed via regs. */ 1915 1916 l32i a6, a2, PT_AREG6 1917 l32i a7, a2, PT_AREG3 1918 l32i a8, a2, PT_AREG4 1919 l32i a9, a2, PT_AREG5 1920 l32i a10, a2, PT_AREG8 1921 l32i a11, a2, PT_AREG9 1922 1923 callx4 a4 1924 19251: /* regs->areg[2] = return_value */ 1926 1927 s32i a6, a2, PT_AREG2 1928 bnez a3, 1f 1929.Lsyscall_exit: 1930 abi_ret_default 1931 19321: 1933 mov a6, a2 1934 call4 do_syscall_trace_leave 1935 abi_ret_default 1936 1937ENDPROC(system_call) 1938 1939/* 1940 * Spill live registers on the kernel stack macro. 1941 * 1942 * Entry condition: ps.woe is set, ps.excm is cleared 1943 * Exit condition: windowstart has single bit set 1944 * May clobber: a12, a13 1945 */ 1946 .macro spill_registers_kernel 1947 1948#if XCHAL_NUM_AREGS > 16 1949 call12 1f 1950 _j 2f 1951 retw 1952 .align 4 19531: 1954 _entry a1, 48 1955 addi a12, a0, 3 1956#if XCHAL_NUM_AREGS > 32 1957 .rept (XCHAL_NUM_AREGS - 32) / 12 1958 _entry a1, 48 1959 mov a12, a0 1960 .endr 1961#endif 1962 _entry a1, 16 1963#if XCHAL_NUM_AREGS % 12 == 0 1964 mov a8, a8 1965#elif XCHAL_NUM_AREGS % 12 == 4 1966 mov a12, a12 1967#elif XCHAL_NUM_AREGS % 12 == 8 1968 mov a4, a4 1969#endif 1970 retw 19712: 1972#else 1973 mov a12, a12 1974#endif 1975 .endm 1976 1977/* 1978 * Task switch. 1979 * 1980 * struct task* _switch_to (struct task* prev, struct task* next) 1981 * a2 a2 a3 1982 */ 1983 1984ENTRY(_switch_to) 1985 1986 abi_entry(XTENSA_SPILL_STACK_RESERVE) 1987 1988 mov a11, a3 # and 'next' (a3) 1989 1990 l32i a4, a2, TASK_THREAD_INFO 1991 l32i a5, a3, TASK_THREAD_INFO 1992 1993 save_xtregs_user a4 a6 a8 a9 a12 a13 THREAD_XTREGS_USER 1994 1995#if THREAD_RA > 1020 || THREAD_SP > 1020 1996 addi a10, a2, TASK_THREAD 1997 s32i a0, a10, THREAD_RA - TASK_THREAD # save return address 1998 s32i a1, a10, THREAD_SP - TASK_THREAD # save stack pointer 1999#else 2000 s32i a0, a2, THREAD_RA # save return address 2001 s32i a1, a2, THREAD_SP # save stack pointer 2002#endif 2003 2004#if defined(CONFIG_STACKPROTECTOR) && !defined(CONFIG_SMP) 2005 movi a6, __stack_chk_guard 2006 l32i a8, a3, TASK_STACK_CANARY 2007 s32i a8, a6, 0 2008#endif 2009 2010 /* Disable ints while we manipulate the stack pointer. */ 2011 2012 irq_save a14, a3 2013 rsync 2014 2015 /* Switch CPENABLE */ 2016 2017#if (XTENSA_HAVE_COPROCESSORS || XTENSA_HAVE_IO_PORTS) 2018 l32i a3, a5, THREAD_CPENABLE 2019 xsr a3, cpenable 2020 s32i a3, a4, THREAD_CPENABLE 2021#endif 2022 2023 /* Flush register file. */ 2024 2025 spill_registers_kernel 2026 2027 /* Set kernel stack (and leave critical section) 2028 * Note: It's save to set it here. The stack will not be overwritten 2029 * because the kernel stack will only be loaded again after 2030 * we return from kernel space. 2031 */ 2032 2033 rsr a3, excsave1 # exc_table 2034 addi a7, a5, PT_REGS_OFFSET 2035 s32i a7, a3, EXC_TABLE_KSTK 2036 2037 /* restore context of the task 'next' */ 2038 2039 l32i a0, a11, THREAD_RA # restore return address 2040 l32i a1, a11, THREAD_SP # restore stack pointer 2041 2042 load_xtregs_user a5 a6 a8 a9 a12 a13 THREAD_XTREGS_USER 2043 2044 wsr a14, ps 2045 rsync 2046 2047 abi_ret(XTENSA_SPILL_STACK_RESERVE) 2048 2049ENDPROC(_switch_to) 2050 2051ENTRY(ret_from_fork) 2052 2053 /* void schedule_tail (struct task_struct *prev) 2054 * Note: prev is still in a6 (return value from fake call4 frame) 2055 */ 2056 call4 schedule_tail 2057 2058 mov a6, a1 2059 call4 do_syscall_trace_leave 2060 2061 j common_exception_return 2062 2063ENDPROC(ret_from_fork) 2064 2065/* 2066 * Kernel thread creation helper 2067 * On entry, set up by copy_thread: a2 = thread_fn, a3 = thread_fn arg 2068 * left from _switch_to: a6 = prev 2069 */ 2070ENTRY(ret_from_kernel_thread) 2071 2072 call4 schedule_tail 2073 mov a6, a3 2074 callx4 a2 2075 j common_exception_return 2076 2077ENDPROC(ret_from_kernel_thread) 2078