1/* 2 * arch/xtensa/kernel/coprocessor.S 3 * 4 * Xtensa processor configuration-specific table of coprocessor and 5 * other custom register layout information. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Copyright (C) 2003 - 2007 Tensilica Inc. 12 */ 13 14 15#include <linux/linkage.h> 16#include <asm/asm-offsets.h> 17#include <asm/asmmacro.h> 18#include <asm/coprocessor.h> 19#include <asm/current.h> 20#include <asm/regs.h> 21 22#if XTENSA_HAVE_COPROCESSORS 23 24/* 25 * Macros for lazy context switch. 26 */ 27 28#define SAVE_CP_REGS(x) \ 29 .if XTENSA_HAVE_COPROCESSOR(x); \ 30 .align 4; \ 31 .Lsave_cp_regs_cp##x: \ 32 xchal_cp##x##_store a2 a4 a5 a6 a7; \ 33 jx a0; \ 34 .endif 35 36#define SAVE_CP_REGS_TAB(x) \ 37 .if XTENSA_HAVE_COPROCESSOR(x); \ 38 .long .Lsave_cp_regs_cp##x; \ 39 .else; \ 40 .long 0; \ 41 .endif; \ 42 .long THREAD_XTREGS_CP##x 43 44 45#define LOAD_CP_REGS(x) \ 46 .if XTENSA_HAVE_COPROCESSOR(x); \ 47 .align 4; \ 48 .Lload_cp_regs_cp##x: \ 49 xchal_cp##x##_load a2 a4 a5 a6 a7; \ 50 jx a0; \ 51 .endif 52 53#define LOAD_CP_REGS_TAB(x) \ 54 .if XTENSA_HAVE_COPROCESSOR(x); \ 55 .long .Lload_cp_regs_cp##x; \ 56 .else; \ 57 .long 0; \ 58 .endif; \ 59 .long THREAD_XTREGS_CP##x 60 61 __XTENSA_HANDLER 62 63 SAVE_CP_REGS(0) 64 SAVE_CP_REGS(1) 65 SAVE_CP_REGS(2) 66 SAVE_CP_REGS(3) 67 SAVE_CP_REGS(4) 68 SAVE_CP_REGS(5) 69 SAVE_CP_REGS(6) 70 SAVE_CP_REGS(7) 71 72 LOAD_CP_REGS(0) 73 LOAD_CP_REGS(1) 74 LOAD_CP_REGS(2) 75 LOAD_CP_REGS(3) 76 LOAD_CP_REGS(4) 77 LOAD_CP_REGS(5) 78 LOAD_CP_REGS(6) 79 LOAD_CP_REGS(7) 80 81 .align 4 82.Lsave_cp_regs_jump_table: 83 SAVE_CP_REGS_TAB(0) 84 SAVE_CP_REGS_TAB(1) 85 SAVE_CP_REGS_TAB(2) 86 SAVE_CP_REGS_TAB(3) 87 SAVE_CP_REGS_TAB(4) 88 SAVE_CP_REGS_TAB(5) 89 SAVE_CP_REGS_TAB(6) 90 SAVE_CP_REGS_TAB(7) 91 92.Lload_cp_regs_jump_table: 93 LOAD_CP_REGS_TAB(0) 94 LOAD_CP_REGS_TAB(1) 95 LOAD_CP_REGS_TAB(2) 96 LOAD_CP_REGS_TAB(3) 97 LOAD_CP_REGS_TAB(4) 98 LOAD_CP_REGS_TAB(5) 99 LOAD_CP_REGS_TAB(6) 100 LOAD_CP_REGS_TAB(7) 101 102/* 103 * Entry condition: 104 * 105 * a0: trashed, original value saved on stack (PT_AREG0) 106 * a1: a1 107 * a2: new stack pointer, original in DEPC 108 * a3: a3 109 * depc: a2, original value saved on stack (PT_DEPC) 110 * excsave_1: dispatch table 111 * 112 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 113 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 114 */ 115 116ENTRY(fast_coprocessor) 117 118 /* Save remaining registers a1-a3 and SAR */ 119 120 s32i a3, a2, PT_AREG3 121 rsr a3, sar 122 s32i a1, a2, PT_AREG1 123 s32i a3, a2, PT_SAR 124 mov a1, a2 125 rsr a2, depc 126 s32i a2, a1, PT_AREG2 127 128 /* 129 * The hal macros require up to 4 temporary registers. We use a3..a6. 130 */ 131 132 s32i a4, a1, PT_AREG4 133 s32i a5, a1, PT_AREG5 134 s32i a6, a1, PT_AREG6 135 136 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ 137 138 rsr a3, exccause 139 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 140 141 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/ 142 143 ssl a3 # SAR: 32 - coprocessor_number 144 movi a2, 1 145 rsr a0, cpenable 146 sll a2, a2 147 or a0, a0, a2 148 wsr a0, cpenable 149 rsync 150 151 /* Retrieve previous owner. (a3 still holds CP number) */ 152 153 movi a0, coprocessor_owner # list of owners 154 addx4 a0, a3, a0 # entry for CP 155 l32i a4, a0, 0 156 157 beqz a4, 1f # skip 'save' if no previous owner 158 159 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */ 160 161 l32i a5, a4, THREAD_CPENABLE 162 xor a5, a5, a2 # (1 << cp-id) still in a2 163 s32i a5, a4, THREAD_CPENABLE 164 165 /* 166 * Get context save area and 'call' save routine. 167 * (a4 still holds previous owner (thread_info), a3 CP number) 168 */ 169 170 movi a5, .Lsave_cp_regs_jump_table 171 movi a0, 2f # a0: 'return' address 172 addx8 a3, a3, a5 # a3: coprocessor number 173 l32i a2, a3, 4 # a2: xtregs offset 174 l32i a3, a3, 0 # a3: jump address 175 add a2, a2, a4 176 jx a3 177 178 /* Note that only a0 and a1 were preserved. */ 179 1802: rsr a3, exccause 181 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 182 movi a0, coprocessor_owner 183 addx4 a0, a3, a0 184 185 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */ 186 1871: GET_THREAD_INFO (a4, a1) 188 s32i a4, a0, 0 189 190 /* Get context save area and 'call' load routine. */ 191 192 movi a5, .Lload_cp_regs_jump_table 193 movi a0, 1f 194 addx8 a3, a3, a5 195 l32i a2, a3, 4 # a2: xtregs offset 196 l32i a3, a3, 0 # a3: jump address 197 add a2, a2, a4 198 jx a3 199 200 /* Restore all registers and return from exception handler. */ 201 2021: l32i a6, a1, PT_AREG6 203 l32i a5, a1, PT_AREG5 204 l32i a4, a1, PT_AREG4 205 206 l32i a0, a1, PT_SAR 207 l32i a3, a1, PT_AREG3 208 l32i a2, a1, PT_AREG2 209 wsr a0, sar 210 l32i a0, a1, PT_AREG0 211 l32i a1, a1, PT_AREG1 212 213 rfe 214 215ENDPROC(fast_coprocessor) 216 217 .text 218 219/* 220 * coprocessor_flush(struct thread_info*, index) 221 * a2 a3 222 * 223 * Save coprocessor registers for coprocessor 'index'. 224 * The register values are saved to or loaded from the coprocessor area 225 * inside the task_info structure. 226 * 227 * Note that this function doesn't update the coprocessor_owner information! 228 * 229 */ 230 231ENTRY(coprocessor_flush) 232 233 /* reserve 4 bytes on stack to save a0 */ 234 abi_entry(4) 235 236 s32i a0, a1, 0 237 movi a0, .Lsave_cp_regs_jump_table 238 addx8 a3, a3, a0 239 l32i a4, a3, 4 240 l32i a3, a3, 0 241 add a2, a2, a4 242 beqz a3, 1f 243 callx0 a3 2441: l32i a0, a1, 0 245 246 abi_ret(4) 247 248ENDPROC(coprocessor_flush) 249 250 .data 251 252ENTRY(coprocessor_owner) 253 254 .fill XCHAL_CP_MAX, 4, 0 255 256END(coprocessor_owner) 257 258#endif /* XTENSA_HAVE_COPROCESSORS */ 259