1/* 2 * arch/xtensa/kernel/coprocessor.S 3 * 4 * Xtensa processor configuration-specific table of coprocessor and 5 * other custom register layout information. 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 * 11 * Copyright (C) 2003 - 2007 Tensilica Inc. 12 */ 13 14 15#include <linux/linkage.h> 16#include <asm/asm-offsets.h> 17#include <asm/processor.h> 18#include <asm/coprocessor.h> 19#include <asm/thread_info.h> 20#include <asm/asm-uaccess.h> 21#include <asm/unistd.h> 22#include <asm/ptrace.h> 23#include <asm/current.h> 24#include <asm/pgtable.h> 25#include <asm/page.h> 26#include <asm/signal.h> 27#include <asm/tlbflush.h> 28 29#if XTENSA_HAVE_COPROCESSORS 30 31/* 32 * Macros for lazy context switch. 33 */ 34 35#define SAVE_CP_REGS(x) \ 36 .if XTENSA_HAVE_COPROCESSOR(x); \ 37 .align 4; \ 38 .Lsave_cp_regs_cp##x: \ 39 xchal_cp##x##_store a2 a4 a5 a6 a7; \ 40 jx a0; \ 41 .endif 42 43#define SAVE_CP_REGS_TAB(x) \ 44 .if XTENSA_HAVE_COPROCESSOR(x); \ 45 .long .Lsave_cp_regs_cp##x; \ 46 .else; \ 47 .long 0; \ 48 .endif; \ 49 .long THREAD_XTREGS_CP##x 50 51 52#define LOAD_CP_REGS(x) \ 53 .if XTENSA_HAVE_COPROCESSOR(x); \ 54 .align 4; \ 55 .Lload_cp_regs_cp##x: \ 56 xchal_cp##x##_load a2 a4 a5 a6 a7; \ 57 jx a0; \ 58 .endif 59 60#define LOAD_CP_REGS_TAB(x) \ 61 .if XTENSA_HAVE_COPROCESSOR(x); \ 62 .long .Lload_cp_regs_cp##x; \ 63 .else; \ 64 .long 0; \ 65 .endif; \ 66 .long THREAD_XTREGS_CP##x 67 68 SAVE_CP_REGS(0) 69 SAVE_CP_REGS(1) 70 SAVE_CP_REGS(2) 71 SAVE_CP_REGS(3) 72 SAVE_CP_REGS(4) 73 SAVE_CP_REGS(5) 74 SAVE_CP_REGS(6) 75 SAVE_CP_REGS(7) 76 77 LOAD_CP_REGS(0) 78 LOAD_CP_REGS(1) 79 LOAD_CP_REGS(2) 80 LOAD_CP_REGS(3) 81 LOAD_CP_REGS(4) 82 LOAD_CP_REGS(5) 83 LOAD_CP_REGS(6) 84 LOAD_CP_REGS(7) 85 86 .section ".rodata", "a" 87 .align 4 88.Lsave_cp_regs_jump_table: 89 SAVE_CP_REGS_TAB(0) 90 SAVE_CP_REGS_TAB(1) 91 SAVE_CP_REGS_TAB(2) 92 SAVE_CP_REGS_TAB(3) 93 SAVE_CP_REGS_TAB(4) 94 SAVE_CP_REGS_TAB(5) 95 SAVE_CP_REGS_TAB(6) 96 SAVE_CP_REGS_TAB(7) 97 98.Lload_cp_regs_jump_table: 99 LOAD_CP_REGS_TAB(0) 100 LOAD_CP_REGS_TAB(1) 101 LOAD_CP_REGS_TAB(2) 102 LOAD_CP_REGS_TAB(3) 103 LOAD_CP_REGS_TAB(4) 104 LOAD_CP_REGS_TAB(5) 105 LOAD_CP_REGS_TAB(6) 106 LOAD_CP_REGS_TAB(7) 107 108 .previous 109 110/* 111 * coprocessor_flush(struct thread_info*, index) 112 * a2 a3 113 * 114 * Save coprocessor registers for coprocessor 'index'. 115 * The register values are saved to or loaded from the coprocessor area 116 * inside the task_info structure. 117 * 118 * Note that this function doesn't update the coprocessor_owner information! 119 * 120 */ 121 122ENTRY(coprocessor_flush) 123 124 entry a1, 32 125 s32i a0, a1, 0 126 movi a0, .Lsave_cp_regs_jump_table 127 addx8 a3, a3, a0 128 l32i a4, a3, 4 129 l32i a3, a3, 0 130 add a2, a2, a4 131 beqz a3, 1f 132 callx0 a3 1331: l32i a0, a1, 0 134 retw 135 136ENDPROC(coprocessor_flush) 137 138/* 139 * Entry condition: 140 * 141 * a0: trashed, original value saved on stack (PT_AREG0) 142 * a1: a1 143 * a2: new stack pointer, original in DEPC 144 * a3: a3 145 * depc: a2, original value saved on stack (PT_DEPC) 146 * excsave_1: dispatch table 147 * 148 * PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC 149 * < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception 150 */ 151 152ENTRY(fast_coprocessor_double) 153 154 wsr a0, excsave1 155 call0 unrecoverable_exception 156 157ENDPROC(fast_coprocessor_double) 158 159ENTRY(fast_coprocessor) 160 161 /* Save remaining registers a1-a3 and SAR */ 162 163 s32i a3, a2, PT_AREG3 164 rsr a3, sar 165 s32i a1, a2, PT_AREG1 166 s32i a3, a2, PT_SAR 167 mov a1, a2 168 rsr a2, depc 169 s32i a2, a1, PT_AREG2 170 171 /* 172 * The hal macros require up to 4 temporary registers. We use a3..a6. 173 */ 174 175 s32i a4, a1, PT_AREG4 176 s32i a5, a1, PT_AREG5 177 s32i a6, a1, PT_AREG6 178 179 /* Find coprocessor number. Subtract first CP EXCCAUSE from EXCCAUSE */ 180 181 rsr a3, exccause 182 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 183 184 /* Set corresponding CPENABLE bit -> (sar:cp-index, a3: 1<<cp-index)*/ 185 186 ssl a3 # SAR: 32 - coprocessor_number 187 movi a2, 1 188 rsr a0, cpenable 189 sll a2, a2 190 or a0, a0, a2 191 wsr a0, cpenable 192 rsync 193 194 /* Retrieve previous owner. (a3 still holds CP number) */ 195 196 movi a0, coprocessor_owner # list of owners 197 addx4 a0, a3, a0 # entry for CP 198 l32i a4, a0, 0 199 200 beqz a4, 1f # skip 'save' if no previous owner 201 202 /* Disable coprocessor for previous owner. (a2 = 1 << CP number) */ 203 204 l32i a5, a4, THREAD_CPENABLE 205 xor a5, a5, a2 # (1 << cp-id) still in a2 206 s32i a5, a4, THREAD_CPENABLE 207 208 /* 209 * Get context save area and 'call' save routine. 210 * (a4 still holds previous owner (thread_info), a3 CP number) 211 */ 212 213 movi a5, .Lsave_cp_regs_jump_table 214 movi a0, 2f # a0: 'return' address 215 addx8 a3, a3, a5 # a3: coprocessor number 216 l32i a2, a3, 4 # a2: xtregs offset 217 l32i a3, a3, 0 # a3: jump address 218 add a2, a2, a4 219 jx a3 220 221 /* Note that only a0 and a1 were preserved. */ 222 2232: rsr a3, exccause 224 addi a3, a3, -EXCCAUSE_COPROCESSOR0_DISABLED 225 movi a0, coprocessor_owner 226 addx4 a0, a3, a0 227 228 /* Set new 'owner' (a0 points to the CP owner, a3 contains the CP nr) */ 229 2301: GET_THREAD_INFO (a4, a1) 231 s32i a4, a0, 0 232 233 /* Get context save area and 'call' load routine. */ 234 235 movi a5, .Lload_cp_regs_jump_table 236 movi a0, 1f 237 addx8 a3, a3, a5 238 l32i a2, a3, 4 # a2: xtregs offset 239 l32i a3, a3, 0 # a3: jump address 240 add a2, a2, a4 241 jx a3 242 243 /* Restore all registers and return from exception handler. */ 244 2451: l32i a6, a1, PT_AREG6 246 l32i a5, a1, PT_AREG5 247 l32i a4, a1, PT_AREG4 248 249 l32i a0, a1, PT_SAR 250 l32i a3, a1, PT_AREG3 251 l32i a2, a1, PT_AREG2 252 wsr a0, sar 253 l32i a0, a1, PT_AREG0 254 l32i a1, a1, PT_AREG1 255 256 rfe 257 258ENDPROC(fast_coprocessor) 259 260 .data 261 262ENTRY(coprocessor_owner) 263 264 .fill XCHAL_CP_MAX, 4, 0 265 266END(coprocessor_owner) 267 268#endif /* XTENSA_HAVE_COPROCESSORS */ 269