1 /* 2 * arch/xtensa/include/asm/traps.h 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2012 Tensilica Inc. 9 */ 10 #ifndef _XTENSA_TRAPS_H 11 #define _XTENSA_TRAPS_H 12 13 #include <asm/ptrace.h> 14 15 /* 16 * handler must be either of the following: 17 * void (*)(struct pt_regs *regs); 18 * void (*)(struct pt_regs *regs, unsigned long exccause); 19 */ 20 extern void * __init trap_set_handler(int cause, void *handler); 21 extern void do_unhandled(struct pt_regs *regs, unsigned long exccause); 22 void secondary_trap_init(void); 23 24 static inline void spill_registers(void) 25 { 26 #if XCHAL_NUM_AREGS > 16 27 __asm__ __volatile__ ( 28 " call12 1f\n" 29 " _j 2f\n" 30 " retw\n" 31 " .align 4\n" 32 "1:\n" 33 " _entry a1, 48\n" 34 " addi a12, a0, 3\n" 35 #if XCHAL_NUM_AREGS > 32 36 " .rept (" __stringify(XCHAL_NUM_AREGS) " - 32) / 12\n" 37 " _entry a1, 48\n" 38 " mov a12, a0\n" 39 " .endr\n" 40 #endif 41 " _entry a1, 48\n" 42 #if XCHAL_NUM_AREGS % 12 == 0 43 " mov a8, a8\n" 44 #elif XCHAL_NUM_AREGS % 12 == 4 45 " mov a12, a12\n" 46 #elif XCHAL_NUM_AREGS % 12 == 8 47 " mov a4, a4\n" 48 #endif 49 " retw\n" 50 "2:\n" 51 : : : "a12", "a13", "memory"); 52 #else 53 __asm__ __volatile__ ( 54 " mov a12, a12\n" 55 : : : "memory"); 56 #endif 57 } 58 59 #endif /* _XTENSA_TRAPS_H */ 60