xref: /openbmc/linux/arch/xtensa/include/asm/traps.h (revision ba61bb17)
1 /*
2  * arch/xtensa/include/asm/traps.h
3  *
4  * This file is subject to the terms and conditions of the GNU General Public
5  * License.  See the file "COPYING" in the main directory of this archive
6  * for more details.
7  *
8  * Copyright (C) 2012 Tensilica Inc.
9  */
10 #ifndef _XTENSA_TRAPS_H
11 #define _XTENSA_TRAPS_H
12 
13 #include <asm/ptrace.h>
14 
15 /*
16  * Per-CPU exception handling data structure.
17  * EXCSAVE1 points to it.
18  */
19 struct exc_table {
20 	/* Kernel Stack */
21 	void *kstk;
22 	/* Double exception save area for a0 */
23 	unsigned long double_save;
24 	/* Fixup handler */
25 	void *fixup;
26 	/* For passing a parameter to fixup */
27 	void *fixup_param;
28 	/* For fast syscall handler */
29 	unsigned long syscall_save;
30 	/* Fast user exception handlers */
31 	void *fast_user_handler[EXCCAUSE_N];
32 	/* Fast kernel exception handlers */
33 	void *fast_kernel_handler[EXCCAUSE_N];
34 	/* Default C-Handlers */
35 	void *default_handler[EXCCAUSE_N];
36 };
37 
38 /*
39  * handler must be either of the following:
40  *  void (*)(struct pt_regs *regs);
41  *  void (*)(struct pt_regs *regs, unsigned long exccause);
42  */
43 extern void * __init trap_set_handler(int cause, void *handler);
44 extern void do_unhandled(struct pt_regs *regs, unsigned long exccause);
45 void fast_second_level_miss(void);
46 
47 /* Initialize minimal exc_table structure sufficient for basic paging */
48 static inline void __init early_trap_init(void)
49 {
50 	static struct exc_table exc_table __initdata = {
51 		.fast_kernel_handler[EXCCAUSE_DTLB_MISS] =
52 			fast_second_level_miss,
53 	};
54 	__asm__ __volatile__("wsr  %0, excsave1\n" : : "a" (&exc_table));
55 }
56 
57 void secondary_trap_init(void);
58 
59 static inline void spill_registers(void)
60 {
61 #if XCHAL_NUM_AREGS > 16
62 	__asm__ __volatile__ (
63 		"	call8	1f\n"
64 		"	_j	2f\n"
65 		"	retw\n"
66 		"	.align	4\n"
67 		"1:\n"
68 #if XCHAL_NUM_AREGS == 32
69 		"	_entry	a1, 32\n"
70 		"	addi	a8, a0, 3\n"
71 		"	_entry	a1, 16\n"
72 		"	mov	a12, a12\n"
73 		"	retw\n"
74 #else
75 		"	_entry	a1, 48\n"
76 		"	call12	1f\n"
77 		"	retw\n"
78 		"	.align	4\n"
79 		"1:\n"
80 		"	.rept	(" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n"
81 		"	_entry	a1, 48\n"
82 		"	mov	a12, a0\n"
83 		"	.endr\n"
84 		"	_entry	a1, 16\n"
85 #if XCHAL_NUM_AREGS % 12 == 0
86 		"	mov	a12, a12\n"
87 #elif XCHAL_NUM_AREGS % 12 == 4
88 		"	mov	a4, a4\n"
89 #elif XCHAL_NUM_AREGS % 12 == 8
90 		"	mov	a8, a8\n"
91 #endif
92 		"	retw\n"
93 #endif
94 		"2:\n"
95 		: : : "a8", "a9", "memory");
96 #else
97 	__asm__ __volatile__ (
98 		"	mov	a12, a12\n"
99 		: : : "memory");
100 #endif
101 }
102 
103 struct debug_table {
104 	/* Pointer to debug exception handler */
105 	void (*debug_exception)(void);
106 	/* Temporary register save area */
107 	unsigned long debug_save[1];
108 #ifdef CONFIG_HAVE_HW_BREAKPOINT
109 	/* Save area for DBREAKC registers */
110 	unsigned long dbreakc_save[XCHAL_NUM_DBREAK];
111 	/* Saved ICOUNT register */
112 	unsigned long icount_save;
113 	/* Saved ICOUNTLEVEL register */
114 	unsigned long icount_level_save;
115 #endif
116 };
117 
118 void debug_exception(void);
119 
120 #endif /* _XTENSA_TRAPS_H */
121