1 /* 2 * arch/xtensa/include/asm/traps.h 3 * 4 * This file is subject to the terms and conditions of the GNU General Public 5 * License. See the file "COPYING" in the main directory of this archive 6 * for more details. 7 * 8 * Copyright (C) 2012 Tensilica Inc. 9 */ 10 #ifndef _XTENSA_TRAPS_H 11 #define _XTENSA_TRAPS_H 12 13 #include <asm/ptrace.h> 14 15 /* 16 * Per-CPU exception handling data structure. 17 * EXCSAVE1 points to it. 18 */ 19 struct exc_table { 20 /* Kernel Stack */ 21 void *kstk; 22 /* Double exception save area for a0 */ 23 unsigned long double_save; 24 /* Fixup handler */ 25 void *fixup; 26 /* For passing a parameter to fixup */ 27 void *fixup_param; 28 /* Fast user exception handlers */ 29 void *fast_user_handler[EXCCAUSE_N]; 30 /* Fast kernel exception handlers */ 31 void *fast_kernel_handler[EXCCAUSE_N]; 32 /* Default C-Handlers */ 33 void *default_handler[EXCCAUSE_N]; 34 }; 35 36 /* 37 * handler must be either of the following: 38 * void (*)(struct pt_regs *regs); 39 * void (*)(struct pt_regs *regs, unsigned long exccause); 40 */ 41 extern void * __init trap_set_handler(int cause, void *handler); 42 extern void do_unhandled(struct pt_regs *regs, unsigned long exccause); 43 void fast_second_level_miss(void); 44 45 /* Initialize minimal exc_table structure sufficient for basic paging */ 46 static inline void __init early_trap_init(void) 47 { 48 static struct exc_table exc_table __initdata = { 49 .fast_kernel_handler[EXCCAUSE_DTLB_MISS] = 50 fast_second_level_miss, 51 }; 52 __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (&exc_table)); 53 } 54 55 void secondary_trap_init(void); 56 57 static inline void spill_registers(void) 58 { 59 #if XCHAL_NUM_AREGS > 16 60 __asm__ __volatile__ ( 61 " call8 1f\n" 62 " _j 2f\n" 63 " retw\n" 64 " .align 4\n" 65 "1:\n" 66 #if XCHAL_NUM_AREGS == 32 67 " _entry a1, 32\n" 68 " addi a8, a0, 3\n" 69 " _entry a1, 16\n" 70 " mov a12, a12\n" 71 " retw\n" 72 #else 73 " _entry a1, 48\n" 74 " call12 1f\n" 75 " retw\n" 76 " .align 4\n" 77 "1:\n" 78 " .rept (" __stringify(XCHAL_NUM_AREGS) " - 16) / 12\n" 79 " _entry a1, 48\n" 80 " mov a12, a0\n" 81 " .endr\n" 82 " _entry a1, 16\n" 83 #if XCHAL_NUM_AREGS % 12 == 0 84 " mov a12, a12\n" 85 #elif XCHAL_NUM_AREGS % 12 == 4 86 " mov a4, a4\n" 87 #elif XCHAL_NUM_AREGS % 12 == 8 88 " mov a8, a8\n" 89 #endif 90 " retw\n" 91 #endif 92 "2:\n" 93 : : : "a8", "a9", "memory"); 94 #else 95 __asm__ __volatile__ ( 96 " mov a12, a12\n" 97 : : : "memory"); 98 #endif 99 } 100 101 struct debug_table { 102 /* Pointer to debug exception handler */ 103 void (*debug_exception)(void); 104 /* Temporary register save area */ 105 unsigned long debug_save[1]; 106 #ifdef CONFIG_HAVE_HW_BREAKPOINT 107 /* Save area for DBREAKC registers */ 108 unsigned long dbreakc_save[XCHAL_NUM_DBREAK]; 109 /* Saved ICOUNT register */ 110 unsigned long icount_save; 111 /* Saved ICOUNTLEVEL register */ 112 unsigned long icount_level_save; 113 #endif 114 }; 115 116 void debug_exception(void); 117 118 #endif /* _XTENSA_TRAPS_H */ 119