1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2001 - 2008 Tensilica Inc. 7 * Copyright (C) 2015 Cadence Design Systems Inc. 8 */ 9 10 #ifndef _XTENSA_PROCESSOR_H 11 #define _XTENSA_PROCESSOR_H 12 13 #include <asm/core.h> 14 15 #include <linux/compiler.h> 16 #include <linux/stringify.h> 17 #include <asm/ptrace.h> 18 #include <asm/types.h> 19 #include <asm/regs.h> 20 21 #define ARCH_SLAB_MINALIGN XTENSA_STACK_ALIGNMENT 22 23 /* 24 * User space process size: 1 GB. 25 * Windowed call ABI requires caller and callee to be located within the same 26 * 1 GB region. The C compiler places trampoline code on the stack for sources 27 * that take the address of a nested C function (a feature used by glibc), so 28 * the 1 GB requirement applies to the stack as well. 29 */ 30 31 #ifdef CONFIG_MMU 32 #define TASK_SIZE __XTENSA_UL_CONST(0x40000000) 33 #else 34 #define TASK_SIZE __XTENSA_UL_CONST(0xffffffff) 35 #endif 36 37 #define STACK_TOP TASK_SIZE 38 #define STACK_TOP_MAX STACK_TOP 39 40 /* 41 * General exception cause assigned to fake NMI. Fake NMI needs to be handled 42 * differently from other interrupts, but it uses common kernel entry/exit 43 * code. 44 */ 45 46 #define EXCCAUSE_MAPPED_NMI 62 47 48 /* 49 * General exception cause assigned to debug exceptions. Debug exceptions go 50 * to their own vector, rather than the general exception vectors (user, 51 * kernel, double); and their specific causes are reported via DEBUGCAUSE 52 * rather than EXCCAUSE. However it is sometimes convenient to redirect debug 53 * exceptions to the general exception mechanism. To do this, an otherwise 54 * unused EXCCAUSE value was assigned to debug exceptions for this purpose. 55 */ 56 57 #define EXCCAUSE_MAPPED_DEBUG 63 58 59 /* 60 * We use DEPC also as a flag to distinguish between double and regular 61 * exceptions. For performance reasons, DEPC might contain the value of 62 * EXCCAUSE for regular exceptions, so we use this definition to mark a 63 * valid double exception address. 64 * (Note: We use it in bgeui, so it should be 64, 128, or 256) 65 */ 66 67 #define VALID_DOUBLE_EXCEPTION_ADDRESS 64 68 69 #define XTENSA_INT_LEVEL(intno) _XTENSA_INT_LEVEL(intno) 70 #define _XTENSA_INT_LEVEL(intno) XCHAL_INT##intno##_LEVEL 71 72 #define XTENSA_INTLEVEL_MASK(level) _XTENSA_INTLEVEL_MASK(level) 73 #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) 74 75 #define XTENSA_INTLEVEL_ANDBELOW_MASK(l) _XTENSA_INTLEVEL_ANDBELOW_MASK(l) 76 #define _XTENSA_INTLEVEL_ANDBELOW_MASK(l) (XCHAL_INTLEVEL##l##_ANDBELOW_MASK) 77 78 #define PROFILING_INTLEVEL XTENSA_INT_LEVEL(XCHAL_PROFILING_INTERRUPT) 79 80 /* LOCKLEVEL defines the interrupt level that masks all 81 * general-purpose interrupts. 82 */ 83 #if defined(CONFIG_XTENSA_FAKE_NMI) && defined(XCHAL_PROFILING_INTERRUPT) 84 #define LOCKLEVEL (PROFILING_INTLEVEL - 1) 85 #else 86 #define LOCKLEVEL XCHAL_EXCM_LEVEL 87 #endif 88 89 #define TOPLEVEL XCHAL_EXCM_LEVEL 90 #define XTENSA_FAKE_NMI (LOCKLEVEL < TOPLEVEL) 91 92 /* WSBITS and WBBITS are the width of the WINDOWSTART and WINDOWBASE 93 * registers 94 */ 95 #define WSBITS (XCHAL_NUM_AREGS / 4) /* width of WINDOWSTART in bits */ 96 #define WBBITS (XCHAL_NUM_AREGS_LOG2 - 2) /* width of WINDOWBASE in bits */ 97 98 #if defined(__XTENSA_WINDOWED_ABI__) 99 #define KERNEL_PS_WOE_MASK PS_WOE_MASK 100 #elif defined(__XTENSA_CALL0_ABI__) 101 #define KERNEL_PS_WOE_MASK 0 102 #else 103 #error Unsupported xtensa ABI 104 #endif 105 106 #ifndef __ASSEMBLY__ 107 108 #if defined(__XTENSA_WINDOWED_ABI__) 109 110 /* Build a valid return address for the specified call winsize. 111 * winsize must be 1 (call4), 2 (call8), or 3 (call12) 112 */ 113 #define MAKE_RA_FOR_CALL(ra,ws) (((ra) & 0x3fffffff) | (ws) << 30) 114 115 /* Convert return address to a valid pc 116 * Note: We assume that the stack pointer is in the same 1GB ranges as the ra 117 */ 118 #define MAKE_PC_FROM_RA(ra,sp) (((ra) & 0x3fffffff) | ((sp) & 0xc0000000)) 119 120 #elif defined(__XTENSA_CALL0_ABI__) 121 122 /* Build a valid return address for the specified call winsize. 123 * winsize must be 1 (call4), 2 (call8), or 3 (call12) 124 */ 125 #define MAKE_RA_FOR_CALL(ra, ws) (ra) 126 127 /* Convert return address to a valid pc 128 * Note: We assume that the stack pointer is in the same 1GB ranges as the ra 129 */ 130 #define MAKE_PC_FROM_RA(ra, sp) (ra) 131 132 #else 133 #error Unsupported Xtensa ABI 134 #endif 135 136 /* Spill slot location for the register reg in the spill area under the stack 137 * pointer sp. reg must be in the range [0..4). 138 */ 139 #define SPILL_SLOT(sp, reg) (*(((unsigned long *)(sp)) - 4 + (reg))) 140 141 /* Spill slot location for the register reg in the spill area under the stack 142 * pointer sp for the call8. reg must be in the range [4..8). 143 */ 144 #define SPILL_SLOT_CALL8(sp, reg) (*(((unsigned long *)(sp)) - 12 + (reg))) 145 146 /* Spill slot location for the register reg in the spill area under the stack 147 * pointer sp for the call12. reg must be in the range [4..12). 148 */ 149 #define SPILL_SLOT_CALL12(sp, reg) (*(((unsigned long *)(sp)) - 16 + (reg))) 150 151 struct thread_struct { 152 153 /* kernel's return address and stack pointer for context switching */ 154 unsigned long ra; /* kernel's a0: return address and window call size */ 155 unsigned long sp; /* kernel's a1: stack pointer */ 156 157 #ifdef CONFIG_HAVE_HW_BREAKPOINT 158 struct perf_event *ptrace_bp[XCHAL_NUM_IBREAK]; 159 struct perf_event *ptrace_wp[XCHAL_NUM_DBREAK]; 160 #endif 161 /* Make structure 16 bytes aligned. */ 162 int align[0] __attribute__ ((aligned(16))); 163 }; 164 165 /* This decides where the kernel will search for a free chunk of vm 166 * space during mmap's. 167 */ 168 #define TASK_UNMAPPED_BASE (TASK_SIZE / 2) 169 170 #define INIT_THREAD \ 171 { \ 172 ra: 0, \ 173 sp: sizeof(init_stack) + (long) &init_stack, \ 174 } 175 176 177 /* 178 * Do necessary setup to start up a newly executed thread. 179 * Note: When windowed ABI is used for userspace we set-up ps 180 * as if we did a call4 to the new pc. 181 * set_thread_state in signal.c depends on it. 182 */ 183 #if IS_ENABLED(CONFIG_USER_ABI_CALL0) 184 #define USER_PS_VALUE ((USER_RING << PS_RING_SHIFT) | \ 185 (1 << PS_UM_BIT) | \ 186 (1 << PS_EXCM_BIT)) 187 #else 188 #define USER_PS_VALUE (PS_WOE_MASK | \ 189 (1 << PS_CALLINC_SHIFT) | \ 190 (USER_RING << PS_RING_SHIFT) | \ 191 (1 << PS_UM_BIT) | \ 192 (1 << PS_EXCM_BIT)) 193 #endif 194 195 /* Clearing a0 terminates the backtrace. */ 196 #define start_thread(regs, new_pc, new_sp) \ 197 do { \ 198 unsigned long syscall = (regs)->syscall; \ 199 unsigned long current_aregs[16]; \ 200 memcpy(current_aregs, (regs)->areg, sizeof(current_aregs)); \ 201 memset((regs), 0, sizeof(*(regs))); \ 202 (regs)->pc = (new_pc); \ 203 (regs)->ps = USER_PS_VALUE; \ 204 memcpy((regs)->areg, current_aregs, sizeof(current_aregs)); \ 205 (regs)->areg[1] = (new_sp); \ 206 (regs)->areg[0] = 0; \ 207 (regs)->wmask = 1; \ 208 (regs)->depc = 0; \ 209 (regs)->windowbase = 0; \ 210 (regs)->windowstart = 1; \ 211 (regs)->syscall = syscall; \ 212 } while (0) 213 214 /* Forward declaration */ 215 struct task_struct; 216 struct mm_struct; 217 218 extern unsigned long __get_wchan(struct task_struct *p); 219 220 #define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc) 221 #define KSTK_ESP(tsk) (task_pt_regs(tsk)->areg[1]) 222 223 #define cpu_relax() barrier() 224 225 /* Special register access. */ 226 227 #define xtensa_set_sr(x, sr) \ 228 ({ \ 229 __asm__ __volatile__ ("wsr %0, "__stringify(sr) :: \ 230 "a"((unsigned int)(x))); \ 231 }) 232 233 #define xtensa_get_sr(sr) \ 234 ({ \ 235 unsigned int v; \ 236 __asm__ __volatile__ ("rsr %0, "__stringify(sr) : "=a"(v)); \ 237 v; \ 238 }) 239 240 #define xtensa_xsr(x, sr) \ 241 ({ \ 242 unsigned int __v__ = (unsigned int)(x); \ 243 __asm__ __volatile__ ("xsr %0, " __stringify(sr) : "+a"(__v__)); \ 244 __v__; \ 245 }) 246 247 #if XCHAL_HAVE_EXTERN_REGS 248 249 static inline void set_er(unsigned long value, unsigned long addr) 250 { 251 asm volatile ("wer %0, %1" : : "a" (value), "a" (addr) : "memory"); 252 } 253 254 static inline unsigned long get_er(unsigned long addr) 255 { 256 register unsigned long value; 257 asm volatile ("rer %0, %1" : "=a" (value) : "a" (addr) : "memory"); 258 return value; 259 } 260 261 #endif /* XCHAL_HAVE_EXTERN_REGS */ 262 263 #endif /* __ASSEMBLY__ */ 264 #endif /* _XTENSA_PROCESSOR_H */ 265