1 /* 2 * include/asm-xtensa/pgtable.h 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Copyright (C) 2001 - 2013 Tensilica Inc. 9 */ 10 11 #ifndef _XTENSA_PGTABLE_H 12 #define _XTENSA_PGTABLE_H 13 14 #include <asm-generic/pgtable-nopmd.h> 15 #include <asm/page.h> 16 #include <asm/kmem_layout.h> 17 18 /* 19 * We only use two ring levels, user and kernel space. 20 */ 21 22 #ifdef CONFIG_MMU 23 #define USER_RING 1 /* user ring level */ 24 #else 25 #define USER_RING 0 26 #endif 27 #define KERNEL_RING 0 /* kernel ring level */ 28 29 /* 30 * The Xtensa architecture port of Linux has a two-level page table system, 31 * i.e. the logical three-level Linux page table layout is folded. 32 * Each task has the following memory page tables: 33 * 34 * PGD table (page directory), ie. 3rd-level page table: 35 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables 36 * (Architectures that don't have the PMD folded point to the PMD tables) 37 * 38 * The pointer to the PGD table for a given task can be retrieved from 39 * the task structure (struct task_struct*) t, e.g. current(): 40 * (t->mm ? t->mm : t->active_mm)->pgd 41 * 42 * PMD tables (page middle-directory), ie. 2nd-level page tables: 43 * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1). 44 * 45 * PTE tables (page table entry), ie. 1st-level page tables: 46 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE 47 * invalid_pte_table for absent mappings. 48 * 49 * The individual pages are 4 kB big with special pages for the empty_zero_page. 50 */ 51 52 #define PGDIR_SHIFT 22 53 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 54 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 55 56 /* 57 * Entries per page directory level: we use two-level, so 58 * we don't really have any PMD directory physically. 59 */ 60 #define PTRS_PER_PTE 1024 61 #define PTRS_PER_PTE_SHIFT 10 62 #define PTRS_PER_PGD 1024 63 #define PGD_ORDER 0 64 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 65 #define FIRST_USER_ADDRESS 0UL 66 #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) 67 68 /* 69 * Virtual memory area. We keep a distance to other memory regions to be 70 * on the safe side. We also use this area for cache aliasing. 71 */ 72 #define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000) 73 #define VMALLOC_END (VMALLOC_START + 0x07FEFFFF) 74 #define TLBTEMP_BASE_1 (VMALLOC_END + 1) 75 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) 76 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE 77 #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE) 78 #else 79 #define TLBTEMP_SIZE ICACHE_WAY_SIZE 80 #endif 81 82 /* 83 * For the Xtensa architecture, the PTE layout is as follows: 84 * 85 * 31------12 11 10-9 8-6 5-4 3-2 1-0 86 * +-----------------------------------------+ 87 * | | Software | HARDWARE | 88 * | PPN | ADW | RI |Attribute| 89 * +-----------------------------------------+ 90 * pte_none | MBZ | 01 | 11 | 00 | 91 * +-----------------------------------------+ 92 * present | PPN | 0 | 00 | ADW | RI | CA | wx | 93 * +- - - - - - - - - - - - - - - - - - - - -+ 94 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 | 95 * +-----------------------------------------+ 96 * swap | index | type | 01 | 11 | 00 | 97 * +-----------------------------------------+ 98 * 99 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE) 100 * +-----------------------------------------+ 101 * present | PPN | 0 | 00 | ADW | RI | CA | w1 | 102 * +-----------------------------------------+ 103 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 | 104 * +-----------------------------------------+ 105 * 106 * Legend: 107 * PPN Physical Page Number 108 * ADW software: accessed (young) / dirty / writable 109 * RI ring (0=privileged, 1=user, 2 and 3 are unused) 110 * CA cache attribute: 00 bypass, 01 writeback, 10 writethrough 111 * (11 is invalid and used to mark pages that are not present) 112 * w page is writable (hw) 113 * x page is executable (hw) 114 * index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB) 115 * (note that the index is always non-zero) 116 * type swap type (5 bits -> 32 types) 117 * 118 * Notes: 119 * - (PROT_NONE) is a special case of 'present' but causes an exception for 120 * any access (read, write, and execute). 121 * - 'multihit-exception' has the highest priority of all MMU exceptions, 122 * so the ring must be set to 'RING_USER' even for 'non-present' pages. 123 * - on older hardware, the exectuable flag was not supported and 124 * used as a 'valid' flag, so it needs to be always set. 125 * - we need to keep track of certain flags in software (dirty and young) 126 * to do this, we use write exceptions and have a separate software w-flag. 127 * - attribute value 1101 (and 1111 on T1050 and earlier) is reserved 128 */ 129 130 #define _PAGE_ATTRIB_MASK 0xf 131 132 #define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */ 133 #define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */ 134 135 #define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */ 136 #define _PAGE_CA_WB (1<<2) /* write-back */ 137 #define _PAGE_CA_WT (2<<2) /* write-through */ 138 #define _PAGE_CA_MASK (3<<2) 139 #define _PAGE_CA_INVALID (3<<2) 140 141 /* We use invalid attribute values to distinguish special pte entries */ 142 #if XCHAL_HW_VERSION_MAJOR < 2000 143 #define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */ 144 #define _PAGE_NONE 0x04 145 #else 146 #define _PAGE_HW_VALID 0x00 147 #define _PAGE_NONE 0x0f 148 #endif 149 150 #define _PAGE_USER (1<<4) /* user access (ring=1) */ 151 152 /* Software */ 153 #define _PAGE_WRITABLE_BIT 6 154 #define _PAGE_WRITABLE (1<<6) /* software: page writable */ 155 #define _PAGE_DIRTY (1<<7) /* software: page dirty */ 156 #define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */ 157 158 #ifdef CONFIG_MMU 159 160 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 161 #define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED) 162 163 #define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER) 164 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER) 165 #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) 166 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER) 167 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) 168 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE) 169 #define PAGE_SHARED_EXEC \ 170 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC) 171 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE) 172 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC) 173 174 #if (DCACHE_WAY_SIZE > PAGE_SIZE) 175 # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS) 176 #else 177 # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB) 178 #endif 179 180 #else /* no mmu */ 181 182 # define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 183 # define PAGE_NONE __pgprot(0) 184 # define PAGE_SHARED __pgprot(0) 185 # define PAGE_COPY __pgprot(0) 186 # define PAGE_READONLY __pgprot(0) 187 # define PAGE_KERNEL __pgprot(0) 188 189 #endif 190 191 /* 192 * On certain configurations of Xtensa MMUs (eg. the initial Linux config), 193 * the MMU can't do page protection for execute, and considers that the same as 194 * read. Also, write permissions may imply read permissions. 195 * What follows is the closest we can get by reasonable means.. 196 * See linux/mm/mmap.c for protection_map[] array that uses these definitions. 197 */ 198 #define __P000 PAGE_NONE /* private --- */ 199 #define __P001 PAGE_READONLY /* private --r */ 200 #define __P010 PAGE_COPY /* private -w- */ 201 #define __P011 PAGE_COPY /* private -wr */ 202 #define __P100 PAGE_READONLY_EXEC /* private x-- */ 203 #define __P101 PAGE_READONLY_EXEC /* private x-r */ 204 #define __P110 PAGE_COPY_EXEC /* private xw- */ 205 #define __P111 PAGE_COPY_EXEC /* private xwr */ 206 207 #define __S000 PAGE_NONE /* shared --- */ 208 #define __S001 PAGE_READONLY /* shared --r */ 209 #define __S010 PAGE_SHARED /* shared -w- */ 210 #define __S011 PAGE_SHARED /* shared -wr */ 211 #define __S100 PAGE_READONLY_EXEC /* shared x-- */ 212 #define __S101 PAGE_READONLY_EXEC /* shared x-r */ 213 #define __S110 PAGE_SHARED_EXEC /* shared xw- */ 214 #define __S111 PAGE_SHARED_EXEC /* shared xwr */ 215 216 #ifndef __ASSEMBLY__ 217 218 #define pte_ERROR(e) \ 219 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 220 #define pgd_ERROR(e) \ 221 printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 222 223 extern unsigned long empty_zero_page[1024]; 224 225 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 226 227 #ifdef CONFIG_MMU 228 extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)]; 229 extern void paging_init(void); 230 #else 231 # define swapper_pg_dir NULL 232 static inline void paging_init(void) { } 233 #endif 234 static inline void pgtable_cache_init(void) { } 235 236 /* 237 * The pmd contains the kernel virtual address of the pte page. 238 */ 239 #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) 240 #define pmd_page(pmd) virt_to_page(pmd_val(pmd)) 241 242 /* 243 * pte status. 244 */ 245 # define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER)) 246 #if XCHAL_HW_VERSION_MAJOR < 2000 247 # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) 248 #else 249 # define pte_present(pte) \ 250 (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \ 251 || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE)) 252 #endif 253 #define pte_clear(mm,addr,ptep) \ 254 do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0) 255 256 #define pmd_none(pmd) (!pmd_val(pmd)) 257 #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK) 258 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 259 #define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0) 260 261 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; } 262 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 263 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 264 static inline int pte_special(pte_t pte) { return 0; } 265 266 static inline pte_t pte_wrprotect(pte_t pte) 267 { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; } 268 static inline pte_t pte_mkclean(pte_t pte) 269 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; } 270 static inline pte_t pte_mkold(pte_t pte) 271 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 272 static inline pte_t pte_mkdirty(pte_t pte) 273 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 274 static inline pte_t pte_mkyoung(pte_t pte) 275 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 276 static inline pte_t pte_mkwrite(pte_t pte) 277 { pte_val(pte) |= _PAGE_WRITABLE; return pte; } 278 static inline pte_t pte_mkspecial(pte_t pte) 279 { return pte; } 280 281 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CA_MASK)) 282 283 /* 284 * Conversion functions: convert a page and protection to a page entry, 285 * and a page entry and page directory to the page they refer to. 286 */ 287 288 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 289 #define pte_same(a,b) (pte_val(a) == pte_val(b)) 290 #define pte_page(x) pfn_to_page(pte_pfn(x)) 291 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 292 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 293 294 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 295 { 296 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 297 } 298 299 /* 300 * Certain architectures need to do special things when pte's 301 * within a page table are directly modified. Thus, the following 302 * hook is made available. 303 */ 304 static inline void update_pte(pte_t *ptep, pte_t pteval) 305 { 306 *ptep = pteval; 307 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK 308 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep)); 309 #endif 310 311 } 312 313 struct mm_struct; 314 315 static inline void 316 set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) 317 { 318 update_pte(ptep, pteval); 319 } 320 321 static inline void set_pte(pte_t *ptep, pte_t pteval) 322 { 323 update_pte(ptep, pteval); 324 } 325 326 static inline void 327 set_pmd(pmd_t *pmdp, pmd_t pmdval) 328 { 329 *pmdp = pmdval; 330 } 331 332 struct vm_area_struct; 333 334 static inline int 335 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, 336 pte_t *ptep) 337 { 338 pte_t pte = *ptep; 339 if (!pte_young(pte)) 340 return 0; 341 update_pte(ptep, pte_mkold(pte)); 342 return 1; 343 } 344 345 static inline pte_t 346 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 347 { 348 pte_t pte = *ptep; 349 pte_clear(mm, addr, ptep); 350 return pte; 351 } 352 353 static inline void 354 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 355 { 356 pte_t pte = *ptep; 357 update_pte(ptep, pte_wrprotect(pte)); 358 } 359 360 /* to find an entry in a kernel page-table-directory */ 361 #define pgd_offset_k(address) pgd_offset(&init_mm, address) 362 363 /* to find an entry in a page-table-directory */ 364 #define pgd_offset(mm,address) ((mm)->pgd + pgd_index(address)) 365 366 #define pgd_index(address) ((address) >> PGDIR_SHIFT) 367 368 /* Find an entry in the second-level page table.. */ 369 #define pmd_offset(dir,address) ((pmd_t*)(dir)) 370 371 /* Find an entry in the third-level page table.. */ 372 #define pte_index(address) (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) 373 #define pte_offset_kernel(dir,addr) \ 374 ((pte_t*) pmd_page_vaddr(*(dir)) + pte_index(addr)) 375 #define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr)) 376 #define pte_unmap(pte) do { } while (0) 377 378 379 /* 380 * Encode and decode a swap and file entry. 381 */ 382 #define SWP_TYPE_BITS 5 383 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) 384 385 #define __swp_type(entry) (((entry).val >> 6) & 0x1f) 386 #define __swp_offset(entry) ((entry).val >> 11) 387 #define __swp_entry(type,offs) \ 388 ((swp_entry_t){((type) << 6) | ((offs) << 11) | \ 389 _PAGE_CA_INVALID | _PAGE_USER}) 390 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 391 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 392 393 #endif /* !defined (__ASSEMBLY__) */ 394 395 396 #ifdef __ASSEMBLY__ 397 398 /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long), 399 * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long), 400 * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long) 401 * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long) 402 * 403 * Note: We require an additional temporary register which can be the same as 404 * the register that holds the address. 405 * 406 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr)) 407 * 408 */ 409 #define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT 410 #define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT 411 412 #define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \ 413 _PGD_INDEX(tmp, adr); \ 414 addx4 mm, tmp, mm 415 416 #define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \ 417 srli pmd, pmd, PAGE_SHIFT; \ 418 slli pmd, pmd, PAGE_SHIFT; \ 419 addx4 pmd, tmp, pmd 420 421 #else 422 423 #define kern_addr_valid(addr) (1) 424 425 extern void update_mmu_cache(struct vm_area_struct * vma, 426 unsigned long address, pte_t *ptep); 427 428 typedef pte_t *pte_addr_t; 429 430 #endif /* !defined (__ASSEMBLY__) */ 431 432 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 433 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 434 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 435 #define __HAVE_ARCH_PTEP_MKDIRTY 436 #define __HAVE_ARCH_PTE_SAME 437 /* We provide our own get_unmapped_area to cope with 438 * SHM area cache aliasing for userland. 439 */ 440 #define HAVE_ARCH_UNMAPPED_AREA 441 442 #include <asm-generic/pgtable.h> 443 444 #endif /* _XTENSA_PGTABLE_H */ 445