1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * include/asm-xtensa/pgtable.h 4 * 5 * Copyright (C) 2001 - 2013 Tensilica Inc. 6 */ 7 8 #ifndef _XTENSA_PGTABLE_H 9 #define _XTENSA_PGTABLE_H 10 11 #include <asm/page.h> 12 #include <asm/kmem_layout.h> 13 #include <asm-generic/pgtable-nopmd.h> 14 15 /* 16 * We only use two ring levels, user and kernel space. 17 */ 18 19 #ifdef CONFIG_MMU 20 #define USER_RING 1 /* user ring level */ 21 #else 22 #define USER_RING 0 23 #endif 24 #define KERNEL_RING 0 /* kernel ring level */ 25 26 /* 27 * The Xtensa architecture port of Linux has a two-level page table system, 28 * i.e. the logical three-level Linux page table layout is folded. 29 * Each task has the following memory page tables: 30 * 31 * PGD table (page directory), ie. 3rd-level page table: 32 * One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables 33 * (Architectures that don't have the PMD folded point to the PMD tables) 34 * 35 * The pointer to the PGD table for a given task can be retrieved from 36 * the task structure (struct task_struct*) t, e.g. current(): 37 * (t->mm ? t->mm : t->active_mm)->pgd 38 * 39 * PMD tables (page middle-directory), ie. 2nd-level page tables: 40 * Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1). 41 * 42 * PTE tables (page table entry), ie. 1st-level page tables: 43 * One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE 44 * invalid_pte_table for absent mappings. 45 * 46 * The individual pages are 4 kB big with special pages for the empty_zero_page. 47 */ 48 49 #define PGDIR_SHIFT 22 50 #define PGDIR_SIZE (1UL << PGDIR_SHIFT) 51 #define PGDIR_MASK (~(PGDIR_SIZE-1)) 52 53 /* 54 * Entries per page directory level: we use two-level, so 55 * we don't really have any PMD directory physically. 56 */ 57 #define PTRS_PER_PTE 1024 58 #define PTRS_PER_PTE_SHIFT 10 59 #define PTRS_PER_PGD 1024 60 #define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE) 61 #define FIRST_USER_PGD_NR (FIRST_USER_ADDRESS >> PGDIR_SHIFT) 62 63 #ifdef CONFIG_MMU 64 /* 65 * Virtual memory area. We keep a distance to other memory regions to be 66 * on the safe side. We also use this area for cache aliasing. 67 */ 68 #define VMALLOC_START (XCHAL_KSEG_CACHED_VADDR - 0x10000000) 69 #define VMALLOC_END (VMALLOC_START + 0x07FEFFFF) 70 #define TLBTEMP_BASE_1 (VMALLOC_START + 0x08000000) 71 #define TLBTEMP_BASE_2 (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE) 72 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE 73 #define TLBTEMP_SIZE (2 * DCACHE_WAY_SIZE) 74 #else 75 #define TLBTEMP_SIZE ICACHE_WAY_SIZE 76 #endif 77 78 #else 79 80 #define VMALLOC_START __XTENSA_UL_CONST(0) 81 #define VMALLOC_END __XTENSA_UL_CONST(0xffffffff) 82 83 #endif 84 85 /* 86 * For the Xtensa architecture, the PTE layout is as follows: 87 * 88 * 31------12 11 10-9 8-6 5-4 3-2 1-0 89 * +-----------------------------------------+ 90 * | | Software | HARDWARE | 91 * | PPN | ADW | RI |Attribute| 92 * +-----------------------------------------+ 93 * pte_none | MBZ | 01 | 11 | 00 | 94 * +-----------------------------------------+ 95 * present | PPN | 0 | 00 | ADW | RI | CA | wx | 96 * +- - - - - - - - - - - - - - - - - - - - -+ 97 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 11 | 11 | 98 * +-----------------------------------------+ 99 * swap | index | type | 01 | 11 | 00 | 100 * +-----------------------------------------+ 101 * 102 * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE) 103 * +-----------------------------------------+ 104 * present | PPN | 0 | 00 | ADW | RI | CA | w1 | 105 * +-----------------------------------------+ 106 * (PAGE_NONE)| PPN | 0 | 00 | ADW | 01 | 01 | 00 | 107 * +-----------------------------------------+ 108 * 109 * Legend: 110 * PPN Physical Page Number 111 * ADW software: accessed (young) / dirty / writable 112 * RI ring (0=privileged, 1=user, 2 and 3 are unused) 113 * CA cache attribute: 00 bypass, 01 writeback, 10 writethrough 114 * (11 is invalid and used to mark pages that are not present) 115 * w page is writable (hw) 116 * x page is executable (hw) 117 * index swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB) 118 * (note that the index is always non-zero) 119 * type swap type (5 bits -> 32 types) 120 * 121 * Notes: 122 * - (PROT_NONE) is a special case of 'present' but causes an exception for 123 * any access (read, write, and execute). 124 * - 'multihit-exception' has the highest priority of all MMU exceptions, 125 * so the ring must be set to 'RING_USER' even for 'non-present' pages. 126 * - on older hardware, the exectuable flag was not supported and 127 * used as a 'valid' flag, so it needs to be always set. 128 * - we need to keep track of certain flags in software (dirty and young) 129 * to do this, we use write exceptions and have a separate software w-flag. 130 * - attribute value 1101 (and 1111 on T1050 and earlier) is reserved 131 */ 132 133 #define _PAGE_ATTRIB_MASK 0xf 134 135 #define _PAGE_HW_EXEC (1<<0) /* hardware: page is executable */ 136 #define _PAGE_HW_WRITE (1<<1) /* hardware: page is writable */ 137 138 #define _PAGE_CA_BYPASS (0<<2) /* bypass, non-speculative */ 139 #define _PAGE_CA_WB (1<<2) /* write-back */ 140 #define _PAGE_CA_WT (2<<2) /* write-through */ 141 #define _PAGE_CA_MASK (3<<2) 142 #define _PAGE_CA_INVALID (3<<2) 143 144 /* We use invalid attribute values to distinguish special pte entries */ 145 #if XCHAL_HW_VERSION_MAJOR < 2000 146 #define _PAGE_HW_VALID 0x01 /* older HW needed this bit set */ 147 #define _PAGE_NONE 0x04 148 #else 149 #define _PAGE_HW_VALID 0x00 150 #define _PAGE_NONE 0x0f 151 #endif 152 153 #define _PAGE_USER (1<<4) /* user access (ring=1) */ 154 155 /* Software */ 156 #define _PAGE_WRITABLE_BIT 6 157 #define _PAGE_WRITABLE (1<<6) /* software: page writable */ 158 #define _PAGE_DIRTY (1<<7) /* software: page dirty */ 159 #define _PAGE_ACCESSED (1<<8) /* software: page accessed (read) */ 160 161 #ifdef CONFIG_MMU 162 163 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 164 #define _PAGE_PRESENT (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED) 165 166 #define PAGE_NONE __pgprot(_PAGE_NONE | _PAGE_USER) 167 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_USER) 168 #define PAGE_COPY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) 169 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_USER) 170 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC) 171 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE) 172 #define PAGE_SHARED_EXEC \ 173 __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC) 174 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE) 175 #define PAGE_KERNEL_RO __pgprot(_PAGE_PRESENT) 176 #define PAGE_KERNEL_EXEC __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC) 177 178 #if (DCACHE_WAY_SIZE > PAGE_SIZE) 179 # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS) 180 #else 181 # define _PAGE_DIRECTORY (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB) 182 #endif 183 184 #else /* no mmu */ 185 186 # define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) 187 # define PAGE_NONE __pgprot(0) 188 # define PAGE_SHARED __pgprot(0) 189 # define PAGE_COPY __pgprot(0) 190 # define PAGE_READONLY __pgprot(0) 191 # define PAGE_KERNEL __pgprot(0) 192 193 #endif 194 195 /* 196 * On certain configurations of Xtensa MMUs (eg. the initial Linux config), 197 * the MMU can't do page protection for execute, and considers that the same as 198 * read. Also, write permissions may imply read permissions. 199 * What follows is the closest we can get by reasonable means.. 200 * See linux/mm/mmap.c for protection_map[] array that uses these definitions. 201 */ 202 #ifndef __ASSEMBLY__ 203 204 #define pte_ERROR(e) \ 205 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) 206 #define pgd_ERROR(e) \ 207 printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e)) 208 209 extern unsigned long empty_zero_page[1024]; 210 211 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 212 213 #ifdef CONFIG_MMU 214 extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)]; 215 extern void paging_init(void); 216 #else 217 # define swapper_pg_dir NULL 218 static inline void paging_init(void) { } 219 #endif 220 221 /* 222 * The pmd contains the kernel virtual address of the pte page. 223 */ 224 #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK)) 225 #define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT) 226 #define pmd_page(pmd) virt_to_page(pmd_val(pmd)) 227 228 /* 229 * pte status. 230 */ 231 # define pte_none(pte) (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER)) 232 #if XCHAL_HW_VERSION_MAJOR < 2000 233 # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) 234 #else 235 # define pte_present(pte) \ 236 (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID) \ 237 || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE)) 238 #endif 239 #define pte_clear(mm,addr,ptep) \ 240 do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0) 241 242 #define pmd_none(pmd) (!pmd_val(pmd)) 243 #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK) 244 #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) 245 #define pmd_clear(pmdp) do { set_pmd(pmdp, __pmd(0)); } while (0) 246 247 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; } 248 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; } 249 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; } 250 251 static inline pte_t pte_wrprotect(pte_t pte) 252 { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; } 253 static inline pte_t pte_mkclean(pte_t pte) 254 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; } 255 static inline pte_t pte_mkold(pte_t pte) 256 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; } 257 static inline pte_t pte_mkdirty(pte_t pte) 258 { pte_val(pte) |= _PAGE_DIRTY; return pte; } 259 static inline pte_t pte_mkyoung(pte_t pte) 260 { pte_val(pte) |= _PAGE_ACCESSED; return pte; } 261 static inline pte_t pte_mkwrite(pte_t pte) 262 { pte_val(pte) |= _PAGE_WRITABLE; return pte; } 263 264 #define pgprot_noncached(prot) \ 265 ((__pgprot((pgprot_val(prot) & ~_PAGE_CA_MASK) | \ 266 _PAGE_CA_BYPASS))) 267 268 /* 269 * Conversion functions: convert a page and protection to a page entry, 270 * and a page entry and page directory to the page they refer to. 271 */ 272 273 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT) 274 #define pte_same(a,b) (pte_val(a) == pte_val(b)) 275 #define pte_page(x) pfn_to_page(pte_pfn(x)) 276 #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) 277 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot) 278 279 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 280 { 281 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)); 282 } 283 284 /* 285 * Certain architectures need to do special things when pte's 286 * within a page table are directly modified. Thus, the following 287 * hook is made available. 288 */ 289 static inline void update_pte(pte_t *ptep, pte_t pteval) 290 { 291 *ptep = pteval; 292 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK 293 __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep)); 294 #endif 295 296 } 297 298 struct mm_struct; 299 300 static inline void 301 set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pteval) 302 { 303 update_pte(ptep, pteval); 304 } 305 306 static inline void set_pte(pte_t *ptep, pte_t pteval) 307 { 308 update_pte(ptep, pteval); 309 } 310 311 static inline void 312 set_pmd(pmd_t *pmdp, pmd_t pmdval) 313 { 314 *pmdp = pmdval; 315 } 316 317 struct vm_area_struct; 318 319 static inline int 320 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr, 321 pte_t *ptep) 322 { 323 pte_t pte = *ptep; 324 if (!pte_young(pte)) 325 return 0; 326 update_pte(ptep, pte_mkold(pte)); 327 return 1; 328 } 329 330 static inline pte_t 331 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 332 { 333 pte_t pte = *ptep; 334 pte_clear(mm, addr, ptep); 335 return pte; 336 } 337 338 static inline void 339 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep) 340 { 341 pte_t pte = *ptep; 342 update_pte(ptep, pte_wrprotect(pte)); 343 } 344 345 /* 346 * Encode and decode a swap and file entry. 347 */ 348 #define SWP_TYPE_BITS 5 349 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS) 350 351 #define __swp_type(entry) (((entry).val >> 6) & 0x1f) 352 #define __swp_offset(entry) ((entry).val >> 11) 353 #define __swp_entry(type,offs) \ 354 ((swp_entry_t){((type) << 6) | ((offs) << 11) | \ 355 _PAGE_CA_INVALID | _PAGE_USER}) 356 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) 357 #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) 358 359 #endif /* !defined (__ASSEMBLY__) */ 360 361 362 #ifdef __ASSEMBLY__ 363 364 /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long), 365 * _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long), 366 * _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long) 367 * _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long) 368 * 369 * Note: We require an additional temporary register which can be the same as 370 * the register that holds the address. 371 * 372 * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr)) 373 * 374 */ 375 #define _PGD_INDEX(rt,rs) extui rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT 376 #define _PTE_INDEX(rt,rs) extui rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT 377 378 #define _PGD_OFFSET(mm,adr,tmp) l32i mm, mm, MM_PGD; \ 379 _PGD_INDEX(tmp, adr); \ 380 addx4 mm, tmp, mm 381 382 #define _PTE_OFFSET(pmd,adr,tmp) _PTE_INDEX(tmp, adr); \ 383 srli pmd, pmd, PAGE_SHIFT; \ 384 slli pmd, pmd, PAGE_SHIFT; \ 385 addx4 pmd, tmp, pmd 386 387 #else 388 389 extern void update_mmu_cache(struct vm_area_struct * vma, 390 unsigned long address, pte_t *ptep); 391 392 typedef pte_t *pte_addr_t; 393 394 void update_mmu_tlb(struct vm_area_struct *vma, 395 unsigned long address, pte_t *ptep); 396 #define __HAVE_ARCH_UPDATE_MMU_TLB 397 398 #endif /* !defined (__ASSEMBLY__) */ 399 400 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG 401 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR 402 #define __HAVE_ARCH_PTEP_SET_WRPROTECT 403 #define __HAVE_ARCH_PTEP_MKDIRTY 404 #define __HAVE_ARCH_PTE_SAME 405 /* We provide our own get_unmapped_area to cope with 406 * SHM area cache aliasing for userland. 407 */ 408 #define HAVE_ARCH_UNMAPPED_AREA 409 410 #endif /* _XTENSA_PGTABLE_H */ 411