1f1883aa7SMax Filippov /* 2f1883aa7SMax Filippov * Kernel virtual memory layout definitions. 3f1883aa7SMax Filippov * 4f1883aa7SMax Filippov * This file is subject to the terms and conditions of the GNU General 5f1883aa7SMax Filippov * Public License. See the file "COPYING" in the main directory of 6f1883aa7SMax Filippov * this archive for more details. 7f1883aa7SMax Filippov * 8f1883aa7SMax Filippov * Copyright (C) 2016 Cadence Design Systems Inc. 9f1883aa7SMax Filippov */ 10f1883aa7SMax Filippov 11f1883aa7SMax Filippov #ifndef _XTENSA_KMEM_LAYOUT_H 12f1883aa7SMax Filippov #define _XTENSA_KMEM_LAYOUT_H 13f1883aa7SMax Filippov 14f1883aa7SMax Filippov #include <asm/types.h> 15f1883aa7SMax Filippov 16d39af902SMax Filippov #ifdef CONFIG_MMU 17d39af902SMax Filippov 18f1883aa7SMax Filippov /* 19f1883aa7SMax Filippov * Fixed TLB translations in the processor. 20f1883aa7SMax Filippov */ 21f1883aa7SMax Filippov 22d39af902SMax Filippov #define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000) 23d39af902SMax Filippov #define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000) 24d39af902SMax Filippov 25d39af902SMax Filippov #if defined(CONFIG_XTENSA_KSEG_MMU_V2) 26d39af902SMax Filippov 27f1883aa7SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) 28f1883aa7SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) 29f1883aa7SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) 30d39af902SMax Filippov #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000) 31d39af902SMax Filippov #define XCHAL_KSEG_TLB_WAY 5 32a9f2fc62SMax Filippov #define XCHAL_KIO_TLB_WAY 6 33d39af902SMax Filippov 34d39af902SMax Filippov #elif defined(CONFIG_XTENSA_KSEG_256M) 35d39af902SMax Filippov 36d39af902SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000) 37d39af902SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) 38d39af902SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000) 39d39af902SMax Filippov #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) 40d39af902SMax Filippov #define XCHAL_KSEG_TLB_WAY 6 41a9f2fc62SMax Filippov #define XCHAL_KIO_TLB_WAY 6 42d39af902SMax Filippov 43d39af902SMax Filippov #elif defined(CONFIG_XTENSA_KSEG_512M) 44d39af902SMax Filippov 45d39af902SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000) 46d39af902SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000) 47d39af902SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000) 48d39af902SMax Filippov #define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000) 49d39af902SMax Filippov #define XCHAL_KSEG_TLB_WAY 6 50a9f2fc62SMax Filippov #define XCHAL_KIO_TLB_WAY 6 51d39af902SMax Filippov 52d39af902SMax Filippov #else 53d39af902SMax Filippov #error Unsupported KSEG configuration 54d39af902SMax Filippov #endif 55d39af902SMax Filippov 56d39af902SMax Filippov #ifdef CONFIG_KSEG_PADDR 57d39af902SMax Filippov #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR) 58d39af902SMax Filippov #else 59f1883aa7SMax Filippov #define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000) 60d39af902SMax Filippov #endif 61d39af902SMax Filippov 62d39af902SMax Filippov #if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1) 63d39af902SMax Filippov #error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT 64d39af902SMax Filippov #endif 65d39af902SMax Filippov 66d39af902SMax Filippov #else 67d39af902SMax Filippov 68d39af902SMax Filippov #define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000) 69d39af902SMax Filippov #define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000) 70d39af902SMax Filippov #define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000) 71d39af902SMax Filippov 72d39af902SMax Filippov #endif 73f1883aa7SMax Filippov 74f4431396SMax Filippov #define KERNEL_STACK_SHIFT 13 75f4431396SMax Filippov #define KERNEL_STACK_SIZE (1 << KERNEL_STACK_SHIFT) 76f4431396SMax Filippov 77f1883aa7SMax Filippov #endif 78