1 /* 2 * arch/xtensa/include/asm/initialize_mmu.h 3 * 4 * Initializes MMU: 5 * 6 * For the new V3 MMU we remap the TLB from virtual == physical 7 * to the standard Linux mapping used in earlier MMU's. 8 * 9 * The the MMU we also support a new configuration register that 10 * specifies how the S32C1I instruction operates with the cache 11 * controller. 12 * 13 * This file is subject to the terms and conditions of the GNU General 14 * Public License. See the file "COPYING" in the main directory of 15 * this archive for more details. 16 * 17 * Copyright (C) 2008 - 2012 Tensilica, Inc. 18 * 19 * Marc Gauthier <marc@tensilica.com> 20 * Pete Delaney <piet@tensilica.com> 21 */ 22 23 #ifndef _XTENSA_INITIALIZE_MMU_H 24 #define _XTENSA_INITIALIZE_MMU_H 25 26 #ifdef __ASSEMBLY__ 27 28 #define XTENSA_HWVERSION_RC_2009_0 230000 29 30 .macro initialize_mmu 31 32 #if XCHAL_HAVE_S32C1I && (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) 33 /* 34 * We Have Atomic Operation Control (ATOMCTL) Register; Initialize it. 35 * For details see Documentation/xtensa/atomctl.txt 36 */ 37 #if XCHAL_DCACHE_IS_COHERENT 38 movi a3, 0x25 /* For SMP/MX -- internal for writeback, 39 * RCW otherwise 40 */ 41 #else 42 movi a3, 0x29 /* non-MX -- Most cores use Std Memory 43 * Controlers which usually can't use RCW 44 */ 45 #endif 46 wsr a3, atomctl 47 #endif /* XCHAL_HAVE_S32C1I && 48 * (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0) 49 */ 50 51 .endm 52 53 #endif /*__ASSEMBLY__*/ 54 55 #endif /* _XTENSA_INITIALIZE_MMU_H */ 56