1367b8112SChris Zankel /* 2367b8112SChris Zankel * include/asm-xtensa/coprocessor.h 3367b8112SChris Zankel * 4367b8112SChris Zankel * This file is subject to the terms and conditions of the GNU General Public 5367b8112SChris Zankel * License. See the file "COPYING" in the main directory of this archive 6367b8112SChris Zankel * for more details. 7367b8112SChris Zankel * 8367b8112SChris Zankel * Copyright (C) 2003 - 2007 Tensilica Inc. 9367b8112SChris Zankel */ 10367b8112SChris Zankel 11367b8112SChris Zankel 12367b8112SChris Zankel #ifndef _XTENSA_COPROCESSOR_H 13367b8112SChris Zankel #define _XTENSA_COPROCESSOR_H 14367b8112SChris Zankel 15367b8112SChris Zankel #include <linux/stringify.h> 16367b8112SChris Zankel #include <variant/tie.h> 17367b8112SChris Zankel #include <asm/types.h> 18367b8112SChris Zankel 19367b8112SChris Zankel #ifdef __ASSEMBLY__ 20367b8112SChris Zankel # include <variant/tie-asm.h> 21367b8112SChris Zankel 22367b8112SChris Zankel .macro xchal_sa_start a b 23367b8112SChris Zankel .set .Lxchal_pofs_, 0 24367b8112SChris Zankel .set .Lxchal_ofs_, 0 25367b8112SChris Zankel .endm 26367b8112SChris Zankel 27367b8112SChris Zankel .macro xchal_sa_align ptr minofs maxofs ofsalign totalign 28367b8112SChris Zankel .set .Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_ + \totalign - 1 29367b8112SChris Zankel .set .Lxchal_ofs_, (.Lxchal_ofs_ & -\totalign) - .Lxchal_pofs_ 30367b8112SChris Zankel .endm 31367b8112SChris Zankel 32367b8112SChris Zankel #define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \ 33367b8112SChris Zankel | XTHAL_SAS_CC \ 34367b8112SChris Zankel | XTHAL_SAS_CALR | XTHAL_SAS_CALE ) 35367b8112SChris Zankel 36367b8112SChris Zankel .macro save_xtregs_opt ptr clb at1 at2 at3 at4 offset 37367b8112SChris Zankel .if XTREGS_OPT_SIZE > 0 38367b8112SChris Zankel addi \clb, \ptr, \offset 39367b8112SChris Zankel xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT 40367b8112SChris Zankel .endif 41367b8112SChris Zankel .endm 42367b8112SChris Zankel 43367b8112SChris Zankel .macro load_xtregs_opt ptr clb at1 at2 at3 at4 offset 44367b8112SChris Zankel .if XTREGS_OPT_SIZE > 0 45367b8112SChris Zankel addi \clb, \ptr, \offset 46367b8112SChris Zankel xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT 47367b8112SChris Zankel .endif 48367b8112SChris Zankel .endm 49367b8112SChris Zankel #undef _SELECT 50367b8112SChris Zankel 51367b8112SChris Zankel #define _SELECT ( XTHAL_SAS_TIE | XTHAL_SAS_OPT \ 52367b8112SChris Zankel | XTHAL_SAS_NOCC \ 53367b8112SChris Zankel | XTHAL_SAS_CALR | XTHAL_SAS_CALE | XTHAL_SAS_GLOB ) 54367b8112SChris Zankel 55367b8112SChris Zankel .macro save_xtregs_user ptr clb at1 at2 at3 at4 offset 56367b8112SChris Zankel .if XTREGS_USER_SIZE > 0 57367b8112SChris Zankel addi \clb, \ptr, \offset 58367b8112SChris Zankel xchal_ncp_store \clb \at1 \at2 \at3 \at4 select=_SELECT 59367b8112SChris Zankel .endif 60367b8112SChris Zankel .endm 61367b8112SChris Zankel 62367b8112SChris Zankel .macro load_xtregs_user ptr clb at1 at2 at3 at4 offset 63367b8112SChris Zankel .if XTREGS_USER_SIZE > 0 64367b8112SChris Zankel addi \clb, \ptr, \offset 65367b8112SChris Zankel xchal_ncp_load \clb \at1 \at2 \at3 \at4 select=_SELECT 66367b8112SChris Zankel .endif 67367b8112SChris Zankel .endm 68367b8112SChris Zankel #undef _SELECT 69367b8112SChris Zankel 70367b8112SChris Zankel 71367b8112SChris Zankel 72367b8112SChris Zankel #endif /* __ASSEMBLY__ */ 73367b8112SChris Zankel 74367b8112SChris Zankel /* 75367b8112SChris Zankel * XTENSA_HAVE_COPROCESSOR(x) returns 1 if coprocessor x is configured. 76367b8112SChris Zankel * 77367b8112SChris Zankel * XTENSA_HAVE_IO_PORT(x) returns 1 if io-port x is configured. 78367b8112SChris Zankel * 79367b8112SChris Zankel */ 80367b8112SChris Zankel 81367b8112SChris Zankel #define XTENSA_HAVE_COPROCESSOR(x) \ 82367b8112SChris Zankel ((XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) & (1 << (x))) 83367b8112SChris Zankel #define XTENSA_HAVE_COPROCESSORS \ 84367b8112SChris Zankel (XCHAL_CP_MASK ^ XCHAL_CP_PORT_MASK) 85367b8112SChris Zankel #define XTENSA_HAVE_IO_PORT(x) \ 86367b8112SChris Zankel (XCHAL_CP_PORT_MASK & (1 << (x))) 87367b8112SChris Zankel #define XTENSA_HAVE_IO_PORTS \ 88367b8112SChris Zankel XCHAL_CP_PORT_MASK 89367b8112SChris Zankel 90367b8112SChris Zankel #ifndef __ASSEMBLY__ 91367b8112SChris Zankel 92367b8112SChris Zankel 93367b8112SChris Zankel #if XCHAL_HAVE_CP 94367b8112SChris Zankel 95367b8112SChris Zankel #define RSR_CPENABLE(x) do { \ 96367b8112SChris Zankel __asm__ __volatile__("rsr %0," __stringify(CPENABLE) : "=a" (x)); \ 97367b8112SChris Zankel } while(0); 98367b8112SChris Zankel #define WSR_CPENABLE(x) do { \ 99367b8112SChris Zankel __asm__ __volatile__("wsr %0," __stringify(CPENABLE) "; rsync" \ 100367b8112SChris Zankel :: "a" (x)); \ 101367b8112SChris Zankel } while(0); 102367b8112SChris Zankel 103367b8112SChris Zankel #endif /* XCHAL_HAVE_CP */ 104367b8112SChris Zankel 105367b8112SChris Zankel 106367b8112SChris Zankel /* 107367b8112SChris Zankel * Additional registers. 108367b8112SChris Zankel * We define three types of additional registers: 109367b8112SChris Zankel * ext: extra registers that are used by the compiler 110367b8112SChris Zankel * cpn: optional registers that can be used by a user application 111367b8112SChris Zankel * cpX: coprocessor registers that can only be used if the corresponding 112367b8112SChris Zankel * CPENABLE bit is set. 113367b8112SChris Zankel */ 114367b8112SChris Zankel 115367b8112SChris Zankel #define XCHAL_SA_REG(list,cc,abi,type,y,name,z,align,size,...) \ 116367b8112SChris Zankel __REG ## list (cc, abi, type, name, size, align) 117367b8112SChris Zankel 118367b8112SChris Zankel #define __REG0(cc,abi,t,name,s,a) __REG0_ ## cc (abi,name) 119367b8112SChris Zankel #define __REG1(cc,abi,t,name,s,a) __REG1_ ## cc (name) 120367b8112SChris Zankel #define __REG2(cc,abi,type,...) __REG2_ ## type (__VA_ARGS__) 121367b8112SChris Zankel 122367b8112SChris Zankel #define __REG0_0(abi,name) 123367b8112SChris Zankel #define __REG0_1(abi,name) __REG0_1 ## abi (name) 124367b8112SChris Zankel #define __REG0_10(name) __u32 name; 125367b8112SChris Zankel #define __REG0_11(name) __u32 name; 126367b8112SChris Zankel #define __REG0_12(name) 127367b8112SChris Zankel 128367b8112SChris Zankel #define __REG1_0(name) __u32 name; 129367b8112SChris Zankel #define __REG1_1(name) 130367b8112SChris Zankel 131367b8112SChris Zankel #define __REG2_0(n,s,a) __u32 name; 132367b8112SChris Zankel #define __REG2_1(n,s,a) unsigned char n[s] __attribute__ ((aligned(a))); 133367b8112SChris Zankel #define __REG2_2(n,s,a) unsigned char n[s] __attribute__ ((aligned(a))); 134367b8112SChris Zankel 135367b8112SChris Zankel typedef struct { XCHAL_NCP_SA_LIST(0) } xtregs_opt_t 136367b8112SChris Zankel __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN))); 137367b8112SChris Zankel typedef struct { XCHAL_NCP_SA_LIST(1) } xtregs_user_t 138367b8112SChris Zankel __attribute__ ((aligned (XCHAL_NCP_SA_ALIGN))); 139367b8112SChris Zankel 140367b8112SChris Zankel #if XTENSA_HAVE_COPROCESSORS 141367b8112SChris Zankel 142367b8112SChris Zankel typedef struct { XCHAL_CP0_SA_LIST(2) } xtregs_cp0_t 143367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP0_SA_ALIGN))); 144367b8112SChris Zankel typedef struct { XCHAL_CP1_SA_LIST(2) } xtregs_cp1_t 145367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP1_SA_ALIGN))); 146367b8112SChris Zankel typedef struct { XCHAL_CP2_SA_LIST(2) } xtregs_cp2_t 147367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP2_SA_ALIGN))); 148367b8112SChris Zankel typedef struct { XCHAL_CP3_SA_LIST(2) } xtregs_cp3_t 149367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP3_SA_ALIGN))); 150367b8112SChris Zankel typedef struct { XCHAL_CP4_SA_LIST(2) } xtregs_cp4_t 151367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP4_SA_ALIGN))); 152367b8112SChris Zankel typedef struct { XCHAL_CP5_SA_LIST(2) } xtregs_cp5_t 153367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP5_SA_ALIGN))); 154367b8112SChris Zankel typedef struct { XCHAL_CP6_SA_LIST(2) } xtregs_cp6_t 155367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP6_SA_ALIGN))); 156367b8112SChris Zankel typedef struct { XCHAL_CP7_SA_LIST(2) } xtregs_cp7_t 157367b8112SChris Zankel __attribute__ ((aligned (XCHAL_CP7_SA_ALIGN))); 158367b8112SChris Zankel 159367b8112SChris Zankel extern struct thread_info* coprocessor_owner[XCHAL_CP_MAX]; 160367b8112SChris Zankel extern void coprocessor_save(void*, int); 161367b8112SChris Zankel extern void coprocessor_load(void*, int); 162367b8112SChris Zankel extern void coprocessor_flush(struct thread_info*, int); 163367b8112SChris Zankel extern void coprocessor_restore(struct thread_info*, int); 164367b8112SChris Zankel 165367b8112SChris Zankel extern void coprocessor_release_all(struct thread_info*); 166367b8112SChris Zankel extern void coprocessor_flush_all(struct thread_info*); 167367b8112SChris Zankel 168367b8112SChris Zankel static inline void coprocessor_clear_cpenable(void) 169367b8112SChris Zankel { 170367b8112SChris Zankel unsigned long i = 0; 171367b8112SChris Zankel WSR_CPENABLE(i); 172367b8112SChris Zankel } 173367b8112SChris Zankel 174367b8112SChris Zankel #endif /* XTENSA_HAVE_COPROCESSORS */ 175367b8112SChris Zankel 176367b8112SChris Zankel #endif /* !__ASSEMBLY__ */ 177367b8112SChris Zankel #endif /* _XTENSA_COPROCESSOR_H */ 178