1 /* 2 * include/asm-xtensa/atomic.h 3 * 4 * Atomic operations that C can't guarantee us. Useful for resource counting.. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 2001 - 2008 Tensilica Inc. 11 */ 12 13 #ifndef _XTENSA_ATOMIC_H 14 #define _XTENSA_ATOMIC_H 15 16 #include <linux/stringify.h> 17 #include <linux/types.h> 18 #include <asm/processor.h> 19 #include <asm/cmpxchg.h> 20 #include <asm/barrier.h> 21 22 #define ATOMIC_INIT(i) { (i) } 23 24 /* 25 * This Xtensa implementation assumes that the right mechanism 26 * for exclusion is for locking interrupts to level EXCM_LEVEL. 27 * 28 * Locking interrupts looks like this: 29 * 30 * rsil a15, TOPLEVEL 31 * <code> 32 * wsr a15, PS 33 * rsync 34 * 35 * Note that a15 is used here because the register allocation 36 * done by the compiler is not guaranteed and a window overflow 37 * may not occur between the rsil and wsr instructions. By using 38 * a15 in the rsil, the machine is guaranteed to be in a state 39 * where no register reference will cause an overflow. 40 */ 41 42 /** 43 * atomic_read - read atomic variable 44 * @v: pointer of type atomic_t 45 * 46 * Atomically reads the value of @v. 47 */ 48 #define atomic_read(v) READ_ONCE((v)->counter) 49 50 /** 51 * atomic_set - set atomic variable 52 * @v: pointer of type atomic_t 53 * @i: required value 54 * 55 * Atomically sets the value of @v to @i. 56 */ 57 #define atomic_set(v,i) WRITE_ONCE((v)->counter, (i)) 58 59 #if XCHAL_HAVE_S32C1I 60 #define ATOMIC_OP(op) \ 61 static inline void atomic_##op(int i, atomic_t * v) \ 62 { \ 63 unsigned long tmp; \ 64 int result; \ 65 \ 66 __asm__ __volatile__( \ 67 "1: l32i %1, %3, 0\n" \ 68 " wsr %1, scompare1\n" \ 69 " " #op " %0, %1, %2\n" \ 70 " s32c1i %0, %3, 0\n" \ 71 " bne %0, %1, 1b\n" \ 72 : "=&a" (result), "=&a" (tmp) \ 73 : "a" (i), "a" (v) \ 74 : "memory" \ 75 ); \ 76 } \ 77 78 #define ATOMIC_OP_RETURN(op) \ 79 static inline int atomic_##op##_return(int i, atomic_t * v) \ 80 { \ 81 unsigned long tmp; \ 82 int result; \ 83 \ 84 __asm__ __volatile__( \ 85 "1: l32i %1, %3, 0\n" \ 86 " wsr %1, scompare1\n" \ 87 " " #op " %0, %1, %2\n" \ 88 " s32c1i %0, %3, 0\n" \ 89 " bne %0, %1, 1b\n" \ 90 " " #op " %0, %0, %2\n" \ 91 : "=&a" (result), "=&a" (tmp) \ 92 : "a" (i), "a" (v) \ 93 : "memory" \ 94 ); \ 95 \ 96 return result; \ 97 } 98 99 #define ATOMIC_FETCH_OP(op) \ 100 static inline int atomic_fetch_##op(int i, atomic_t * v) \ 101 { \ 102 unsigned long tmp; \ 103 int result; \ 104 \ 105 __asm__ __volatile__( \ 106 "1: l32i %1, %3, 0\n" \ 107 " wsr %1, scompare1\n" \ 108 " " #op " %0, %1, %2\n" \ 109 " s32c1i %0, %3, 0\n" \ 110 " bne %0, %1, 1b\n" \ 111 : "=&a" (result), "=&a" (tmp) \ 112 : "a" (i), "a" (v) \ 113 : "memory" \ 114 ); \ 115 \ 116 return result; \ 117 } 118 119 #else /* XCHAL_HAVE_S32C1I */ 120 121 #define ATOMIC_OP(op) \ 122 static inline void atomic_##op(int i, atomic_t * v) \ 123 { \ 124 unsigned int vval; \ 125 \ 126 __asm__ __volatile__( \ 127 " rsil a15, "__stringify(TOPLEVEL)"\n"\ 128 " l32i %0, %2, 0\n" \ 129 " " #op " %0, %0, %1\n" \ 130 " s32i %0, %2, 0\n" \ 131 " wsr a15, ps\n" \ 132 " rsync\n" \ 133 : "=&a" (vval) \ 134 : "a" (i), "a" (v) \ 135 : "a15", "memory" \ 136 ); \ 137 } \ 138 139 #define ATOMIC_OP_RETURN(op) \ 140 static inline int atomic_##op##_return(int i, atomic_t * v) \ 141 { \ 142 unsigned int vval; \ 143 \ 144 __asm__ __volatile__( \ 145 " rsil a15,"__stringify(TOPLEVEL)"\n" \ 146 " l32i %0, %2, 0\n" \ 147 " " #op " %0, %0, %1\n" \ 148 " s32i %0, %2, 0\n" \ 149 " wsr a15, ps\n" \ 150 " rsync\n" \ 151 : "=&a" (vval) \ 152 : "a" (i), "a" (v) \ 153 : "a15", "memory" \ 154 ); \ 155 \ 156 return vval; \ 157 } 158 159 #define ATOMIC_FETCH_OP(op) \ 160 static inline int atomic_fetch_##op(int i, atomic_t * v) \ 161 { \ 162 unsigned int tmp, vval; \ 163 \ 164 __asm__ __volatile__( \ 165 " rsil a15,"__stringify(TOPLEVEL)"\n" \ 166 " l32i %0, %3, 0\n" \ 167 " " #op " %1, %0, %2\n" \ 168 " s32i %1, %3, 0\n" \ 169 " wsr a15, ps\n" \ 170 " rsync\n" \ 171 : "=&a" (vval), "=&a" (tmp) \ 172 : "a" (i), "a" (v) \ 173 : "a15", "memory" \ 174 ); \ 175 \ 176 return vval; \ 177 } 178 179 #endif /* XCHAL_HAVE_S32C1I */ 180 181 #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) ATOMIC_OP_RETURN(op) 182 183 ATOMIC_OPS(add) 184 ATOMIC_OPS(sub) 185 186 #undef ATOMIC_OPS 187 #define ATOMIC_OPS(op) ATOMIC_OP(op) ATOMIC_FETCH_OP(op) 188 189 ATOMIC_OPS(and) 190 ATOMIC_OPS(or) 191 ATOMIC_OPS(xor) 192 193 #undef ATOMIC_OPS 194 #undef ATOMIC_FETCH_OP 195 #undef ATOMIC_OP_RETURN 196 #undef ATOMIC_OP 197 198 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n))) 199 #define atomic_xchg(v, new) (xchg(&((v)->counter), new)) 200 201 #endif /* _XTENSA_ATOMIC_H */ 202