1/ { 2 compatible = "cdns,xtensa-xtfpga"; 3 #address-cells = <1>; 4 #size-cells = <1>; 5 interrupt-parent = <&pic>; 6 7 chosen { 8 bootargs = "earlycon=uart8250,mmio32native,0xfd050020,115200n8 console=ttyS0,115200n8 ip=dhcp root=/dev/nfs rw debug"; 9 }; 10 11 memory@0 { 12 device_type = "memory"; 13 reg = <0x00000000 0x06000000>; 14 }; 15 16 cpus { 17 #address-cells = <1>; 18 #size-cells = <0>; 19 cpu@0 { 20 compatible = "cdns,xtensa-cpu"; 21 reg = <0>; 22 /* Filled in by platform_setup from FPGA register 23 * clock-frequency = <100000000>; 24 */ 25 }; 26 }; 27 28 pic: pic { 29 compatible = "cdns,xtensa-pic"; 30 /* one cell: internal irq number, 31 * two cells: second cell == 0: internal irq number 32 * second cell == 1: external irq number 33 */ 34 #interrupt-cells = <2>; 35 interrupt-controller; 36 }; 37 38 clocks { 39 clk54: clk54 { 40 #clock-cells = <0>; 41 compatible = "fixed-clock"; 42 clock-frequency = <54000000>; 43 }; 44 }; 45 46 soc { 47 #address-cells = <1>; 48 #size-cells = <1>; 49 compatible = "simple-bus"; 50 ranges = <0x00000000 0xf0000000 0x10000000>; 51 52 osc: main-oscillator { 53 #clock-cells = <0>; 54 compatible = "cdns,xtfpga-clock"; 55 reg = <0x0d020004 0x4>; 56 }; 57 58 serial0: serial@0d050020 { 59 device_type = "serial"; 60 compatible = "ns16550a"; 61 no-loopback-test; 62 reg = <0x0d050020 0x20>; 63 reg-shift = <2>; 64 reg-io-width = <4>; 65 native-endian; 66 interrupts = <0 1>; /* external irq 0 */ 67 clocks = <&osc>; 68 }; 69 70 enet0: ethoc@0d030000 { 71 compatible = "opencores,ethoc"; 72 reg = <0x0d030000 0x4000 0x0d800000 0x4000>; 73 native-endian; 74 interrupts = <1 1>; /* external irq 1 */ 75 local-mac-address = [00 50 c2 13 6f 00]; 76 clocks = <&osc>; 77 }; 78 79 i2s0: xtfpga-i2s@0d080000 { 80 #sound-dai-cells = <0>; 81 compatible = "cdns,xtfpga-i2s"; 82 reg = <0x0d080000 0x40>; 83 interrupts = <2 1>; /* external irq 2 */ 84 clocks = <&cdce706 4>; 85 }; 86 87 i2c0: i2c-master@0d090000 { 88 compatible = "opencores,i2c-ocores"; 89 #address-cells = <1>; 90 #size-cells = <0>; 91 reg = <0x0d090000 0x20>; 92 reg-shift = <2>; 93 reg-io-width = <4>; 94 native-endian; 95 interrupts = <4 1>; 96 clocks = <&osc>; 97 98 cdce706: clock-synth@69 { 99 compatible = "ti,cdce706"; 100 #clock-cells = <1>; 101 reg = <0x69>; 102 clocks = <&clk54>; 103 clock-names = "clk_in0"; 104 }; 105 }; 106 107 spi0: spi-master@0d0a0000 { 108 compatible = "cdns,xtfpga-spi"; 109 #address-cells = <1>; 110 #size-cells = <0>; 111 reg = <0x0d0a0000 0xc>; 112 113 tlv320aic23: sound-codec@0 { 114 #sound-dai-cells = <0>; 115 compatible = "tlv320aic23"; 116 reg = <0>; 117 spi-max-frequency = <12500000>; 118 }; 119 }; 120 }; 121 122 sound { 123 compatible = "simple-audio-card"; 124 simple-audio-card,format = "i2s"; 125 simple-audio-card,mclk-fs = <256>; 126 127 simple-audio-card,cpu { 128 sound-dai = <&i2s0>; 129 }; 130 131 simple-audio-card,codec { 132 sound-dai = <&tlv320aic23>; 133 simple-audio-card,bitclock-master = <0>; 134 simple-audio-card,frame-master = <0>; 135 clocks = <&cdce706 4>; 136 }; 137 }; 138}; 139