1/dts-v1/; 2 3/ { 4 compatible = "cdns,xtensa-xtfpga"; 5 #address-cells = <1>; 6 #size-cells = <1>; 7 interrupt-parent = <&pic>; 8 9 chosen { 10 bootargs = "earlycon=cdns,0xfd000000,115200 console=tty0 console=ttyPS0,115200 root=/dev/ram0 rw earlyprintk xilinx_uartps.rx_trigger_level=32 loglevel=8 nohz=off ignore_loglevel"; 11 }; 12 13 memory@0 { 14 device_type = "memory"; 15 reg = <0x00000000 0x40000000>; 16 }; 17 18 cpus { 19 #address-cells = <1>; 20 #size-cells = <0>; 21 cpu@0 { 22 compatible = "cdns,xtensa-cpu"; 23 reg = <0>; 24 }; 25 }; 26 27 pic: pic { 28 compatible = "cdns,xtensa-pic"; 29 #interrupt-cells = <2>; 30 interrupt-controller; 31 }; 32 33 clocks { 34 osc: main-oscillator { 35 #clock-cells = <0>; 36 compatible = "fixed-clock"; 37 }; 38 }; 39 40 soc { 41 #address-cells = <1>; 42 #size-cells = <1>; 43 compatible = "simple-bus"; 44 ranges = <0x00000000 0xf0000000 0x10000000>; 45 46 uart0: serial@0d000000 { 47 compatible = "xlnx,xuartps", "cdns,uart-r1p8"; 48 clocks = <&osc>, <&osc>; 49 clock-names = "uart_clk", "pclk"; 50 reg = <0x0d000000 0x1000>; 51 interrupts = <0 1>; 52 }; 53 }; 54}; 55