xref: /openbmc/linux/arch/xtensa/Kconfig (revision e1e38ea1)
1# SPDX-License-Identifier: GPL-2.0
2config ZONE_DMA
3	def_bool y
4
5config XTENSA
6	def_bool y
7	select ARCH_HAS_SYNC_DMA_FOR_CPU
8	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
9	select ARCH_NO_COHERENT_DMA_MMAP if !MMU
10	select ARCH_WANT_FRAME_POINTERS
11	select ARCH_WANT_IPC_PARSE_VERSION
12	select BUILDTIME_EXTABLE_SORT
13	select CLONE_BACKWARDS
14	select COMMON_CLK
15	select DMA_NONCOHERENT_OPS
16	select GENERIC_ATOMIC64
17	select GENERIC_CLOCKEVENTS
18	select GENERIC_IRQ_SHOW
19	select GENERIC_PCI_IOMAP
20	select GENERIC_SCHED_CLOCK
21	select GENERIC_STRNCPY_FROM_USER if KASAN
22	select HAVE_ARCH_KASAN if MMU
23	select HAVE_DEBUG_KMEMLEAK
24	select HAVE_DMA_CONTIGUOUS
25	select HAVE_EXIT_THREAD
26	select HAVE_FUNCTION_TRACER
27	select HAVE_FUTEX_CMPXCHG if !MMU
28	select HAVE_HW_BREAKPOINT if PERF_EVENTS
29	select HAVE_IRQ_TIME_ACCOUNTING
30	select HAVE_MEMBLOCK
31	select HAVE_OPROFILE
32	select HAVE_PERF_EVENTS
33	select HAVE_STACKPROTECTOR
34	select IRQ_DOMAIN
35	select MODULES_USE_ELF_RELA
36	select NO_BOOTMEM
37	select PERF_USE_VMALLOC
38	select VIRT_TO_BUS
39	help
40	  Xtensa processors are 32-bit RISC machines designed by Tensilica
41	  primarily for embedded systems.  These processors are both
42	  configurable and extensible.  The Linux port to the Xtensa
43	  architecture supports all processor configurations and extensions,
44	  with reasonable minimum requirements.  The Xtensa Linux project has
45	  a home page at <http://www.linux-xtensa.org/>.
46
47config RWSEM_XCHGADD_ALGORITHM
48	def_bool y
49
50config GENERIC_HWEIGHT
51	def_bool y
52
53config ARCH_HAS_ILOG2_U32
54	def_bool n
55
56config ARCH_HAS_ILOG2_U64
57	def_bool n
58
59config NO_IOPORT_MAP
60	def_bool n
61
62config HZ
63	int
64	default 100
65
66config LOCKDEP_SUPPORT
67	def_bool y
68
69config STACKTRACE_SUPPORT
70	def_bool y
71
72config TRACE_IRQFLAGS_SUPPORT
73	def_bool y
74
75config MMU
76	def_bool n
77
78config HAVE_XTENSA_GPIO32
79	def_bool n
80
81config KASAN_SHADOW_OFFSET
82	hex
83	default 0x6e400000
84
85menu "Processor type and features"
86
87choice
88	prompt "Xtensa Processor Configuration"
89	default XTENSA_VARIANT_FSF
90
91config XTENSA_VARIANT_FSF
92	bool "fsf - default (not generic) configuration"
93	select MMU
94
95config XTENSA_VARIANT_DC232B
96	bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
97	select MMU
98	select HAVE_XTENSA_GPIO32
99	help
100	  This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
101
102config XTENSA_VARIANT_DC233C
103	bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
104	select MMU
105	select HAVE_XTENSA_GPIO32
106	help
107	  This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
108
109config XTENSA_VARIANT_CUSTOM
110	bool "Custom Xtensa processor configuration"
111	select HAVE_XTENSA_GPIO32
112	help
113	  Select this variant to use a custom Xtensa processor configuration.
114	  You will be prompted for a processor variant CORENAME.
115endchoice
116
117config XTENSA_VARIANT_CUSTOM_NAME
118	string "Xtensa Processor Custom Core Variant Name"
119	depends on XTENSA_VARIANT_CUSTOM
120	help
121	  Provide the name of a custom Xtensa processor variant.
122	  This CORENAME selects arch/xtensa/variant/CORENAME.
123	  Dont forget you have to select MMU if you have one.
124
125config XTENSA_VARIANT_NAME
126	string
127	default "dc232b"			if XTENSA_VARIANT_DC232B
128	default "dc233c"			if XTENSA_VARIANT_DC233C
129	default "fsf"				if XTENSA_VARIANT_FSF
130	default XTENSA_VARIANT_CUSTOM_NAME	if XTENSA_VARIANT_CUSTOM
131
132config XTENSA_VARIANT_MMU
133	bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
134	depends on XTENSA_VARIANT_CUSTOM
135	default y
136	select MMU
137	help
138	  Build a Conventional Kernel with full MMU support,
139	  ie: it supports a TLB with auto-loading, page protection.
140
141config XTENSA_VARIANT_HAVE_PERF_EVENTS
142	bool "Core variant has Performance Monitor Module"
143	depends on XTENSA_VARIANT_CUSTOM
144	default n
145	help
146	  Enable if core variant has Performance Monitor Module with
147	  External Registers Interface.
148
149	  If unsure, say N.
150
151config XTENSA_FAKE_NMI
152	bool "Treat PMM IRQ as NMI"
153	depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
154	default n
155	help
156	  If PMM IRQ is the only IRQ at EXCM level it is safe to
157	  treat it as NMI, which improves accuracy of profiling.
158
159	  If there are other interrupts at or above PMM IRQ priority level
160	  but not above the EXCM level, PMM IRQ still may be treated as NMI,
161	  but only if these IRQs are not used. There will be a build warning
162	  saying that this is not safe, and a bugcheck if one of these IRQs
163	  actually fire.
164
165	  If unsure, say N.
166
167config XTENSA_UNALIGNED_USER
168	bool "Unaligned memory access in use space"
169	help
170	  The Xtensa architecture currently does not handle unaligned
171	  memory accesses in hardware but through an exception handler.
172	  Per default, unaligned memory accesses are disabled in user space.
173
174	  Say Y here to enable unaligned memory access in user space.
175
176config HAVE_SMP
177	bool "System Supports SMP (MX)"
178	depends on XTENSA_VARIANT_CUSTOM
179	select XTENSA_MX
180	help
181	  This option is use to indicate that the system-on-a-chip (SOC)
182	  supports Multiprocessing. Multiprocessor support implemented above
183	  the CPU core definition and currently needs to be selected manually.
184
185	  Multiprocessor support in implemented with external cache and
186	  interrupt controllers.
187
188	  The MX interrupt distributer adds Interprocessor Interrupts
189	  and causes the IRQ numbers to be increased by 4 for devices
190	  like the open cores ethernet driver and the serial interface.
191
192	  You still have to select "Enable SMP" to enable SMP on this SOC.
193
194config SMP
195	bool "Enable Symmetric multi-processing support"
196	depends on HAVE_SMP
197	select GENERIC_SMP_IDLE_THREAD
198	help
199	  Enabled SMP Software; allows more than one CPU/CORE
200	  to be activated during startup.
201
202config NR_CPUS
203	depends on SMP
204	int "Maximum number of CPUs (2-32)"
205	range 2 32
206	default "4"
207
208config HOTPLUG_CPU
209	bool "Enable CPU hotplug support"
210	depends on SMP
211	help
212	  Say Y here to allow turning CPUs off and on. CPUs can be
213	  controlled through /sys/devices/system/cpu.
214
215	  Say N if you want to disable CPU hotplug.
216
217config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
218	bool "Initialize Xtensa MMU inside the Linux kernel code"
219	depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
220	default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
221	help
222	  Earlier version initialized the MMU in the exception vector
223	  before jumping to _startup in head.S and had an advantage that
224	  it was possible to place a software breakpoint at 'reset' and
225	  then enter your normal kernel breakpoints once the MMU was mapped
226	  to the kernel mappings (0XC0000000).
227
228	  This unfortunately won't work for U-Boot and likely also wont
229	  work for using KEXEC to have a hot kernel ready for doing a
230	  KDUMP.
231
232	  So now the MMU is initialized in head.S but it's necessary to
233	  use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
234	  xt-gdb can't place a Software Breakpoint in the  0XD region prior
235	  to mapping the MMU and after mapping even if the area of low memory
236	  was mapped gdb wouldn't remove the breakpoint on hitting it as the
237	  PC wouldn't match. Since Hardware Breakpoints are recommended for
238	  Linux configurations it seems reasonable to just assume they exist
239	  and leave this older mechanism for unfortunate souls that choose
240	  not to follow Tensilica's recommendation.
241
242	  Selecting this will cause U-Boot to set the KERNEL Load and Entry
243	  address at 0x00003000 instead of the mapped std of 0xD0003000.
244
245	  If in doubt, say Y.
246
247config MEMMAP_CACHEATTR
248	hex "Cache attributes for the memory address space"
249	depends on !MMU
250	default 0x22222222
251	help
252	  These cache attributes are set up for noMMU systems. Each hex digit
253	  specifies cache attributes for the corresponding 512MB memory
254	  region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
255	  bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
256
257	  Cache attribute values are specific for the MMU type, so e.g.
258	  for region protection MMUs: 2 is cache bypass, 4 is WB cached,
259	  1 is WT cached, f is illegal. For ful MMU: bit 0 makes it executable,
260	  bit 1 makes it writable, bits 2..3 meaning is 0: cache bypass,
261	  1: WB cache, 2: WT cache, 3: special (c and e are illegal, f is
262	  reserved).
263
264config KSEG_PADDR
265	hex "Physical address of the KSEG mapping"
266	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
267	default 0x00000000
268	help
269	  This is the physical address where KSEG is mapped. Please refer to
270	  the chosen KSEG layout help for the required address alignment.
271	  Unpacked kernel image (including vectors) must be located completely
272	  within KSEG.
273	  Physical memory below this address is not available to linux.
274
275	  If unsure, leave the default value here.
276
277config KERNEL_LOAD_ADDRESS
278	hex "Kernel load address"
279	default 0x60003000 if !MMU
280	default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
281	default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
282	help
283	  This is the address where the kernel is loaded.
284	  It is virtual address for MMUv2 configurations and physical address
285	  for all other configurations.
286
287	  If unsure, leave the default value here.
288
289config VECTORS_OFFSET
290	hex "Kernel vectors offset"
291	default 0x00003000
292	help
293	  This is the offset of the kernel image from the relocatable vectors
294	  base.
295
296	  If unsure, leave the default value here.
297
298choice
299	prompt "KSEG layout"
300	depends on MMU
301	default XTENSA_KSEG_MMU_V2
302
303config XTENSA_KSEG_MMU_V2
304	bool "MMUv2: 128MB cached + 128MB uncached"
305	help
306	  MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
307	  at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
308	  without cache.
309	  KSEG_PADDR must be aligned to 128MB.
310
311config XTENSA_KSEG_256M
312	bool "256MB cached + 256MB uncached"
313	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
314	help
315	  TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
316	  with cache and to 0xc0000000 without cache.
317	  KSEG_PADDR must be aligned to 256MB.
318
319config XTENSA_KSEG_512M
320	bool "512MB cached + 512MB uncached"
321	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
322	help
323	  TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
324	  with cache and to 0xc0000000 without cache.
325	  KSEG_PADDR must be aligned to 256MB.
326
327endchoice
328
329config HIGHMEM
330	bool "High Memory Support"
331	depends on MMU
332	help
333	  Linux can use the full amount of RAM in the system by
334	  default. However, the default MMUv2 setup only maps the
335	  lowermost 128 MB of memory linearly to the areas starting
336	  at 0xd0000000 (cached) and 0xd8000000 (uncached).
337	  When there are more than 128 MB memory in the system not
338	  all of it can be "permanently mapped" by the kernel.
339	  The physical memory that's not permanently mapped is called
340	  "high memory".
341
342	  If you are compiling a kernel which will never run on a
343	  machine with more than 128 MB total physical RAM, answer
344	  N here.
345
346	  If unsure, say Y.
347
348config FAST_SYSCALL_XTENSA
349	bool "Enable fast atomic syscalls"
350	default n
351	help
352	  fast_syscall_xtensa is a syscall that can make atomic operations
353	  on UP kernel when processor has no s32c1i support.
354
355	  This syscall is deprecated. It may have issues when called with
356	  invalid arguments. It is provided only for backwards compatibility.
357	  Only enable it if your userspace software requires it.
358
359	  If unsure, say N.
360
361config FAST_SYSCALL_SPILL_REGISTERS
362	bool "Enable spill registers syscall"
363	default n
364	help
365	  fast_syscall_spill_registers is a syscall that spills all active
366	  register windows of a calling userspace task onto its stack.
367
368	  This syscall is deprecated. It may have issues when called with
369	  invalid arguments. It is provided only for backwards compatibility.
370	  Only enable it if your userspace software requires it.
371
372	  If unsure, say N.
373
374endmenu
375
376config XTENSA_CALIBRATE_CCOUNT
377	def_bool n
378	help
379	  On some platforms (XT2000, for example), the CPU clock rate can
380	  vary.  The frequency can be determined, however, by measuring
381	  against a well known, fixed frequency, such as an UART oscillator.
382
383config SERIAL_CONSOLE
384	def_bool n
385
386menu "Bus options"
387
388config PCI
389	bool "PCI support"
390	default y
391	help
392	  Find out whether you have a PCI motherboard. PCI is the name of a
393	  bus system, i.e. the way the CPU talks to the other stuff inside
394	  your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
395	  VESA. If you have PCI, say Y, otherwise N.
396
397source "drivers/pci/Kconfig"
398
399endmenu
400
401menu "Platform options"
402
403choice
404	prompt "Xtensa System Type"
405	default XTENSA_PLATFORM_ISS
406
407config XTENSA_PLATFORM_ISS
408	bool "ISS"
409	select XTENSA_CALIBRATE_CCOUNT
410	select SERIAL_CONSOLE
411	help
412	  ISS is an acronym for Tensilica's Instruction Set Simulator.
413
414config XTENSA_PLATFORM_XT2000
415	bool "XT2000"
416	select HAVE_IDE
417	help
418	  XT2000 is the name of Tensilica's feature-rich emulation platform.
419	  This hardware is capable of running a full Linux distribution.
420
421config XTENSA_PLATFORM_XTFPGA
422	bool "XTFPGA"
423	select ETHOC if ETHERNET
424	select PLATFORM_WANT_DEFAULT_MEM if !MMU
425	select SERIAL_CONSOLE
426	select XTENSA_CALIBRATE_CCOUNT
427	help
428	  XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
429	  This hardware is capable of running a full Linux distribution.
430
431endchoice
432
433config PLATFORM_NR_IRQS
434	int
435	default 3 if XTENSA_PLATFORM_XT2000
436	default 0
437
438config XTENSA_CPU_CLOCK
439	int "CPU clock rate [MHz]"
440	depends on !XTENSA_CALIBRATE_CCOUNT
441	default 16
442
443config GENERIC_CALIBRATE_DELAY
444	bool "Auto calibration of the BogoMIPS value"
445	help
446	  The BogoMIPS value can easily be derived from the CPU frequency.
447
448config CMDLINE_BOOL
449	bool "Default bootloader kernel arguments"
450
451config CMDLINE
452	string "Initial kernel command string"
453	depends on CMDLINE_BOOL
454	default "console=ttyS0,38400 root=/dev/ram"
455	help
456	  On some architectures (EBSA110 and CATS), there is currently no way
457	  for the boot loader to pass arguments to the kernel. For these
458	  architectures, you should supply some command-line options at build
459	  time by entering them here. As a minimum, you should specify the
460	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
461
462config USE_OF
463	bool "Flattened Device Tree support"
464	select OF
465	select OF_EARLY_FLATTREE
466	select OF_RESERVED_MEM
467	help
468	  Include support for flattened device tree machine descriptions.
469
470config BUILTIN_DTB
471	string "DTB to build into the kernel image"
472	depends on OF
473
474config PARSE_BOOTPARAM
475	bool "Parse bootparam block"
476	default y
477	help
478	  Parse parameters passed to the kernel from the bootloader. It may
479	  be disabled if the kernel is known to run without the bootloader.
480
481	  If unsure, say Y.
482
483config BLK_DEV_SIMDISK
484	tristate "Host file-based simulated block device support"
485	default n
486	depends on XTENSA_PLATFORM_ISS && BLOCK
487	help
488	  Create block devices that map to files in the host file system.
489	  Device binding to host file may be changed at runtime via proc
490	  interface provided the device is not in use.
491
492config BLK_DEV_SIMDISK_COUNT
493	int "Number of host file-based simulated block devices"
494	range 1 10
495	depends on BLK_DEV_SIMDISK
496	default 2
497	help
498	  This is the default minimal number of created block devices.
499	  Kernel/module parameter 'simdisk_count' may be used to change this
500	  value at runtime. More file names (but no more than 10) may be
501	  specified as parameters, simdisk_count grows accordingly.
502
503config SIMDISK0_FILENAME
504	string "Host filename for the first simulated device"
505	depends on BLK_DEV_SIMDISK = y
506	default ""
507	help
508	  Attach a first simdisk to a host file. Conventionally, this file
509	  contains a root file system.
510
511config SIMDISK1_FILENAME
512	string "Host filename for the second simulated device"
513	depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
514	default ""
515	help
516	  Another simulated disk in a host file for a buildroot-independent
517	  storage.
518
519config FORCE_MAX_ZONEORDER
520	int "Maximum zone order"
521	default "11"
522	help
523	  The kernel memory allocator divides physically contiguous memory
524	  blocks into "zones", where each zone is a power of two number of
525	  pages.  This option selects the largest power of two that the kernel
526	  keeps in the memory allocator.  If you need to allocate very large
527	  blocks of physically contiguous memory, then you may need to
528	  increase this value.
529
530	  This config option is actually maximum order plus one. For example,
531	  a value of 11 means that the largest free memory block is 2^10 pages.
532
533source "drivers/pcmcia/Kconfig"
534
535config PLATFORM_WANT_DEFAULT_MEM
536	def_bool n
537
538config DEFAULT_MEM_START
539	hex
540	prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
541	default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
542	default 0x00000000
543	help
544	  This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
545	  in noMMU configurations.
546
547	  If unsure, leave the default value here.
548
549config XTFPGA_LCD
550	bool "Enable XTFPGA LCD driver"
551	depends on XTENSA_PLATFORM_XTFPGA
552	default n
553	help
554	  There's a 2x16 LCD on most of XTFPGA boards, kernel may output
555	  progress messages there during bootup/shutdown. It may be useful
556	  during board bringup.
557
558	  If unsure, say N.
559
560config XTFPGA_LCD_BASE_ADDR
561	hex "XTFPGA LCD base address"
562	depends on XTFPGA_LCD
563	default "0x0d0c0000"
564	help
565	  Base address of the LCD controller inside KIO region.
566	  Different boards from XTFPGA family have LCD controller at different
567	  addresses. Please consult prototyping user guide for your board for
568	  the correct address. Wrong address here may lead to hardware lockup.
569
570config XTFPGA_LCD_8BIT_ACCESS
571	bool "Use 8-bit access to XTFPGA LCD"
572	depends on XTFPGA_LCD
573	default n
574	help
575	  LCD may be connected with 4- or 8-bit interface, 8-bit access may
576	  only be used with 8-bit interface. Please consult prototyping user
577	  guide for your board for the correct interface width.
578
579endmenu
580
581menu "Power management options"
582
583source "kernel/power/Kconfig"
584
585endmenu
586