1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/memblock.h> 27 #include <linux/export.h> 28 #include <linux/mm.h> 29 #include <linux/page-flags.h> 30 #include <linux/pci.h> 31 #include <linux/gfp.h> 32 #include <linux/edd.h> 33 #include <linux/reboot.h> 34 #include <linux/virtio_anchor.h> 35 36 #include <xen/xen.h> 37 #include <xen/events.h> 38 #include <xen/interface/xen.h> 39 #include <xen/interface/version.h> 40 #include <xen/interface/physdev.h> 41 #include <xen/interface/vcpu.h> 42 #include <xen/interface/memory.h> 43 #include <xen/interface/nmi.h> 44 #include <xen/interface/xen-mca.h> 45 #include <xen/features.h> 46 #include <xen/page.h> 47 #include <xen/hvc-console.h> 48 #include <xen/acpi.h> 49 50 #include <asm/paravirt.h> 51 #include <asm/apic.h> 52 #include <asm/page.h> 53 #include <asm/xen/pci.h> 54 #include <asm/xen/hypercall.h> 55 #include <asm/xen/hypervisor.h> 56 #include <asm/xen/cpuid.h> 57 #include <asm/fixmap.h> 58 #include <asm/processor.h> 59 #include <asm/proto.h> 60 #include <asm/msr-index.h> 61 #include <asm/traps.h> 62 #include <asm/setup.h> 63 #include <asm/desc.h> 64 #include <asm/pgalloc.h> 65 #include <asm/tlbflush.h> 66 #include <asm/reboot.h> 67 #include <asm/stackprotector.h> 68 #include <asm/hypervisor.h> 69 #include <asm/mach_traps.h> 70 #include <asm/mwait.h> 71 #include <asm/pci_x86.h> 72 #include <asm/cpu.h> 73 #ifdef CONFIG_X86_IOPL_IOPERM 74 #include <asm/io_bitmap.h> 75 #endif 76 77 #ifdef CONFIG_ACPI 78 #include <linux/acpi.h> 79 #include <asm/acpi.h> 80 #include <acpi/pdc_intel.h> 81 #include <acpi/processor.h> 82 #include <xen/interface/platform.h> 83 #endif 84 85 #include "xen-ops.h" 86 #include "mmu.h" 87 #include "smp.h" 88 #include "multicalls.h" 89 #include "pmu.h" 90 91 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 92 93 void *xen_initial_gdt; 94 95 static int xen_cpu_up_prepare_pv(unsigned int cpu); 96 static int xen_cpu_dead_pv(unsigned int cpu); 97 98 struct tls_descs { 99 struct desc_struct desc[3]; 100 }; 101 102 /* 103 * Updating the 3 TLS descriptors in the GDT on every task switch is 104 * surprisingly expensive so we avoid updating them if they haven't 105 * changed. Since Xen writes different descriptors than the one 106 * passed in the update_descriptor hypercall we keep shadow copies to 107 * compare against. 108 */ 109 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 110 111 static void __init xen_pv_init_platform(void) 112 { 113 /* PV guests can't operate virtio devices without grants. */ 114 if (IS_ENABLED(CONFIG_XEN_VIRTIO)) 115 virtio_set_mem_acc_cb(virtio_require_restricted_mem_acc); 116 117 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 118 119 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 120 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 121 122 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 123 xen_vcpu_info_reset(0); 124 125 /* pvclock is in shared info area */ 126 xen_init_time_ops(); 127 } 128 129 static void __init xen_pv_guest_late_init(void) 130 { 131 #ifndef CONFIG_SMP 132 /* Setup shared vcpu info for non-smp configurations */ 133 xen_setup_vcpu_info_placement(); 134 #endif 135 } 136 137 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 138 static __read_mostly unsigned int cpuid_leaf5_edx_val; 139 140 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 141 unsigned int *cx, unsigned int *dx) 142 { 143 unsigned maskebx = ~0; 144 145 /* 146 * Mask out inconvenient features, to try and disable as many 147 * unsupported kernel subsystems as possible. 148 */ 149 switch (*ax) { 150 case CPUID_MWAIT_LEAF: 151 /* Synthesize the values.. */ 152 *ax = 0; 153 *bx = 0; 154 *cx = cpuid_leaf5_ecx_val; 155 *dx = cpuid_leaf5_edx_val; 156 return; 157 158 case 0xb: 159 /* Suppress extended topology stuff */ 160 maskebx = 0; 161 break; 162 } 163 164 asm(XEN_EMULATE_PREFIX "cpuid" 165 : "=a" (*ax), 166 "=b" (*bx), 167 "=c" (*cx), 168 "=d" (*dx) 169 : "0" (*ax), "2" (*cx)); 170 171 *bx &= maskebx; 172 } 173 174 static bool __init xen_check_mwait(void) 175 { 176 #ifdef CONFIG_ACPI 177 struct xen_platform_op op = { 178 .cmd = XENPF_set_processor_pminfo, 179 .u.set_pminfo.id = -1, 180 .u.set_pminfo.type = XEN_PM_PDC, 181 }; 182 uint32_t buf[3]; 183 unsigned int ax, bx, cx, dx; 184 unsigned int mwait_mask; 185 186 /* We need to determine whether it is OK to expose the MWAIT 187 * capability to the kernel to harvest deeper than C3 states from ACPI 188 * _CST using the processor_harvest_xen.c module. For this to work, we 189 * need to gather the MWAIT_LEAF values (which the cstate.c code 190 * checks against). The hypervisor won't expose the MWAIT flag because 191 * it would break backwards compatibility; so we will find out directly 192 * from the hardware and hypercall. 193 */ 194 if (!xen_initial_domain()) 195 return false; 196 197 /* 198 * When running under platform earlier than Xen4.2, do not expose 199 * mwait, to avoid the risk of loading native acpi pad driver 200 */ 201 if (!xen_running_on_version_or_later(4, 2)) 202 return false; 203 204 ax = 1; 205 cx = 0; 206 207 native_cpuid(&ax, &bx, &cx, &dx); 208 209 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 210 (1 << (X86_FEATURE_MWAIT % 32)); 211 212 if ((cx & mwait_mask) != mwait_mask) 213 return false; 214 215 /* We need to emulate the MWAIT_LEAF and for that we need both 216 * ecx and edx. The hypercall provides only partial information. 217 */ 218 219 ax = CPUID_MWAIT_LEAF; 220 bx = 0; 221 cx = 0; 222 dx = 0; 223 224 native_cpuid(&ax, &bx, &cx, &dx); 225 226 /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so, 227 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 228 */ 229 buf[0] = ACPI_PDC_REVISION_ID; 230 buf[1] = 1; 231 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP); 232 233 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 234 235 if ((HYPERVISOR_platform_op(&op) == 0) && 236 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) { 237 cpuid_leaf5_ecx_val = cx; 238 cpuid_leaf5_edx_val = dx; 239 } 240 return true; 241 #else 242 return false; 243 #endif 244 } 245 246 static bool __init xen_check_xsave(void) 247 { 248 unsigned int cx, xsave_mask; 249 250 cx = cpuid_ecx(1); 251 252 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 253 (1 << (X86_FEATURE_OSXSAVE % 32)); 254 255 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 256 return (cx & xsave_mask) == xsave_mask; 257 } 258 259 static void __init xen_init_capabilities(void) 260 { 261 setup_force_cpu_cap(X86_FEATURE_XENPV); 262 setup_clear_cpu_cap(X86_FEATURE_DCA); 263 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 264 setup_clear_cpu_cap(X86_FEATURE_MTRR); 265 setup_clear_cpu_cap(X86_FEATURE_ACC); 266 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 267 setup_clear_cpu_cap(X86_FEATURE_SME); 268 269 /* 270 * Xen PV would need some work to support PCID: CR3 handling as well 271 * as xen_flush_tlb_others() would need updating. 272 */ 273 setup_clear_cpu_cap(X86_FEATURE_PCID); 274 275 if (!xen_initial_domain()) 276 setup_clear_cpu_cap(X86_FEATURE_ACPI); 277 278 if (xen_check_mwait()) 279 setup_force_cpu_cap(X86_FEATURE_MWAIT); 280 else 281 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 282 283 if (!xen_check_xsave()) { 284 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 285 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 286 } 287 } 288 289 static noinstr void xen_set_debugreg(int reg, unsigned long val) 290 { 291 HYPERVISOR_set_debugreg(reg, val); 292 } 293 294 static noinstr unsigned long xen_get_debugreg(int reg) 295 { 296 return HYPERVISOR_get_debugreg(reg); 297 } 298 299 static void xen_end_context_switch(struct task_struct *next) 300 { 301 xen_mc_flush(); 302 paravirt_end_context_switch(next); 303 } 304 305 static unsigned long xen_store_tr(void) 306 { 307 return 0; 308 } 309 310 /* 311 * Set the page permissions for a particular virtual address. If the 312 * address is a vmalloc mapping (or other non-linear mapping), then 313 * find the linear mapping of the page and also set its protections to 314 * match. 315 */ 316 static void set_aliased_prot(void *v, pgprot_t prot) 317 { 318 int level; 319 pte_t *ptep; 320 pte_t pte; 321 unsigned long pfn; 322 unsigned char dummy; 323 void *va; 324 325 ptep = lookup_address((unsigned long)v, &level); 326 BUG_ON(ptep == NULL); 327 328 pfn = pte_pfn(*ptep); 329 pte = pfn_pte(pfn, prot); 330 331 /* 332 * Careful: update_va_mapping() will fail if the virtual address 333 * we're poking isn't populated in the page tables. We don't 334 * need to worry about the direct map (that's always in the page 335 * tables), but we need to be careful about vmap space. In 336 * particular, the top level page table can lazily propagate 337 * entries between processes, so if we've switched mms since we 338 * vmapped the target in the first place, we might not have the 339 * top-level page table entry populated. 340 * 341 * We disable preemption because we want the same mm active when 342 * we probe the target and when we issue the hypercall. We'll 343 * have the same nominal mm, but if we're a kernel thread, lazy 344 * mm dropping could change our pgd. 345 * 346 * Out of an abundance of caution, this uses __get_user() to fault 347 * in the target address just in case there's some obscure case 348 * in which the target address isn't readable. 349 */ 350 351 preempt_disable(); 352 353 copy_from_kernel_nofault(&dummy, v, 1); 354 355 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 356 BUG(); 357 358 va = __va(PFN_PHYS(pfn)); 359 360 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 361 BUG(); 362 363 preempt_enable(); 364 } 365 366 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 367 { 368 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 369 int i; 370 371 /* 372 * We need to mark the all aliases of the LDT pages RO. We 373 * don't need to call vm_flush_aliases(), though, since that's 374 * only responsible for flushing aliases out the TLBs, not the 375 * page tables, and Xen will flush the TLB for us if needed. 376 * 377 * To avoid confusing future readers: none of this is necessary 378 * to load the LDT. The hypervisor only checks this when the 379 * LDT is faulted in due to subsequent descriptor access. 380 */ 381 382 for (i = 0; i < entries; i += entries_per_page) 383 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 384 } 385 386 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 387 { 388 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 389 int i; 390 391 for (i = 0; i < entries; i += entries_per_page) 392 set_aliased_prot(ldt + i, PAGE_KERNEL); 393 } 394 395 static void xen_set_ldt(const void *addr, unsigned entries) 396 { 397 struct mmuext_op *op; 398 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 399 400 trace_xen_cpu_set_ldt(addr, entries); 401 402 op = mcs.args; 403 op->cmd = MMUEXT_SET_LDT; 404 op->arg1.linear_addr = (unsigned long)addr; 405 op->arg2.nr_ents = entries; 406 407 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 408 409 xen_mc_issue(PARAVIRT_LAZY_CPU); 410 } 411 412 static void xen_load_gdt(const struct desc_ptr *dtr) 413 { 414 unsigned long va = dtr->address; 415 unsigned int size = dtr->size + 1; 416 unsigned long pfn, mfn; 417 int level; 418 pte_t *ptep; 419 void *virt; 420 421 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 422 BUG_ON(size > PAGE_SIZE); 423 BUG_ON(va & ~PAGE_MASK); 424 425 /* 426 * The GDT is per-cpu and is in the percpu data area. 427 * That can be virtually mapped, so we need to do a 428 * page-walk to get the underlying MFN for the 429 * hypercall. The page can also be in the kernel's 430 * linear range, so we need to RO that mapping too. 431 */ 432 ptep = lookup_address(va, &level); 433 BUG_ON(ptep == NULL); 434 435 pfn = pte_pfn(*ptep); 436 mfn = pfn_to_mfn(pfn); 437 virt = __va(PFN_PHYS(pfn)); 438 439 make_lowmem_page_readonly((void *)va); 440 make_lowmem_page_readonly(virt); 441 442 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 443 BUG(); 444 } 445 446 /* 447 * load_gdt for early boot, when the gdt is only mapped once 448 */ 449 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 450 { 451 unsigned long va = dtr->address; 452 unsigned int size = dtr->size + 1; 453 unsigned long pfn, mfn; 454 pte_t pte; 455 456 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 457 BUG_ON(size > PAGE_SIZE); 458 BUG_ON(va & ~PAGE_MASK); 459 460 pfn = virt_to_pfn(va); 461 mfn = pfn_to_mfn(pfn); 462 463 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 464 465 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 466 BUG(); 467 468 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 469 BUG(); 470 } 471 472 static inline bool desc_equal(const struct desc_struct *d1, 473 const struct desc_struct *d2) 474 { 475 return !memcmp(d1, d2, sizeof(*d1)); 476 } 477 478 static void load_TLS_descriptor(struct thread_struct *t, 479 unsigned int cpu, unsigned int i) 480 { 481 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 482 struct desc_struct *gdt; 483 xmaddr_t maddr; 484 struct multicall_space mc; 485 486 if (desc_equal(shadow, &t->tls_array[i])) 487 return; 488 489 *shadow = t->tls_array[i]; 490 491 gdt = get_cpu_gdt_rw(cpu); 492 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 493 mc = __xen_mc_entry(0); 494 495 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 496 } 497 498 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 499 { 500 /* 501 * In lazy mode we need to zero %fs, otherwise we may get an 502 * exception between the new %fs descriptor being loaded and 503 * %fs being effectively cleared at __switch_to(). 504 */ 505 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) 506 loadsegment(fs, 0); 507 508 xen_mc_batch(); 509 510 load_TLS_descriptor(t, cpu, 0); 511 load_TLS_descriptor(t, cpu, 1); 512 load_TLS_descriptor(t, cpu, 2); 513 514 xen_mc_issue(PARAVIRT_LAZY_CPU); 515 } 516 517 static void xen_load_gs_index(unsigned int idx) 518 { 519 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 520 BUG(); 521 } 522 523 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 524 const void *ptr) 525 { 526 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 527 u64 entry = *(u64 *)ptr; 528 529 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 530 531 preempt_disable(); 532 533 xen_mc_flush(); 534 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 535 BUG(); 536 537 preempt_enable(); 538 } 539 540 void noist_exc_debug(struct pt_regs *regs); 541 542 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 543 { 544 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 545 exc_nmi(regs); 546 } 547 548 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 549 { 550 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 551 exc_double_fault(regs, error_code); 552 } 553 554 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 555 { 556 /* 557 * There's no IST on Xen PV, but we still need to dispatch 558 * to the correct handler. 559 */ 560 if (user_mode(regs)) 561 noist_exc_debug(regs); 562 else 563 exc_debug(regs); 564 } 565 566 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 567 { 568 /* This should never happen and there is no way to handle it. */ 569 instrumentation_begin(); 570 pr_err("Unknown trap in Xen PV mode."); 571 BUG(); 572 instrumentation_end(); 573 } 574 575 #ifdef CONFIG_X86_MCE 576 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 577 { 578 /* 579 * There's no IST on Xen PV, but we still need to dispatch 580 * to the correct handler. 581 */ 582 if (user_mode(regs)) 583 noist_exc_machine_check(regs); 584 else 585 exc_machine_check(regs); 586 } 587 #endif 588 589 struct trap_array_entry { 590 void (*orig)(void); 591 void (*xen)(void); 592 bool ist_okay; 593 }; 594 595 #define TRAP_ENTRY(func, ist_ok) { \ 596 .orig = asm_##func, \ 597 .xen = xen_asm_##func, \ 598 .ist_okay = ist_ok } 599 600 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 601 .orig = asm_##func, \ 602 .xen = xen_asm_xenpv_##func, \ 603 .ist_okay = ist_ok } 604 605 static struct trap_array_entry trap_array[] = { 606 TRAP_ENTRY_REDIR(exc_debug, true ), 607 TRAP_ENTRY_REDIR(exc_double_fault, true ), 608 #ifdef CONFIG_X86_MCE 609 TRAP_ENTRY_REDIR(exc_machine_check, true ), 610 #endif 611 TRAP_ENTRY_REDIR(exc_nmi, true ), 612 TRAP_ENTRY(exc_int3, false ), 613 TRAP_ENTRY(exc_overflow, false ), 614 #ifdef CONFIG_IA32_EMULATION 615 { entry_INT80_compat, xen_entry_INT80_compat, false }, 616 #endif 617 TRAP_ENTRY(exc_page_fault, false ), 618 TRAP_ENTRY(exc_divide_error, false ), 619 TRAP_ENTRY(exc_bounds, false ), 620 TRAP_ENTRY(exc_invalid_op, false ), 621 TRAP_ENTRY(exc_device_not_available, false ), 622 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 623 TRAP_ENTRY(exc_invalid_tss, false ), 624 TRAP_ENTRY(exc_segment_not_present, false ), 625 TRAP_ENTRY(exc_stack_segment, false ), 626 TRAP_ENTRY(exc_general_protection, false ), 627 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 628 TRAP_ENTRY(exc_coprocessor_error, false ), 629 TRAP_ENTRY(exc_alignment_check, false ), 630 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 631 #ifdef CONFIG_X86_KERNEL_IBT 632 TRAP_ENTRY(exc_control_protection, false ), 633 #endif 634 }; 635 636 static bool __ref get_trap_addr(void **addr, unsigned int ist) 637 { 638 unsigned int nr; 639 bool ist_okay = false; 640 bool found = false; 641 642 /* 643 * Replace trap handler addresses by Xen specific ones. 644 * Check for known traps using IST and whitelist them. 645 * The debugger ones are the only ones we care about. 646 * Xen will handle faults like double_fault, so we should never see 647 * them. Warn if there's an unexpected IST-using fault handler. 648 */ 649 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 650 struct trap_array_entry *entry = trap_array + nr; 651 652 if (*addr == entry->orig) { 653 *addr = entry->xen; 654 ist_okay = entry->ist_okay; 655 found = true; 656 break; 657 } 658 } 659 660 if (nr == ARRAY_SIZE(trap_array) && 661 *addr >= (void *)early_idt_handler_array[0] && 662 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 663 nr = (*addr - (void *)early_idt_handler_array[0]) / 664 EARLY_IDT_HANDLER_SIZE; 665 *addr = (void *)xen_early_idt_handler_array[nr]; 666 found = true; 667 } 668 669 if (!found) 670 *addr = (void *)xen_asm_exc_xen_unknown_trap; 671 672 if (WARN_ON(found && ist != 0 && !ist_okay)) 673 return false; 674 675 return true; 676 } 677 678 static int cvt_gate_to_trap(int vector, const gate_desc *val, 679 struct trap_info *info) 680 { 681 unsigned long addr; 682 683 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 684 return 0; 685 686 info->vector = vector; 687 688 addr = gate_offset(val); 689 if (!get_trap_addr((void **)&addr, val->bits.ist)) 690 return 0; 691 info->address = addr; 692 693 info->cs = gate_segment(val); 694 info->flags = val->bits.dpl; 695 /* interrupt gates clear IF */ 696 if (val->bits.type == GATE_INTERRUPT) 697 info->flags |= 1 << 2; 698 699 return 1; 700 } 701 702 /* Locations of each CPU's IDT */ 703 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 704 705 /* Set an IDT entry. If the entry is part of the current IDT, then 706 also update Xen. */ 707 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 708 { 709 unsigned long p = (unsigned long)&dt[entrynum]; 710 unsigned long start, end; 711 712 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 713 714 preempt_disable(); 715 716 start = __this_cpu_read(idt_desc.address); 717 end = start + __this_cpu_read(idt_desc.size) + 1; 718 719 xen_mc_flush(); 720 721 native_write_idt_entry(dt, entrynum, g); 722 723 if (p >= start && (p + 8) <= end) { 724 struct trap_info info[2]; 725 726 info[1].address = 0; 727 728 if (cvt_gate_to_trap(entrynum, g, &info[0])) 729 if (HYPERVISOR_set_trap_table(info)) 730 BUG(); 731 } 732 733 preempt_enable(); 734 } 735 736 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 737 struct trap_info *traps, bool full) 738 { 739 unsigned in, out, count; 740 741 count = (desc->size+1) / sizeof(gate_desc); 742 BUG_ON(count > 256); 743 744 for (in = out = 0; in < count; in++) { 745 gate_desc *entry = (gate_desc *)(desc->address) + in; 746 747 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 748 out++; 749 } 750 751 return out; 752 } 753 754 void xen_copy_trap_info(struct trap_info *traps) 755 { 756 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 757 758 xen_convert_trap_info(desc, traps, true); 759 } 760 761 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 762 hold a spinlock to protect the static traps[] array (static because 763 it avoids allocation, and saves stack space). */ 764 static void xen_load_idt(const struct desc_ptr *desc) 765 { 766 static DEFINE_SPINLOCK(lock); 767 static struct trap_info traps[257]; 768 unsigned out; 769 770 trace_xen_cpu_load_idt(desc); 771 772 spin_lock(&lock); 773 774 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 775 776 out = xen_convert_trap_info(desc, traps, false); 777 memset(&traps[out], 0, sizeof(traps[0])); 778 779 xen_mc_flush(); 780 if (HYPERVISOR_set_trap_table(traps)) 781 BUG(); 782 783 spin_unlock(&lock); 784 } 785 786 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 787 they're handled differently. */ 788 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 789 const void *desc, int type) 790 { 791 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 792 793 preempt_disable(); 794 795 switch (type) { 796 case DESC_LDT: 797 case DESC_TSS: 798 /* ignore */ 799 break; 800 801 default: { 802 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 803 804 xen_mc_flush(); 805 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 806 BUG(); 807 } 808 809 } 810 811 preempt_enable(); 812 } 813 814 /* 815 * Version of write_gdt_entry for use at early boot-time needed to 816 * update an entry as simply as possible. 817 */ 818 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 819 const void *desc, int type) 820 { 821 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 822 823 switch (type) { 824 case DESC_LDT: 825 case DESC_TSS: 826 /* ignore */ 827 break; 828 829 default: { 830 xmaddr_t maddr = virt_to_machine(&dt[entry]); 831 832 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 833 dt[entry] = *(struct desc_struct *)desc; 834 } 835 836 } 837 } 838 839 static void xen_load_sp0(unsigned long sp0) 840 { 841 struct multicall_space mcs; 842 843 mcs = xen_mc_entry(0); 844 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 845 xen_mc_issue(PARAVIRT_LAZY_CPU); 846 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 847 } 848 849 #ifdef CONFIG_X86_IOPL_IOPERM 850 static void xen_invalidate_io_bitmap(void) 851 { 852 struct physdev_set_iobitmap iobitmap = { 853 .bitmap = NULL, 854 .nr_ports = 0, 855 }; 856 857 native_tss_invalidate_io_bitmap(); 858 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 859 } 860 861 static void xen_update_io_bitmap(void) 862 { 863 struct physdev_set_iobitmap iobitmap; 864 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 865 866 native_tss_update_io_bitmap(); 867 868 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 869 tss->x86_tss.io_bitmap_base; 870 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 871 iobitmap.nr_ports = 0; 872 else 873 iobitmap.nr_ports = IO_BITMAP_BITS; 874 875 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 876 } 877 #endif 878 879 static void xen_io_delay(void) 880 { 881 } 882 883 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 884 885 static unsigned long xen_read_cr0(void) 886 { 887 unsigned long cr0 = this_cpu_read(xen_cr0_value); 888 889 if (unlikely(cr0 == 0)) { 890 cr0 = native_read_cr0(); 891 this_cpu_write(xen_cr0_value, cr0); 892 } 893 894 return cr0; 895 } 896 897 static void xen_write_cr0(unsigned long cr0) 898 { 899 struct multicall_space mcs; 900 901 this_cpu_write(xen_cr0_value, cr0); 902 903 /* Only pay attention to cr0.TS; everything else is 904 ignored. */ 905 mcs = xen_mc_entry(0); 906 907 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 908 909 xen_mc_issue(PARAVIRT_LAZY_CPU); 910 } 911 912 static void xen_write_cr4(unsigned long cr4) 913 { 914 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 915 916 native_write_cr4(cr4); 917 } 918 919 static u64 xen_read_msr_safe(unsigned int msr, int *err) 920 { 921 u64 val; 922 923 if (pmu_msr_read(msr, &val, err)) 924 return val; 925 926 val = native_read_msr_safe(msr, err); 927 switch (msr) { 928 case MSR_IA32_APICBASE: 929 val &= ~X2APIC_ENABLE; 930 break; 931 } 932 return val; 933 } 934 935 static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) 936 { 937 int ret; 938 unsigned int which; 939 u64 base; 940 941 ret = 0; 942 943 switch (msr) { 944 case MSR_FS_BASE: which = SEGBASE_FS; goto set; 945 case MSR_KERNEL_GS_BASE: which = SEGBASE_GS_USER; goto set; 946 case MSR_GS_BASE: which = SEGBASE_GS_KERNEL; goto set; 947 948 set: 949 base = ((u64)high << 32) | low; 950 if (HYPERVISOR_set_segment_base(which, base) != 0) 951 ret = -EIO; 952 break; 953 954 case MSR_STAR: 955 case MSR_CSTAR: 956 case MSR_LSTAR: 957 case MSR_SYSCALL_MASK: 958 case MSR_IA32_SYSENTER_CS: 959 case MSR_IA32_SYSENTER_ESP: 960 case MSR_IA32_SYSENTER_EIP: 961 /* Fast syscall setup is all done in hypercalls, so 962 these are all ignored. Stub them out here to stop 963 Xen console noise. */ 964 break; 965 966 default: 967 if (!pmu_msr_write(msr, low, high, &ret)) 968 ret = native_write_msr_safe(msr, low, high); 969 } 970 971 return ret; 972 } 973 974 static u64 xen_read_msr(unsigned int msr) 975 { 976 /* 977 * This will silently swallow a #GP from RDMSR. It may be worth 978 * changing that. 979 */ 980 int err; 981 982 return xen_read_msr_safe(msr, &err); 983 } 984 985 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 986 { 987 /* 988 * This will silently swallow a #GP from WRMSR. It may be worth 989 * changing that. 990 */ 991 xen_write_msr_safe(msr, low, high); 992 } 993 994 /* This is called once we have the cpu_possible_mask */ 995 void __init xen_setup_vcpu_info_placement(void) 996 { 997 int cpu; 998 999 for_each_possible_cpu(cpu) { 1000 /* Set up direct vCPU id mapping for PV guests. */ 1001 per_cpu(xen_vcpu_id, cpu) = cpu; 1002 xen_vcpu_setup(cpu); 1003 } 1004 1005 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1006 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1007 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1008 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1009 } 1010 1011 static const struct pv_info xen_info __initconst = { 1012 .extra_user_64bit_cs = FLAT_USER_CS64, 1013 .name = "Xen", 1014 }; 1015 1016 static const typeof(pv_ops) xen_cpu_ops __initconst = { 1017 .cpu = { 1018 .cpuid = xen_cpuid, 1019 1020 .set_debugreg = xen_set_debugreg, 1021 .get_debugreg = xen_get_debugreg, 1022 1023 .read_cr0 = xen_read_cr0, 1024 .write_cr0 = xen_write_cr0, 1025 1026 .write_cr4 = xen_write_cr4, 1027 1028 .wbinvd = native_wbinvd, 1029 1030 .read_msr = xen_read_msr, 1031 .write_msr = xen_write_msr, 1032 1033 .read_msr_safe = xen_read_msr_safe, 1034 .write_msr_safe = xen_write_msr_safe, 1035 1036 .read_pmc = xen_read_pmc, 1037 1038 .load_tr_desc = paravirt_nop, 1039 .set_ldt = xen_set_ldt, 1040 .load_gdt = xen_load_gdt, 1041 .load_idt = xen_load_idt, 1042 .load_tls = xen_load_tls, 1043 .load_gs_index = xen_load_gs_index, 1044 1045 .alloc_ldt = xen_alloc_ldt, 1046 .free_ldt = xen_free_ldt, 1047 1048 .store_tr = xen_store_tr, 1049 1050 .write_ldt_entry = xen_write_ldt_entry, 1051 .write_gdt_entry = xen_write_gdt_entry, 1052 .write_idt_entry = xen_write_idt_entry, 1053 .load_sp0 = xen_load_sp0, 1054 1055 #ifdef CONFIG_X86_IOPL_IOPERM 1056 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1057 .update_io_bitmap = xen_update_io_bitmap, 1058 #endif 1059 .io_delay = xen_io_delay, 1060 1061 .start_context_switch = paravirt_start_context_switch, 1062 .end_context_switch = xen_end_context_switch, 1063 }, 1064 }; 1065 1066 static void xen_restart(char *msg) 1067 { 1068 xen_reboot(SHUTDOWN_reboot); 1069 } 1070 1071 static void xen_machine_halt(void) 1072 { 1073 xen_reboot(SHUTDOWN_poweroff); 1074 } 1075 1076 static void xen_machine_power_off(void) 1077 { 1078 do_kernel_power_off(); 1079 xen_reboot(SHUTDOWN_poweroff); 1080 } 1081 1082 static void xen_crash_shutdown(struct pt_regs *regs) 1083 { 1084 xen_reboot(SHUTDOWN_crash); 1085 } 1086 1087 static const struct machine_ops xen_machine_ops __initconst = { 1088 .restart = xen_restart, 1089 .halt = xen_machine_halt, 1090 .power_off = xen_machine_power_off, 1091 .shutdown = xen_machine_halt, 1092 .crash_shutdown = xen_crash_shutdown, 1093 .emergency_restart = xen_emergency_restart, 1094 }; 1095 1096 static unsigned char xen_get_nmi_reason(void) 1097 { 1098 unsigned char reason = 0; 1099 1100 /* Construct a value which looks like it came from port 0x61. */ 1101 if (test_bit(_XEN_NMIREASON_io_error, 1102 &HYPERVISOR_shared_info->arch.nmi_reason)) 1103 reason |= NMI_REASON_IOCHK; 1104 if (test_bit(_XEN_NMIREASON_pci_serr, 1105 &HYPERVISOR_shared_info->arch.nmi_reason)) 1106 reason |= NMI_REASON_SERR; 1107 1108 return reason; 1109 } 1110 1111 static void __init xen_boot_params_init_edd(void) 1112 { 1113 #if IS_ENABLED(CONFIG_EDD) 1114 struct xen_platform_op op; 1115 struct edd_info *edd_info; 1116 u32 *mbr_signature; 1117 unsigned nr; 1118 int ret; 1119 1120 edd_info = boot_params.eddbuf; 1121 mbr_signature = boot_params.edd_mbr_sig_buffer; 1122 1123 op.cmd = XENPF_firmware_info; 1124 1125 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1126 for (nr = 0; nr < EDDMAXNR; nr++) { 1127 struct edd_info *info = edd_info + nr; 1128 1129 op.u.firmware_info.index = nr; 1130 info->params.length = sizeof(info->params); 1131 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1132 &info->params); 1133 ret = HYPERVISOR_platform_op(&op); 1134 if (ret) 1135 break; 1136 1137 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1138 C(device); 1139 C(version); 1140 C(interface_support); 1141 C(legacy_max_cylinder); 1142 C(legacy_max_head); 1143 C(legacy_sectors_per_track); 1144 #undef C 1145 } 1146 boot_params.eddbuf_entries = nr; 1147 1148 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1149 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1150 op.u.firmware_info.index = nr; 1151 ret = HYPERVISOR_platform_op(&op); 1152 if (ret) 1153 break; 1154 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1155 } 1156 boot_params.edd_mbr_sig_buf_entries = nr; 1157 #endif 1158 } 1159 1160 /* 1161 * Set up the GDT and segment registers for -fstack-protector. Until 1162 * we do this, we have to be careful not to call any stack-protected 1163 * function, which is most of the kernel. 1164 */ 1165 static void __init xen_setup_gdt(int cpu) 1166 { 1167 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1168 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1169 1170 switch_to_new_gdt(cpu); 1171 1172 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1173 pv_ops.cpu.load_gdt = xen_load_gdt; 1174 } 1175 1176 static void __init xen_dom0_set_legacy_features(void) 1177 { 1178 x86_platform.legacy.rtc = 1; 1179 } 1180 1181 static void __init xen_domu_set_legacy_features(void) 1182 { 1183 x86_platform.legacy.rtc = 0; 1184 } 1185 1186 extern void early_xen_iret_patch(void); 1187 1188 /* First C function to be called on Xen boot */ 1189 asmlinkage __visible void __init xen_start_kernel(struct start_info *si) 1190 { 1191 struct physdev_set_iopl set_iopl; 1192 unsigned long initrd_start = 0; 1193 int rc; 1194 1195 if (!si) 1196 return; 1197 1198 clear_bss(); 1199 1200 xen_start_info = si; 1201 1202 __text_gen_insn(&early_xen_iret_patch, 1203 JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, 1204 JMP32_INSN_SIZE); 1205 1206 xen_domain_type = XEN_PV_DOMAIN; 1207 xen_start_flags = xen_start_info->flags; 1208 1209 xen_setup_features(); 1210 1211 /* Install Xen paravirt ops */ 1212 pv_info = xen_info; 1213 pv_ops.cpu = xen_cpu_ops.cpu; 1214 xen_init_irq_ops(); 1215 1216 /* 1217 * Setup xen_vcpu early because it is needed for 1218 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1219 * 1220 * Don't do the full vcpu_info placement stuff until we have 1221 * the cpu_possible_mask and a non-dummy shared_info. 1222 */ 1223 xen_vcpu_info_reset(0); 1224 1225 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1226 1227 x86_init.resources.memory_setup = xen_memory_setup; 1228 x86_init.irqs.intr_mode_select = x86_init_noop; 1229 x86_init.irqs.intr_mode_init = x86_init_noop; 1230 x86_init.oem.arch_setup = xen_arch_setup; 1231 x86_init.oem.banner = xen_banner; 1232 x86_init.hyper.init_platform = xen_pv_init_platform; 1233 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1234 1235 /* 1236 * Set up some pagetable state before starting to set any ptes. 1237 */ 1238 1239 xen_setup_machphys_mapping(); 1240 xen_init_mmu_ops(); 1241 1242 /* Prevent unwanted bits from being set in PTEs. */ 1243 __supported_pte_mask &= ~_PAGE_GLOBAL; 1244 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1245 1246 /* Get mfn list */ 1247 xen_build_dynamic_phys_to_machine(); 1248 1249 /* Work out if we support NX */ 1250 get_cpu_cap(&boot_cpu_data); 1251 x86_configure_nx(); 1252 1253 /* 1254 * Set up kernel GDT and segment registers, mainly so that 1255 * -fstack-protector code can be executed. 1256 */ 1257 xen_setup_gdt(0); 1258 1259 /* Determine virtual and physical address sizes */ 1260 get_cpu_address_sizes(&boot_cpu_data); 1261 1262 /* Let's presume PV guests always boot on vCPU with id 0. */ 1263 per_cpu(xen_vcpu_id, 0) = 0; 1264 1265 idt_setup_early_handler(); 1266 1267 xen_init_capabilities(); 1268 1269 #ifdef CONFIG_X86_LOCAL_APIC 1270 /* 1271 * set up the basic apic ops. 1272 */ 1273 xen_init_apic(); 1274 #endif 1275 1276 machine_ops = xen_machine_ops; 1277 1278 /* 1279 * The only reliable way to retain the initial address of the 1280 * percpu gdt_page is to remember it here, so we can go and 1281 * mark it RW later, when the initial percpu area is freed. 1282 */ 1283 xen_initial_gdt = &per_cpu(gdt_page, 0); 1284 1285 xen_smp_init(); 1286 1287 #ifdef CONFIG_ACPI_NUMA 1288 /* 1289 * The pages we from Xen are not related to machine pages, so 1290 * any NUMA information the kernel tries to get from ACPI will 1291 * be meaningless. Prevent it from trying. 1292 */ 1293 disable_srat(); 1294 #endif 1295 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1296 1297 local_irq_disable(); 1298 early_boot_irqs_disabled = true; 1299 1300 xen_raw_console_write("mapping kernel into physical memory\n"); 1301 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1302 xen_start_info->nr_pages); 1303 xen_reserve_special_pages(); 1304 1305 /* 1306 * We used to do this in xen_arch_setup, but that is too late 1307 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1308 * early_amd_init which pokes 0xcf8 port. 1309 */ 1310 set_iopl.iopl = 1; 1311 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1312 if (rc != 0) 1313 xen_raw_printk("physdev_op failed %d\n", rc); 1314 1315 1316 if (xen_start_info->mod_start) { 1317 if (xen_start_info->flags & SIF_MOD_START_PFN) 1318 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1319 else 1320 initrd_start = __pa(xen_start_info->mod_start); 1321 } 1322 1323 /* Poke various useful things into boot_params */ 1324 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1325 boot_params.hdr.ramdisk_image = initrd_start; 1326 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1327 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1328 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1329 1330 if (!xen_initial_domain()) { 1331 if (pci_xen) 1332 x86_init.pci.arch_init = pci_xen_init; 1333 x86_platform.set_legacy_features = 1334 xen_domu_set_legacy_features; 1335 } else { 1336 const struct dom0_vga_console_info *info = 1337 (void *)((char *)xen_start_info + 1338 xen_start_info->console.dom0.info_off); 1339 struct xen_platform_op op = { 1340 .cmd = XENPF_firmware_info, 1341 .interface_version = XENPF_INTERFACE_VERSION, 1342 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1343 }; 1344 1345 x86_platform.set_legacy_features = 1346 xen_dom0_set_legacy_features; 1347 xen_init_vga(info, xen_start_info->console.dom0.info_size); 1348 xen_start_info->console.domU.mfn = 0; 1349 xen_start_info->console.domU.evtchn = 0; 1350 1351 if (HYPERVISOR_platform_op(&op) == 0) 1352 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1353 1354 /* Make sure ACS will be enabled */ 1355 pci_request_acs(); 1356 1357 xen_acpi_sleep_register(); 1358 1359 xen_boot_params_init_edd(); 1360 1361 #ifdef CONFIG_ACPI 1362 /* 1363 * Disable selecting "Firmware First mode" for correctable 1364 * memory errors, as this is the duty of the hypervisor to 1365 * decide. 1366 */ 1367 acpi_disable_cmcff = 1; 1368 #endif 1369 } 1370 1371 xen_add_preferred_consoles(); 1372 1373 #ifdef CONFIG_PCI 1374 /* PCI BIOS service won't work from a PV guest. */ 1375 pci_probe &= ~PCI_PROBE_BIOS; 1376 #endif 1377 xen_raw_console_write("about to get started...\n"); 1378 1379 /* We need this for printk timestamps */ 1380 xen_setup_runstate_info(0); 1381 1382 xen_efi_init(&boot_params); 1383 1384 /* Start the world */ 1385 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1386 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1387 } 1388 1389 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1390 { 1391 int rc; 1392 1393 if (per_cpu(xen_vcpu, cpu) == NULL) 1394 return -ENODEV; 1395 1396 xen_setup_timer(cpu); 1397 1398 rc = xen_smp_intr_init(cpu); 1399 if (rc) { 1400 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1401 cpu, rc); 1402 return rc; 1403 } 1404 1405 rc = xen_smp_intr_init_pv(cpu); 1406 if (rc) { 1407 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1408 cpu, rc); 1409 return rc; 1410 } 1411 1412 return 0; 1413 } 1414 1415 static int xen_cpu_dead_pv(unsigned int cpu) 1416 { 1417 xen_smp_intr_free(cpu); 1418 xen_smp_intr_free_pv(cpu); 1419 1420 xen_teardown_timer(cpu); 1421 1422 return 0; 1423 } 1424 1425 static uint32_t __init xen_platform_pv(void) 1426 { 1427 if (xen_pv_domain()) 1428 return xen_cpuid_base(); 1429 1430 return 0; 1431 } 1432 1433 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1434 .name = "Xen PV", 1435 .detect = xen_platform_pv, 1436 .type = X86_HYPER_XEN_PV, 1437 .runtime.pin_vcpu = xen_pin_vcpu, 1438 .ignore_nopv = true, 1439 }; 1440