1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Core of Xen paravirt_ops implementation. 4 * 5 * This file contains the xen_paravirt_ops structure itself, and the 6 * implementations for: 7 * - privileged instructions 8 * - interrupt flags 9 * - segment operations 10 * - booting and setup 11 * 12 * Jeremy Fitzhardinge <jeremy@xensource.com>, XenSource Inc, 2007 13 */ 14 15 #include <linux/cpu.h> 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/smp.h> 19 #include <linux/preempt.h> 20 #include <linux/hardirq.h> 21 #include <linux/percpu.h> 22 #include <linux/delay.h> 23 #include <linux/start_kernel.h> 24 #include <linux/sched.h> 25 #include <linux/kprobes.h> 26 #include <linux/memblock.h> 27 #include <linux/export.h> 28 #include <linux/mm.h> 29 #include <linux/page-flags.h> 30 #include <linux/pci.h> 31 #include <linux/gfp.h> 32 #include <linux/edd.h> 33 #include <linux/reboot.h> 34 #include <linux/virtio_anchor.h> 35 36 #include <xen/xen.h> 37 #include <xen/events.h> 38 #include <xen/interface/xen.h> 39 #include <xen/interface/version.h> 40 #include <xen/interface/physdev.h> 41 #include <xen/interface/vcpu.h> 42 #include <xen/interface/memory.h> 43 #include <xen/interface/nmi.h> 44 #include <xen/interface/xen-mca.h> 45 #include <xen/features.h> 46 #include <xen/page.h> 47 #include <xen/hvc-console.h> 48 #include <xen/acpi.h> 49 50 #include <asm/paravirt.h> 51 #include <asm/apic.h> 52 #include <asm/page.h> 53 #include <asm/xen/pci.h> 54 #include <asm/xen/hypercall.h> 55 #include <asm/xen/hypervisor.h> 56 #include <asm/xen/cpuid.h> 57 #include <asm/fixmap.h> 58 #include <asm/processor.h> 59 #include <asm/proto.h> 60 #include <asm/msr-index.h> 61 #include <asm/traps.h> 62 #include <asm/setup.h> 63 #include <asm/desc.h> 64 #include <asm/pgalloc.h> 65 #include <asm/tlbflush.h> 66 #include <asm/reboot.h> 67 #include <asm/stackprotector.h> 68 #include <asm/hypervisor.h> 69 #include <asm/mach_traps.h> 70 #include <asm/mwait.h> 71 #include <asm/pci_x86.h> 72 #include <asm/cpu.h> 73 #ifdef CONFIG_X86_IOPL_IOPERM 74 #include <asm/io_bitmap.h> 75 #endif 76 77 #ifdef CONFIG_ACPI 78 #include <linux/acpi.h> 79 #include <asm/acpi.h> 80 #include <acpi/pdc_intel.h> 81 #include <acpi/processor.h> 82 #include <xen/interface/platform.h> 83 #endif 84 85 #include "xen-ops.h" 86 #include "mmu.h" 87 #include "smp.h" 88 #include "multicalls.h" 89 #include "pmu.h" 90 91 #include "../kernel/cpu/cpu.h" /* get_cpu_cap() */ 92 93 void *xen_initial_gdt; 94 95 static int xen_cpu_up_prepare_pv(unsigned int cpu); 96 static int xen_cpu_dead_pv(unsigned int cpu); 97 98 struct tls_descs { 99 struct desc_struct desc[3]; 100 }; 101 102 /* 103 * Updating the 3 TLS descriptors in the GDT on every task switch is 104 * surprisingly expensive so we avoid updating them if they haven't 105 * changed. Since Xen writes different descriptors than the one 106 * passed in the update_descriptor hypercall we keep shadow copies to 107 * compare against. 108 */ 109 static DEFINE_PER_CPU(struct tls_descs, shadow_tls_desc); 110 111 static __read_mostly bool xen_msr_safe = IS_ENABLED(CONFIG_XEN_PV_MSR_SAFE); 112 113 static int __init parse_xen_msr_safe(char *str) 114 { 115 if (str) 116 return strtobool(str, &xen_msr_safe); 117 return -EINVAL; 118 } 119 early_param("xen_msr_safe", parse_xen_msr_safe); 120 121 static void __init xen_pv_init_platform(void) 122 { 123 /* PV guests can't operate virtio devices without grants. */ 124 if (IS_ENABLED(CONFIG_XEN_VIRTIO)) 125 virtio_set_mem_acc_cb(xen_virtio_restricted_mem_acc); 126 127 populate_extra_pte(fix_to_virt(FIX_PARAVIRT_BOOTMAP)); 128 129 set_fixmap(FIX_PARAVIRT_BOOTMAP, xen_start_info->shared_info); 130 HYPERVISOR_shared_info = (void *)fix_to_virt(FIX_PARAVIRT_BOOTMAP); 131 132 /* xen clock uses per-cpu vcpu_info, need to init it for boot cpu */ 133 xen_vcpu_info_reset(0); 134 135 /* pvclock is in shared info area */ 136 xen_init_time_ops(); 137 } 138 139 static void __init xen_pv_guest_late_init(void) 140 { 141 #ifndef CONFIG_SMP 142 /* Setup shared vcpu info for non-smp configurations */ 143 xen_setup_vcpu_info_placement(); 144 #endif 145 } 146 147 static __read_mostly unsigned int cpuid_leaf5_ecx_val; 148 static __read_mostly unsigned int cpuid_leaf5_edx_val; 149 150 static void xen_cpuid(unsigned int *ax, unsigned int *bx, 151 unsigned int *cx, unsigned int *dx) 152 { 153 unsigned maskebx = ~0; 154 155 /* 156 * Mask out inconvenient features, to try and disable as many 157 * unsupported kernel subsystems as possible. 158 */ 159 switch (*ax) { 160 case CPUID_MWAIT_LEAF: 161 /* Synthesize the values.. */ 162 *ax = 0; 163 *bx = 0; 164 *cx = cpuid_leaf5_ecx_val; 165 *dx = cpuid_leaf5_edx_val; 166 return; 167 168 case 0xb: 169 /* Suppress extended topology stuff */ 170 maskebx = 0; 171 break; 172 } 173 174 asm(XEN_EMULATE_PREFIX "cpuid" 175 : "=a" (*ax), 176 "=b" (*bx), 177 "=c" (*cx), 178 "=d" (*dx) 179 : "0" (*ax), "2" (*cx)); 180 181 *bx &= maskebx; 182 } 183 184 static bool __init xen_check_mwait(void) 185 { 186 #ifdef CONFIG_ACPI 187 struct xen_platform_op op = { 188 .cmd = XENPF_set_processor_pminfo, 189 .u.set_pminfo.id = -1, 190 .u.set_pminfo.type = XEN_PM_PDC, 191 }; 192 uint32_t buf[3]; 193 unsigned int ax, bx, cx, dx; 194 unsigned int mwait_mask; 195 196 /* We need to determine whether it is OK to expose the MWAIT 197 * capability to the kernel to harvest deeper than C3 states from ACPI 198 * _CST using the processor_harvest_xen.c module. For this to work, we 199 * need to gather the MWAIT_LEAF values (which the cstate.c code 200 * checks against). The hypervisor won't expose the MWAIT flag because 201 * it would break backwards compatibility; so we will find out directly 202 * from the hardware and hypercall. 203 */ 204 if (!xen_initial_domain()) 205 return false; 206 207 /* 208 * When running under platform earlier than Xen4.2, do not expose 209 * mwait, to avoid the risk of loading native acpi pad driver 210 */ 211 if (!xen_running_on_version_or_later(4, 2)) 212 return false; 213 214 ax = 1; 215 cx = 0; 216 217 native_cpuid(&ax, &bx, &cx, &dx); 218 219 mwait_mask = (1 << (X86_FEATURE_EST % 32)) | 220 (1 << (X86_FEATURE_MWAIT % 32)); 221 222 if ((cx & mwait_mask) != mwait_mask) 223 return false; 224 225 /* We need to emulate the MWAIT_LEAF and for that we need both 226 * ecx and edx. The hypercall provides only partial information. 227 */ 228 229 ax = CPUID_MWAIT_LEAF; 230 bx = 0; 231 cx = 0; 232 dx = 0; 233 234 native_cpuid(&ax, &bx, &cx, &dx); 235 236 /* Ask the Hypervisor whether to clear ACPI_PDC_C_C2C3_FFH. If so, 237 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3. 238 */ 239 buf[0] = ACPI_PDC_REVISION_ID; 240 buf[1] = 1; 241 buf[2] = (ACPI_PDC_C_CAPABILITY_SMP | ACPI_PDC_EST_CAPABILITY_SWSMP); 242 243 set_xen_guest_handle(op.u.set_pminfo.pdc, buf); 244 245 if ((HYPERVISOR_platform_op(&op) == 0) && 246 (buf[2] & (ACPI_PDC_C_C1_FFH | ACPI_PDC_C_C2C3_FFH))) { 247 cpuid_leaf5_ecx_val = cx; 248 cpuid_leaf5_edx_val = dx; 249 } 250 return true; 251 #else 252 return false; 253 #endif 254 } 255 256 static bool __init xen_check_xsave(void) 257 { 258 unsigned int cx, xsave_mask; 259 260 cx = cpuid_ecx(1); 261 262 xsave_mask = (1 << (X86_FEATURE_XSAVE % 32)) | 263 (1 << (X86_FEATURE_OSXSAVE % 32)); 264 265 /* Xen will set CR4.OSXSAVE if supported and not disabled by force */ 266 return (cx & xsave_mask) == xsave_mask; 267 } 268 269 static void __init xen_init_capabilities(void) 270 { 271 setup_force_cpu_cap(X86_FEATURE_XENPV); 272 setup_clear_cpu_cap(X86_FEATURE_DCA); 273 setup_clear_cpu_cap(X86_FEATURE_APERFMPERF); 274 setup_clear_cpu_cap(X86_FEATURE_MTRR); 275 setup_clear_cpu_cap(X86_FEATURE_ACC); 276 setup_clear_cpu_cap(X86_FEATURE_X2APIC); 277 setup_clear_cpu_cap(X86_FEATURE_SME); 278 279 /* 280 * Xen PV would need some work to support PCID: CR3 handling as well 281 * as xen_flush_tlb_others() would need updating. 282 */ 283 setup_clear_cpu_cap(X86_FEATURE_PCID); 284 285 if (!xen_initial_domain()) 286 setup_clear_cpu_cap(X86_FEATURE_ACPI); 287 288 if (xen_check_mwait()) 289 setup_force_cpu_cap(X86_FEATURE_MWAIT); 290 else 291 setup_clear_cpu_cap(X86_FEATURE_MWAIT); 292 293 if (!xen_check_xsave()) { 294 setup_clear_cpu_cap(X86_FEATURE_XSAVE); 295 setup_clear_cpu_cap(X86_FEATURE_OSXSAVE); 296 } 297 } 298 299 static noinstr void xen_set_debugreg(int reg, unsigned long val) 300 { 301 HYPERVISOR_set_debugreg(reg, val); 302 } 303 304 static noinstr unsigned long xen_get_debugreg(int reg) 305 { 306 return HYPERVISOR_get_debugreg(reg); 307 } 308 309 static void xen_end_context_switch(struct task_struct *next) 310 { 311 xen_mc_flush(); 312 paravirt_end_context_switch(next); 313 } 314 315 static unsigned long xen_store_tr(void) 316 { 317 return 0; 318 } 319 320 /* 321 * Set the page permissions for a particular virtual address. If the 322 * address is a vmalloc mapping (or other non-linear mapping), then 323 * find the linear mapping of the page and also set its protections to 324 * match. 325 */ 326 static void set_aliased_prot(void *v, pgprot_t prot) 327 { 328 int level; 329 pte_t *ptep; 330 pte_t pte; 331 unsigned long pfn; 332 unsigned char dummy; 333 void *va; 334 335 ptep = lookup_address((unsigned long)v, &level); 336 BUG_ON(ptep == NULL); 337 338 pfn = pte_pfn(*ptep); 339 pte = pfn_pte(pfn, prot); 340 341 /* 342 * Careful: update_va_mapping() will fail if the virtual address 343 * we're poking isn't populated in the page tables. We don't 344 * need to worry about the direct map (that's always in the page 345 * tables), but we need to be careful about vmap space. In 346 * particular, the top level page table can lazily propagate 347 * entries between processes, so if we've switched mms since we 348 * vmapped the target in the first place, we might not have the 349 * top-level page table entry populated. 350 * 351 * We disable preemption because we want the same mm active when 352 * we probe the target and when we issue the hypercall. We'll 353 * have the same nominal mm, but if we're a kernel thread, lazy 354 * mm dropping could change our pgd. 355 * 356 * Out of an abundance of caution, this uses __get_user() to fault 357 * in the target address just in case there's some obscure case 358 * in which the target address isn't readable. 359 */ 360 361 preempt_disable(); 362 363 copy_from_kernel_nofault(&dummy, v, 1); 364 365 if (HYPERVISOR_update_va_mapping((unsigned long)v, pte, 0)) 366 BUG(); 367 368 va = __va(PFN_PHYS(pfn)); 369 370 if (va != v && HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 371 BUG(); 372 373 preempt_enable(); 374 } 375 376 static void xen_alloc_ldt(struct desc_struct *ldt, unsigned entries) 377 { 378 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 379 int i; 380 381 /* 382 * We need to mark the all aliases of the LDT pages RO. We 383 * don't need to call vm_flush_aliases(), though, since that's 384 * only responsible for flushing aliases out the TLBs, not the 385 * page tables, and Xen will flush the TLB for us if needed. 386 * 387 * To avoid confusing future readers: none of this is necessary 388 * to load the LDT. The hypervisor only checks this when the 389 * LDT is faulted in due to subsequent descriptor access. 390 */ 391 392 for (i = 0; i < entries; i += entries_per_page) 393 set_aliased_prot(ldt + i, PAGE_KERNEL_RO); 394 } 395 396 static void xen_free_ldt(struct desc_struct *ldt, unsigned entries) 397 { 398 const unsigned entries_per_page = PAGE_SIZE / LDT_ENTRY_SIZE; 399 int i; 400 401 for (i = 0; i < entries; i += entries_per_page) 402 set_aliased_prot(ldt + i, PAGE_KERNEL); 403 } 404 405 static void xen_set_ldt(const void *addr, unsigned entries) 406 { 407 struct mmuext_op *op; 408 struct multicall_space mcs = xen_mc_entry(sizeof(*op)); 409 410 trace_xen_cpu_set_ldt(addr, entries); 411 412 op = mcs.args; 413 op->cmd = MMUEXT_SET_LDT; 414 op->arg1.linear_addr = (unsigned long)addr; 415 op->arg2.nr_ents = entries; 416 417 MULTI_mmuext_op(mcs.mc, op, 1, NULL, DOMID_SELF); 418 419 xen_mc_issue(PARAVIRT_LAZY_CPU); 420 } 421 422 static void xen_load_gdt(const struct desc_ptr *dtr) 423 { 424 unsigned long va = dtr->address; 425 unsigned int size = dtr->size + 1; 426 unsigned long pfn, mfn; 427 int level; 428 pte_t *ptep; 429 void *virt; 430 431 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 432 BUG_ON(size > PAGE_SIZE); 433 BUG_ON(va & ~PAGE_MASK); 434 435 /* 436 * The GDT is per-cpu and is in the percpu data area. 437 * That can be virtually mapped, so we need to do a 438 * page-walk to get the underlying MFN for the 439 * hypercall. The page can also be in the kernel's 440 * linear range, so we need to RO that mapping too. 441 */ 442 ptep = lookup_address(va, &level); 443 BUG_ON(ptep == NULL); 444 445 pfn = pte_pfn(*ptep); 446 mfn = pfn_to_mfn(pfn); 447 virt = __va(PFN_PHYS(pfn)); 448 449 make_lowmem_page_readonly((void *)va); 450 make_lowmem_page_readonly(virt); 451 452 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 453 BUG(); 454 } 455 456 /* 457 * load_gdt for early boot, when the gdt is only mapped once 458 */ 459 static void __init xen_load_gdt_boot(const struct desc_ptr *dtr) 460 { 461 unsigned long va = dtr->address; 462 unsigned int size = dtr->size + 1; 463 unsigned long pfn, mfn; 464 pte_t pte; 465 466 /* @size should be at most GDT_SIZE which is smaller than PAGE_SIZE. */ 467 BUG_ON(size > PAGE_SIZE); 468 BUG_ON(va & ~PAGE_MASK); 469 470 pfn = virt_to_pfn(va); 471 mfn = pfn_to_mfn(pfn); 472 473 pte = pfn_pte(pfn, PAGE_KERNEL_RO); 474 475 if (HYPERVISOR_update_va_mapping((unsigned long)va, pte, 0)) 476 BUG(); 477 478 if (HYPERVISOR_set_gdt(&mfn, size / sizeof(struct desc_struct))) 479 BUG(); 480 } 481 482 static inline bool desc_equal(const struct desc_struct *d1, 483 const struct desc_struct *d2) 484 { 485 return !memcmp(d1, d2, sizeof(*d1)); 486 } 487 488 static void load_TLS_descriptor(struct thread_struct *t, 489 unsigned int cpu, unsigned int i) 490 { 491 struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i]; 492 struct desc_struct *gdt; 493 xmaddr_t maddr; 494 struct multicall_space mc; 495 496 if (desc_equal(shadow, &t->tls_array[i])) 497 return; 498 499 *shadow = t->tls_array[i]; 500 501 gdt = get_cpu_gdt_rw(cpu); 502 maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN+i]); 503 mc = __xen_mc_entry(0); 504 505 MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]); 506 } 507 508 static void xen_load_tls(struct thread_struct *t, unsigned int cpu) 509 { 510 /* 511 * In lazy mode we need to zero %fs, otherwise we may get an 512 * exception between the new %fs descriptor being loaded and 513 * %fs being effectively cleared at __switch_to(). 514 */ 515 if (paravirt_get_lazy_mode() == PARAVIRT_LAZY_CPU) 516 loadsegment(fs, 0); 517 518 xen_mc_batch(); 519 520 load_TLS_descriptor(t, cpu, 0); 521 load_TLS_descriptor(t, cpu, 1); 522 load_TLS_descriptor(t, cpu, 2); 523 524 xen_mc_issue(PARAVIRT_LAZY_CPU); 525 } 526 527 static void xen_load_gs_index(unsigned int idx) 528 { 529 if (HYPERVISOR_set_segment_base(SEGBASE_GS_USER_SEL, idx)) 530 BUG(); 531 } 532 533 static void xen_write_ldt_entry(struct desc_struct *dt, int entrynum, 534 const void *ptr) 535 { 536 xmaddr_t mach_lp = arbitrary_virt_to_machine(&dt[entrynum]); 537 u64 entry = *(u64 *)ptr; 538 539 trace_xen_cpu_write_ldt_entry(dt, entrynum, entry); 540 541 preempt_disable(); 542 543 xen_mc_flush(); 544 if (HYPERVISOR_update_descriptor(mach_lp.maddr, entry)) 545 BUG(); 546 547 preempt_enable(); 548 } 549 550 void noist_exc_debug(struct pt_regs *regs); 551 552 DEFINE_IDTENTRY_RAW(xenpv_exc_nmi) 553 { 554 /* On Xen PV, NMI doesn't use IST. The C part is the same as native. */ 555 exc_nmi(regs); 556 } 557 558 DEFINE_IDTENTRY_RAW_ERRORCODE(xenpv_exc_double_fault) 559 { 560 /* On Xen PV, DF doesn't use IST. The C part is the same as native. */ 561 exc_double_fault(regs, error_code); 562 } 563 564 DEFINE_IDTENTRY_RAW(xenpv_exc_debug) 565 { 566 /* 567 * There's no IST on Xen PV, but we still need to dispatch 568 * to the correct handler. 569 */ 570 if (user_mode(regs)) 571 noist_exc_debug(regs); 572 else 573 exc_debug(regs); 574 } 575 576 DEFINE_IDTENTRY_RAW(exc_xen_unknown_trap) 577 { 578 /* This should never happen and there is no way to handle it. */ 579 instrumentation_begin(); 580 pr_err("Unknown trap in Xen PV mode."); 581 BUG(); 582 instrumentation_end(); 583 } 584 585 #ifdef CONFIG_X86_MCE 586 DEFINE_IDTENTRY_RAW(xenpv_exc_machine_check) 587 { 588 /* 589 * There's no IST on Xen PV, but we still need to dispatch 590 * to the correct handler. 591 */ 592 if (user_mode(regs)) 593 noist_exc_machine_check(regs); 594 else 595 exc_machine_check(regs); 596 } 597 #endif 598 599 struct trap_array_entry { 600 void (*orig)(void); 601 void (*xen)(void); 602 bool ist_okay; 603 }; 604 605 #define TRAP_ENTRY(func, ist_ok) { \ 606 .orig = asm_##func, \ 607 .xen = xen_asm_##func, \ 608 .ist_okay = ist_ok } 609 610 #define TRAP_ENTRY_REDIR(func, ist_ok) { \ 611 .orig = asm_##func, \ 612 .xen = xen_asm_xenpv_##func, \ 613 .ist_okay = ist_ok } 614 615 static struct trap_array_entry trap_array[] = { 616 TRAP_ENTRY_REDIR(exc_debug, true ), 617 TRAP_ENTRY_REDIR(exc_double_fault, true ), 618 #ifdef CONFIG_X86_MCE 619 TRAP_ENTRY_REDIR(exc_machine_check, true ), 620 #endif 621 TRAP_ENTRY_REDIR(exc_nmi, true ), 622 TRAP_ENTRY(exc_int3, false ), 623 TRAP_ENTRY(exc_overflow, false ), 624 #ifdef CONFIG_IA32_EMULATION 625 { entry_INT80_compat, xen_entry_INT80_compat, false }, 626 #endif 627 TRAP_ENTRY(exc_page_fault, false ), 628 TRAP_ENTRY(exc_divide_error, false ), 629 TRAP_ENTRY(exc_bounds, false ), 630 TRAP_ENTRY(exc_invalid_op, false ), 631 TRAP_ENTRY(exc_device_not_available, false ), 632 TRAP_ENTRY(exc_coproc_segment_overrun, false ), 633 TRAP_ENTRY(exc_invalid_tss, false ), 634 TRAP_ENTRY(exc_segment_not_present, false ), 635 TRAP_ENTRY(exc_stack_segment, false ), 636 TRAP_ENTRY(exc_general_protection, false ), 637 TRAP_ENTRY(exc_spurious_interrupt_bug, false ), 638 TRAP_ENTRY(exc_coprocessor_error, false ), 639 TRAP_ENTRY(exc_alignment_check, false ), 640 TRAP_ENTRY(exc_simd_coprocessor_error, false ), 641 #ifdef CONFIG_X86_KERNEL_IBT 642 TRAP_ENTRY(exc_control_protection, false ), 643 #endif 644 }; 645 646 static bool __ref get_trap_addr(void **addr, unsigned int ist) 647 { 648 unsigned int nr; 649 bool ist_okay = false; 650 bool found = false; 651 652 /* 653 * Replace trap handler addresses by Xen specific ones. 654 * Check for known traps using IST and whitelist them. 655 * The debugger ones are the only ones we care about. 656 * Xen will handle faults like double_fault, so we should never see 657 * them. Warn if there's an unexpected IST-using fault handler. 658 */ 659 for (nr = 0; nr < ARRAY_SIZE(trap_array); nr++) { 660 struct trap_array_entry *entry = trap_array + nr; 661 662 if (*addr == entry->orig) { 663 *addr = entry->xen; 664 ist_okay = entry->ist_okay; 665 found = true; 666 break; 667 } 668 } 669 670 if (nr == ARRAY_SIZE(trap_array) && 671 *addr >= (void *)early_idt_handler_array[0] && 672 *addr < (void *)early_idt_handler_array[NUM_EXCEPTION_VECTORS]) { 673 nr = (*addr - (void *)early_idt_handler_array[0]) / 674 EARLY_IDT_HANDLER_SIZE; 675 *addr = (void *)xen_early_idt_handler_array[nr]; 676 found = true; 677 } 678 679 if (!found) 680 *addr = (void *)xen_asm_exc_xen_unknown_trap; 681 682 if (WARN_ON(found && ist != 0 && !ist_okay)) 683 return false; 684 685 return true; 686 } 687 688 static int cvt_gate_to_trap(int vector, const gate_desc *val, 689 struct trap_info *info) 690 { 691 unsigned long addr; 692 693 if (val->bits.type != GATE_TRAP && val->bits.type != GATE_INTERRUPT) 694 return 0; 695 696 info->vector = vector; 697 698 addr = gate_offset(val); 699 if (!get_trap_addr((void **)&addr, val->bits.ist)) 700 return 0; 701 info->address = addr; 702 703 info->cs = gate_segment(val); 704 info->flags = val->bits.dpl; 705 /* interrupt gates clear IF */ 706 if (val->bits.type == GATE_INTERRUPT) 707 info->flags |= 1 << 2; 708 709 return 1; 710 } 711 712 /* Locations of each CPU's IDT */ 713 static DEFINE_PER_CPU(struct desc_ptr, idt_desc); 714 715 /* Set an IDT entry. If the entry is part of the current IDT, then 716 also update Xen. */ 717 static void xen_write_idt_entry(gate_desc *dt, int entrynum, const gate_desc *g) 718 { 719 unsigned long p = (unsigned long)&dt[entrynum]; 720 unsigned long start, end; 721 722 trace_xen_cpu_write_idt_entry(dt, entrynum, g); 723 724 preempt_disable(); 725 726 start = __this_cpu_read(idt_desc.address); 727 end = start + __this_cpu_read(idt_desc.size) + 1; 728 729 xen_mc_flush(); 730 731 native_write_idt_entry(dt, entrynum, g); 732 733 if (p >= start && (p + 8) <= end) { 734 struct trap_info info[2]; 735 736 info[1].address = 0; 737 738 if (cvt_gate_to_trap(entrynum, g, &info[0])) 739 if (HYPERVISOR_set_trap_table(info)) 740 BUG(); 741 } 742 743 preempt_enable(); 744 } 745 746 static unsigned xen_convert_trap_info(const struct desc_ptr *desc, 747 struct trap_info *traps, bool full) 748 { 749 unsigned in, out, count; 750 751 count = (desc->size+1) / sizeof(gate_desc); 752 BUG_ON(count > 256); 753 754 for (in = out = 0; in < count; in++) { 755 gate_desc *entry = (gate_desc *)(desc->address) + in; 756 757 if (cvt_gate_to_trap(in, entry, &traps[out]) || full) 758 out++; 759 } 760 761 return out; 762 } 763 764 void xen_copy_trap_info(struct trap_info *traps) 765 { 766 const struct desc_ptr *desc = this_cpu_ptr(&idt_desc); 767 768 xen_convert_trap_info(desc, traps, true); 769 } 770 771 /* Load a new IDT into Xen. In principle this can be per-CPU, so we 772 hold a spinlock to protect the static traps[] array (static because 773 it avoids allocation, and saves stack space). */ 774 static void xen_load_idt(const struct desc_ptr *desc) 775 { 776 static DEFINE_SPINLOCK(lock); 777 static struct trap_info traps[257]; 778 static const struct trap_info zero = { }; 779 unsigned out; 780 781 trace_xen_cpu_load_idt(desc); 782 783 spin_lock(&lock); 784 785 memcpy(this_cpu_ptr(&idt_desc), desc, sizeof(idt_desc)); 786 787 out = xen_convert_trap_info(desc, traps, false); 788 traps[out] = zero; 789 790 xen_mc_flush(); 791 if (HYPERVISOR_set_trap_table(traps)) 792 BUG(); 793 794 spin_unlock(&lock); 795 } 796 797 /* Write a GDT descriptor entry. Ignore LDT descriptors, since 798 they're handled differently. */ 799 static void xen_write_gdt_entry(struct desc_struct *dt, int entry, 800 const void *desc, int type) 801 { 802 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 803 804 preempt_disable(); 805 806 switch (type) { 807 case DESC_LDT: 808 case DESC_TSS: 809 /* ignore */ 810 break; 811 812 default: { 813 xmaddr_t maddr = arbitrary_virt_to_machine(&dt[entry]); 814 815 xen_mc_flush(); 816 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 817 BUG(); 818 } 819 820 } 821 822 preempt_enable(); 823 } 824 825 /* 826 * Version of write_gdt_entry for use at early boot-time needed to 827 * update an entry as simply as possible. 828 */ 829 static void __init xen_write_gdt_entry_boot(struct desc_struct *dt, int entry, 830 const void *desc, int type) 831 { 832 trace_xen_cpu_write_gdt_entry(dt, entry, desc, type); 833 834 switch (type) { 835 case DESC_LDT: 836 case DESC_TSS: 837 /* ignore */ 838 break; 839 840 default: { 841 xmaddr_t maddr = virt_to_machine(&dt[entry]); 842 843 if (HYPERVISOR_update_descriptor(maddr.maddr, *(u64 *)desc)) 844 dt[entry] = *(struct desc_struct *)desc; 845 } 846 847 } 848 } 849 850 static void xen_load_sp0(unsigned long sp0) 851 { 852 struct multicall_space mcs; 853 854 mcs = xen_mc_entry(0); 855 MULTI_stack_switch(mcs.mc, __KERNEL_DS, sp0); 856 xen_mc_issue(PARAVIRT_LAZY_CPU); 857 this_cpu_write(cpu_tss_rw.x86_tss.sp0, sp0); 858 } 859 860 #ifdef CONFIG_X86_IOPL_IOPERM 861 static void xen_invalidate_io_bitmap(void) 862 { 863 struct physdev_set_iobitmap iobitmap = { 864 .bitmap = NULL, 865 .nr_ports = 0, 866 }; 867 868 native_tss_invalidate_io_bitmap(); 869 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 870 } 871 872 static void xen_update_io_bitmap(void) 873 { 874 struct physdev_set_iobitmap iobitmap; 875 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw); 876 877 native_tss_update_io_bitmap(); 878 879 iobitmap.bitmap = (uint8_t *)(&tss->x86_tss) + 880 tss->x86_tss.io_bitmap_base; 881 if (tss->x86_tss.io_bitmap_base == IO_BITMAP_OFFSET_INVALID) 882 iobitmap.nr_ports = 0; 883 else 884 iobitmap.nr_ports = IO_BITMAP_BITS; 885 886 HYPERVISOR_physdev_op(PHYSDEVOP_set_iobitmap, &iobitmap); 887 } 888 #endif 889 890 static void xen_io_delay(void) 891 { 892 } 893 894 static DEFINE_PER_CPU(unsigned long, xen_cr0_value); 895 896 static unsigned long xen_read_cr0(void) 897 { 898 unsigned long cr0 = this_cpu_read(xen_cr0_value); 899 900 if (unlikely(cr0 == 0)) { 901 cr0 = native_read_cr0(); 902 this_cpu_write(xen_cr0_value, cr0); 903 } 904 905 return cr0; 906 } 907 908 static void xen_write_cr0(unsigned long cr0) 909 { 910 struct multicall_space mcs; 911 912 this_cpu_write(xen_cr0_value, cr0); 913 914 /* Only pay attention to cr0.TS; everything else is 915 ignored. */ 916 mcs = xen_mc_entry(0); 917 918 MULTI_fpu_taskswitch(mcs.mc, (cr0 & X86_CR0_TS) != 0); 919 920 xen_mc_issue(PARAVIRT_LAZY_CPU); 921 } 922 923 static void xen_write_cr4(unsigned long cr4) 924 { 925 cr4 &= ~(X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PCE); 926 927 native_write_cr4(cr4); 928 } 929 930 static u64 xen_do_read_msr(unsigned int msr, int *err) 931 { 932 u64 val = 0; /* Avoid uninitialized value for safe variant. */ 933 934 if (pmu_msr_read(msr, &val, err)) 935 return val; 936 937 if (err) 938 val = native_read_msr_safe(msr, err); 939 else 940 val = native_read_msr(msr); 941 942 switch (msr) { 943 case MSR_IA32_APICBASE: 944 val &= ~X2APIC_ENABLE; 945 break; 946 } 947 return val; 948 } 949 950 static void set_seg(unsigned int which, unsigned int low, unsigned int high, 951 int *err) 952 { 953 u64 base = ((u64)high << 32) | low; 954 955 if (HYPERVISOR_set_segment_base(which, base) == 0) 956 return; 957 958 if (err) 959 *err = -EIO; 960 else 961 WARN(1, "Xen set_segment_base(%u, %llx) failed\n", which, base); 962 } 963 964 /* 965 * Support write_msr_safe() and write_msr() semantics. 966 * With err == NULL write_msr() semantics are selected. 967 * Supplying an err pointer requires err to be pre-initialized with 0. 968 */ 969 static void xen_do_write_msr(unsigned int msr, unsigned int low, 970 unsigned int high, int *err) 971 { 972 switch (msr) { 973 case MSR_FS_BASE: 974 set_seg(SEGBASE_FS, low, high, err); 975 break; 976 977 case MSR_KERNEL_GS_BASE: 978 set_seg(SEGBASE_GS_USER, low, high, err); 979 break; 980 981 case MSR_GS_BASE: 982 set_seg(SEGBASE_GS_KERNEL, low, high, err); 983 break; 984 985 case MSR_STAR: 986 case MSR_CSTAR: 987 case MSR_LSTAR: 988 case MSR_SYSCALL_MASK: 989 case MSR_IA32_SYSENTER_CS: 990 case MSR_IA32_SYSENTER_ESP: 991 case MSR_IA32_SYSENTER_EIP: 992 /* Fast syscall setup is all done in hypercalls, so 993 these are all ignored. Stub them out here to stop 994 Xen console noise. */ 995 break; 996 997 default: 998 if (!pmu_msr_write(msr, low, high, err)) { 999 if (err) 1000 *err = native_write_msr_safe(msr, low, high); 1001 else 1002 native_write_msr(msr, low, high); 1003 } 1004 } 1005 } 1006 1007 static u64 xen_read_msr_safe(unsigned int msr, int *err) 1008 { 1009 return xen_do_read_msr(msr, err); 1010 } 1011 1012 static int xen_write_msr_safe(unsigned int msr, unsigned int low, 1013 unsigned int high) 1014 { 1015 int err = 0; 1016 1017 xen_do_write_msr(msr, low, high, &err); 1018 1019 return err; 1020 } 1021 1022 static u64 xen_read_msr(unsigned int msr) 1023 { 1024 int err; 1025 1026 return xen_do_read_msr(msr, xen_msr_safe ? &err : NULL); 1027 } 1028 1029 static void xen_write_msr(unsigned int msr, unsigned low, unsigned high) 1030 { 1031 int err; 1032 1033 xen_do_write_msr(msr, low, high, xen_msr_safe ? &err : NULL); 1034 } 1035 1036 /* This is called once we have the cpu_possible_mask */ 1037 void __init xen_setup_vcpu_info_placement(void) 1038 { 1039 int cpu; 1040 1041 for_each_possible_cpu(cpu) { 1042 /* Set up direct vCPU id mapping for PV guests. */ 1043 per_cpu(xen_vcpu_id, cpu) = cpu; 1044 xen_vcpu_setup(cpu); 1045 } 1046 1047 pv_ops.irq.save_fl = __PV_IS_CALLEE_SAVE(xen_save_fl_direct); 1048 pv_ops.irq.irq_disable = __PV_IS_CALLEE_SAVE(xen_irq_disable_direct); 1049 pv_ops.irq.irq_enable = __PV_IS_CALLEE_SAVE(xen_irq_enable_direct); 1050 pv_ops.mmu.read_cr2 = __PV_IS_CALLEE_SAVE(xen_read_cr2_direct); 1051 } 1052 1053 static const struct pv_info xen_info __initconst = { 1054 .extra_user_64bit_cs = FLAT_USER_CS64, 1055 .name = "Xen", 1056 }; 1057 1058 static const typeof(pv_ops) xen_cpu_ops __initconst = { 1059 .cpu = { 1060 .cpuid = xen_cpuid, 1061 1062 .set_debugreg = xen_set_debugreg, 1063 .get_debugreg = xen_get_debugreg, 1064 1065 .read_cr0 = xen_read_cr0, 1066 .write_cr0 = xen_write_cr0, 1067 1068 .write_cr4 = xen_write_cr4, 1069 1070 .wbinvd = native_wbinvd, 1071 1072 .read_msr = xen_read_msr, 1073 .write_msr = xen_write_msr, 1074 1075 .read_msr_safe = xen_read_msr_safe, 1076 .write_msr_safe = xen_write_msr_safe, 1077 1078 .read_pmc = xen_read_pmc, 1079 1080 .load_tr_desc = paravirt_nop, 1081 .set_ldt = xen_set_ldt, 1082 .load_gdt = xen_load_gdt, 1083 .load_idt = xen_load_idt, 1084 .load_tls = xen_load_tls, 1085 .load_gs_index = xen_load_gs_index, 1086 1087 .alloc_ldt = xen_alloc_ldt, 1088 .free_ldt = xen_free_ldt, 1089 1090 .store_tr = xen_store_tr, 1091 1092 .write_ldt_entry = xen_write_ldt_entry, 1093 .write_gdt_entry = xen_write_gdt_entry, 1094 .write_idt_entry = xen_write_idt_entry, 1095 .load_sp0 = xen_load_sp0, 1096 1097 #ifdef CONFIG_X86_IOPL_IOPERM 1098 .invalidate_io_bitmap = xen_invalidate_io_bitmap, 1099 .update_io_bitmap = xen_update_io_bitmap, 1100 #endif 1101 .io_delay = xen_io_delay, 1102 1103 .start_context_switch = paravirt_start_context_switch, 1104 .end_context_switch = xen_end_context_switch, 1105 }, 1106 }; 1107 1108 static void xen_restart(char *msg) 1109 { 1110 xen_reboot(SHUTDOWN_reboot); 1111 } 1112 1113 static void xen_machine_halt(void) 1114 { 1115 xen_reboot(SHUTDOWN_poweroff); 1116 } 1117 1118 static void xen_machine_power_off(void) 1119 { 1120 do_kernel_power_off(); 1121 xen_reboot(SHUTDOWN_poweroff); 1122 } 1123 1124 static void xen_crash_shutdown(struct pt_regs *regs) 1125 { 1126 xen_reboot(SHUTDOWN_crash); 1127 } 1128 1129 static const struct machine_ops xen_machine_ops __initconst = { 1130 .restart = xen_restart, 1131 .halt = xen_machine_halt, 1132 .power_off = xen_machine_power_off, 1133 .shutdown = xen_machine_halt, 1134 .crash_shutdown = xen_crash_shutdown, 1135 .emergency_restart = xen_emergency_restart, 1136 }; 1137 1138 static unsigned char xen_get_nmi_reason(void) 1139 { 1140 unsigned char reason = 0; 1141 1142 /* Construct a value which looks like it came from port 0x61. */ 1143 if (test_bit(_XEN_NMIREASON_io_error, 1144 &HYPERVISOR_shared_info->arch.nmi_reason)) 1145 reason |= NMI_REASON_IOCHK; 1146 if (test_bit(_XEN_NMIREASON_pci_serr, 1147 &HYPERVISOR_shared_info->arch.nmi_reason)) 1148 reason |= NMI_REASON_SERR; 1149 1150 return reason; 1151 } 1152 1153 static void __init xen_boot_params_init_edd(void) 1154 { 1155 #if IS_ENABLED(CONFIG_EDD) 1156 struct xen_platform_op op; 1157 struct edd_info *edd_info; 1158 u32 *mbr_signature; 1159 unsigned nr; 1160 int ret; 1161 1162 edd_info = boot_params.eddbuf; 1163 mbr_signature = boot_params.edd_mbr_sig_buffer; 1164 1165 op.cmd = XENPF_firmware_info; 1166 1167 op.u.firmware_info.type = XEN_FW_DISK_INFO; 1168 for (nr = 0; nr < EDDMAXNR; nr++) { 1169 struct edd_info *info = edd_info + nr; 1170 1171 op.u.firmware_info.index = nr; 1172 info->params.length = sizeof(info->params); 1173 set_xen_guest_handle(op.u.firmware_info.u.disk_info.edd_params, 1174 &info->params); 1175 ret = HYPERVISOR_platform_op(&op); 1176 if (ret) 1177 break; 1178 1179 #define C(x) info->x = op.u.firmware_info.u.disk_info.x 1180 C(device); 1181 C(version); 1182 C(interface_support); 1183 C(legacy_max_cylinder); 1184 C(legacy_max_head); 1185 C(legacy_sectors_per_track); 1186 #undef C 1187 } 1188 boot_params.eddbuf_entries = nr; 1189 1190 op.u.firmware_info.type = XEN_FW_DISK_MBR_SIGNATURE; 1191 for (nr = 0; nr < EDD_MBR_SIG_MAX; nr++) { 1192 op.u.firmware_info.index = nr; 1193 ret = HYPERVISOR_platform_op(&op); 1194 if (ret) 1195 break; 1196 mbr_signature[nr] = op.u.firmware_info.u.disk_mbr_signature.mbr_signature; 1197 } 1198 boot_params.edd_mbr_sig_buf_entries = nr; 1199 #endif 1200 } 1201 1202 /* 1203 * Set up the GDT and segment registers for -fstack-protector. Until 1204 * we do this, we have to be careful not to call any stack-protected 1205 * function, which is most of the kernel. 1206 */ 1207 static void __init xen_setup_gdt(int cpu) 1208 { 1209 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry_boot; 1210 pv_ops.cpu.load_gdt = xen_load_gdt_boot; 1211 1212 switch_to_new_gdt(cpu); 1213 1214 pv_ops.cpu.write_gdt_entry = xen_write_gdt_entry; 1215 pv_ops.cpu.load_gdt = xen_load_gdt; 1216 } 1217 1218 static void __init xen_dom0_set_legacy_features(void) 1219 { 1220 x86_platform.legacy.rtc = 1; 1221 } 1222 1223 static void __init xen_domu_set_legacy_features(void) 1224 { 1225 x86_platform.legacy.rtc = 0; 1226 } 1227 1228 extern void early_xen_iret_patch(void); 1229 1230 /* First C function to be called on Xen boot */ 1231 asmlinkage __visible void __init xen_start_kernel(struct start_info *si) 1232 { 1233 struct physdev_set_iopl set_iopl; 1234 unsigned long initrd_start = 0; 1235 int rc; 1236 1237 if (!si) 1238 return; 1239 1240 clear_bss(); 1241 1242 xen_start_info = si; 1243 1244 __text_gen_insn(&early_xen_iret_patch, 1245 JMP32_INSN_OPCODE, &early_xen_iret_patch, &xen_iret, 1246 JMP32_INSN_SIZE); 1247 1248 xen_domain_type = XEN_PV_DOMAIN; 1249 xen_start_flags = xen_start_info->flags; 1250 1251 xen_setup_features(); 1252 1253 /* Install Xen paravirt ops */ 1254 pv_info = xen_info; 1255 pv_ops.cpu = xen_cpu_ops.cpu; 1256 xen_init_irq_ops(); 1257 1258 /* 1259 * Setup xen_vcpu early because it is needed for 1260 * local_irq_disable(), irqs_disabled(), e.g. in printk(). 1261 * 1262 * Don't do the full vcpu_info placement stuff until we have 1263 * the cpu_possible_mask and a non-dummy shared_info. 1264 */ 1265 xen_vcpu_info_reset(0); 1266 1267 x86_platform.get_nmi_reason = xen_get_nmi_reason; 1268 1269 x86_init.resources.memory_setup = xen_memory_setup; 1270 x86_init.irqs.intr_mode_select = x86_init_noop; 1271 x86_init.irqs.intr_mode_init = x86_init_noop; 1272 x86_init.oem.arch_setup = xen_arch_setup; 1273 x86_init.oem.banner = xen_banner; 1274 x86_init.hyper.init_platform = xen_pv_init_platform; 1275 x86_init.hyper.guest_late_init = xen_pv_guest_late_init; 1276 1277 /* 1278 * Set up some pagetable state before starting to set any ptes. 1279 */ 1280 1281 xen_setup_machphys_mapping(); 1282 xen_init_mmu_ops(); 1283 1284 /* Prevent unwanted bits from being set in PTEs. */ 1285 __supported_pte_mask &= ~_PAGE_GLOBAL; 1286 __default_kernel_pte_mask &= ~_PAGE_GLOBAL; 1287 1288 /* Get mfn list */ 1289 xen_build_dynamic_phys_to_machine(); 1290 1291 /* Work out if we support NX */ 1292 get_cpu_cap(&boot_cpu_data); 1293 x86_configure_nx(); 1294 1295 /* 1296 * Set up kernel GDT and segment registers, mainly so that 1297 * -fstack-protector code can be executed. 1298 */ 1299 xen_setup_gdt(0); 1300 1301 /* Determine virtual and physical address sizes */ 1302 get_cpu_address_sizes(&boot_cpu_data); 1303 1304 /* Let's presume PV guests always boot on vCPU with id 0. */ 1305 per_cpu(xen_vcpu_id, 0) = 0; 1306 1307 idt_setup_early_handler(); 1308 1309 xen_init_capabilities(); 1310 1311 #ifdef CONFIG_X86_LOCAL_APIC 1312 /* 1313 * set up the basic apic ops. 1314 */ 1315 xen_init_apic(); 1316 #endif 1317 1318 machine_ops = xen_machine_ops; 1319 1320 /* 1321 * The only reliable way to retain the initial address of the 1322 * percpu gdt_page is to remember it here, so we can go and 1323 * mark it RW later, when the initial percpu area is freed. 1324 */ 1325 xen_initial_gdt = &per_cpu(gdt_page, 0); 1326 1327 xen_smp_init(); 1328 1329 #ifdef CONFIG_ACPI_NUMA 1330 /* 1331 * The pages we from Xen are not related to machine pages, so 1332 * any NUMA information the kernel tries to get from ACPI will 1333 * be meaningless. Prevent it from trying. 1334 */ 1335 disable_srat(); 1336 #endif 1337 WARN_ON(xen_cpuhp_setup(xen_cpu_up_prepare_pv, xen_cpu_dead_pv)); 1338 1339 local_irq_disable(); 1340 early_boot_irqs_disabled = true; 1341 1342 xen_raw_console_write("mapping kernel into physical memory\n"); 1343 xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, 1344 xen_start_info->nr_pages); 1345 xen_reserve_special_pages(); 1346 1347 /* 1348 * We used to do this in xen_arch_setup, but that is too late 1349 * on AMD were early_cpu_init (run before ->arch_setup()) calls 1350 * early_amd_init which pokes 0xcf8 port. 1351 */ 1352 set_iopl.iopl = 1; 1353 rc = HYPERVISOR_physdev_op(PHYSDEVOP_set_iopl, &set_iopl); 1354 if (rc != 0) 1355 xen_raw_printk("physdev_op failed %d\n", rc); 1356 1357 1358 if (xen_start_info->mod_start) { 1359 if (xen_start_info->flags & SIF_MOD_START_PFN) 1360 initrd_start = PFN_PHYS(xen_start_info->mod_start); 1361 else 1362 initrd_start = __pa(xen_start_info->mod_start); 1363 } 1364 1365 /* Poke various useful things into boot_params */ 1366 boot_params.hdr.type_of_loader = (9 << 4) | 0; 1367 boot_params.hdr.ramdisk_image = initrd_start; 1368 boot_params.hdr.ramdisk_size = xen_start_info->mod_len; 1369 boot_params.hdr.cmd_line_ptr = __pa(xen_start_info->cmd_line); 1370 boot_params.hdr.hardware_subarch = X86_SUBARCH_XEN; 1371 1372 if (!xen_initial_domain()) { 1373 if (pci_xen) 1374 x86_init.pci.arch_init = pci_xen_init; 1375 x86_platform.set_legacy_features = 1376 xen_domu_set_legacy_features; 1377 } else { 1378 const struct dom0_vga_console_info *info = 1379 (void *)((char *)xen_start_info + 1380 xen_start_info->console.dom0.info_off); 1381 struct xen_platform_op op = { 1382 .cmd = XENPF_firmware_info, 1383 .interface_version = XENPF_INTERFACE_VERSION, 1384 .u.firmware_info.type = XEN_FW_KBD_SHIFT_FLAGS, 1385 }; 1386 1387 x86_platform.set_legacy_features = 1388 xen_dom0_set_legacy_features; 1389 xen_init_vga(info, xen_start_info->console.dom0.info_size); 1390 xen_start_info->console.domU.mfn = 0; 1391 xen_start_info->console.domU.evtchn = 0; 1392 1393 if (HYPERVISOR_platform_op(&op) == 0) 1394 boot_params.kbd_status = op.u.firmware_info.u.kbd_shift_flags; 1395 1396 /* Make sure ACS will be enabled */ 1397 pci_request_acs(); 1398 1399 xen_acpi_sleep_register(); 1400 1401 xen_boot_params_init_edd(); 1402 1403 #ifdef CONFIG_ACPI 1404 /* 1405 * Disable selecting "Firmware First mode" for correctable 1406 * memory errors, as this is the duty of the hypervisor to 1407 * decide. 1408 */ 1409 acpi_disable_cmcff = 1; 1410 #endif 1411 } 1412 1413 xen_add_preferred_consoles(); 1414 1415 #ifdef CONFIG_PCI 1416 /* PCI BIOS service won't work from a PV guest. */ 1417 pci_probe &= ~PCI_PROBE_BIOS; 1418 #endif 1419 xen_raw_console_write("about to get started...\n"); 1420 1421 /* We need this for printk timestamps */ 1422 xen_setup_runstate_info(0); 1423 1424 xen_efi_init(&boot_params); 1425 1426 /* Start the world */ 1427 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */ 1428 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1429 } 1430 1431 static int xen_cpu_up_prepare_pv(unsigned int cpu) 1432 { 1433 int rc; 1434 1435 if (per_cpu(xen_vcpu, cpu) == NULL) 1436 return -ENODEV; 1437 1438 xen_setup_timer(cpu); 1439 1440 rc = xen_smp_intr_init(cpu); 1441 if (rc) { 1442 WARN(1, "xen_smp_intr_init() for CPU %d failed: %d\n", 1443 cpu, rc); 1444 return rc; 1445 } 1446 1447 rc = xen_smp_intr_init_pv(cpu); 1448 if (rc) { 1449 WARN(1, "xen_smp_intr_init_pv() for CPU %d failed: %d\n", 1450 cpu, rc); 1451 return rc; 1452 } 1453 1454 return 0; 1455 } 1456 1457 static int xen_cpu_dead_pv(unsigned int cpu) 1458 { 1459 xen_smp_intr_free(cpu); 1460 xen_smp_intr_free_pv(cpu); 1461 1462 xen_teardown_timer(cpu); 1463 1464 return 0; 1465 } 1466 1467 static uint32_t __init xen_platform_pv(void) 1468 { 1469 if (xen_pv_domain()) 1470 return xen_cpuid_base(); 1471 1472 return 0; 1473 } 1474 1475 const __initconst struct hypervisor_x86 x86_hyper_xen_pv = { 1476 .name = "Xen PV", 1477 .detect = xen_platform_pv, 1478 .type = X86_HYPER_XEN_PV, 1479 .runtime.pin_vcpu = xen_pin_vcpu, 1480 .ignore_nopv = true, 1481 }; 1482