1b2441318SGreg Kroah-Hartman# SPDX-License-Identifier: GPL-2.0 2e1cfdc0eSMasahiro Yamada 35c48b108SAl Viromenu "Host processor type and features" 45c48b108SAl Viro 55c48b108SAl Virosource "arch/x86/Kconfig.cpu" 65c48b108SAl Viro 75c48b108SAl Viroendmenu 85c48b108SAl Viro 95c48b108SAl Viroconfig UML_X86 105c48b108SAl Viro def_bool y 11*b62a8486SCatalin Marinas select ARCH_BINFMT_ELF_EXTRA_PHDRS if X86_32 126692531dSAl Viro select DCACHE_WORD_ACCESS 135c48b108SAl Viro 145c48b108SAl Viroconfig 64BIT 15104daea1SMasahiro Yamada bool "64-bit kernel" if "$(SUBARCH)" = "x86" 16104daea1SMasahiro Yamada default "$(SUBARCH)" != "i386" 175c48b108SAl Viro 185c48b108SAl Viroconfig X86_32 195c48b108SAl Viro def_bool !64BIT 20942fa985SYury Norov select ARCH_32BIT_OFF_T 21bbb35efcSRichard Weinberger select ARCH_WANT_IPC_PARSE_VERSION 22786d35d4SDavid Howells select MODULES_USE_ELF_REL 231d4b4b29SAl Viro select CLONE_BACKWARDS 2415ce1f71SAl Viro select OLD_SIGSUSPEND3 255b3eb3adSAl Viro select OLD_SIGACTION 265c48b108SAl Viro 275c48b108SAl Viroconfig X86_64 285c48b108SAl Viro def_bool 64BIT 29786d35d4SDavid Howells select MODULES_USE_ELF_RELA 305c48b108SAl Viro 315c48b108SAl Viroconfig 3_LEVEL_PGTABLES 3201b35ab7SKees Cook bool "Three-level pagetables" if !64BIT 335c48b108SAl Viro default 64BIT 345c48b108SAl Viro help 355c48b108SAl Viro Three-level pagetables will let UML have more than 4G of physical 365c48b108SAl Viro memory. All the memory that can't be mapped directly will be treated 375c48b108SAl Viro as high memory. 385c48b108SAl Viro 395c48b108SAl Viro However, this it experimental on 32-bit architectures, so if unsure say 405c48b108SAl Viro N (on x86-64 it's automatically enabled, instead, as it's safe there). 415c48b108SAl Viro 425c48b108SAl Viroconfig ARCH_HAS_SC_SIGNALS 435c48b108SAl Viro def_bool !64BIT 445c48b108SAl Viro 455c48b108SAl Viroconfig ARCH_REUSE_HOST_VSYSCALL_AREA 465c48b108SAl Viro def_bool !64BIT 475c48b108SAl Viro 485c48b108SAl Viroconfig GENERIC_HWEIGHT 495c48b108SAl Viro def_bool y 50