1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 *
4 *	Trampoline.S	Derived from Setup.S by Linus Torvalds
5 *
6 *	4 Jan 1997 Michael Chastain: changed to gnu as.
7 *	15 Sept 2005 Eric Biederman: 64bit PIC support
8 *
9 *	Entry: CS:IP point to the start of our code, we are
10 *	in real mode with no stack, but the rest of the
11 *	trampoline page to make our stack and everything else
12 *	is a mystery.
13 *
14 *	On entry to trampoline_start, the processor is in real mode
15 *	with 16-bit addressing and 16-bit data.  CS has some value
16 *	and IP is zero.  Thus, data addresses need to be absolute
17 *	(no relocation) and are taken with regard to r_base.
18 *
19 *	With the addition of trampoline_level4_pgt this code can
20 *	now enter a 64bit kernel that lives at arbitrary 64bit
21 *	physical addresses.
22 *
23 *	If you work on this file, check the object module with objdump
24 *	--full-contents --reloc to make sure there are no relocation
25 *	entries.
26 */
27
28#include <linux/linkage.h>
29#include <asm/pgtable_types.h>
30#include <asm/page_types.h>
31#include <asm/msr.h>
32#include <asm/segment.h>
33#include <asm/processor-flags.h>
34#include <asm/realmode.h>
35#include "realmode.h"
36
37	.text
38	.code16
39
40	.balign	PAGE_SIZE
41SYM_CODE_START(trampoline_start)
42	cli			# We should be safe anyway
43	wbinvd
44
45	LJMPW_RM(1f)
461:
47	mov	%cs, %ax	# Code and data in the same place
48	mov	%ax, %ds
49	mov	%ax, %es
50	mov	%ax, %ss
51
52	# Setup stack
53	movl	$rm_stack_end, %esp
54
55	call	verify_cpu		# Verify the cpu supports long mode
56	testl   %eax, %eax		# Check for return code
57	jnz	no_longmode
58
59.Lswitch_to_protected:
60	/*
61	 * GDT tables in non default location kernel can be beyond 16MB and
62	 * lgdt will not be able to load the address as in real mode default
63	 * operand size is 16bit. Use lgdtl instead to force operand size
64	 * to 32 bit.
65	 */
66
67	lidtl	tr_idt	# load idt with 0, 0
68	lgdtl	tr_gdt	# load gdt with whatever is appropriate
69
70	movw	$__KERNEL_DS, %dx	# Data segment descriptor
71
72	# Enable protected mode
73	movl	$X86_CR0_PE, %eax	# protected mode (PE) bit
74	movl	%eax, %cr0		# into protected mode
75
76	# flush prefetch and jump to startup_32
77	ljmpl	$__KERNEL32_CS, $pa_startup_32
78
79no_longmode:
80	hlt
81	jmp no_longmode
82SYM_CODE_END(trampoline_start)
83
84#ifdef CONFIG_AMD_MEM_ENCRYPT
85/* SEV-ES supports non-zero IP for entry points - no alignment needed */
86SYM_CODE_START(sev_es_trampoline_start)
87	cli			# We should be safe anyway
88
89	LJMPW_RM(1f)
901:
91	mov	%cs, %ax	# Code and data in the same place
92	mov	%ax, %ds
93	mov	%ax, %es
94	mov	%ax, %ss
95
96	# Setup stack
97	movl	$rm_stack_end, %esp
98
99	jmp	.Lswitch_to_protected
100SYM_CODE_END(sev_es_trampoline_start)
101#endif	/* CONFIG_AMD_MEM_ENCRYPT */
102
103#include "../kernel/verify_cpu.S"
104
105	.section ".text32","ax"
106	.code32
107	.balign 4
108SYM_CODE_START(startup_32)
109	movl	%edx, %ss
110	addl	$pa_real_mode_base, %esp
111	movl	%edx, %ds
112	movl	%edx, %es
113	movl	%edx, %fs
114	movl	%edx, %gs
115
116	/*
117	 * Check for memory encryption support. This is a safety net in
118	 * case BIOS hasn't done the necessary step of setting the bit in
119	 * the MSR for this AP. If SME is active and we've gotten this far
120	 * then it is safe for us to set the MSR bit and continue. If we
121	 * don't we'll eventually crash trying to execute encrypted
122	 * instructions.
123	 */
124	btl	$TH_FLAGS_SME_ACTIVE_BIT, pa_tr_flags
125	jnc	.Ldone
126	movl	$MSR_K8_SYSCFG, %ecx
127	rdmsr
128	bts	$MSR_K8_SYSCFG_MEM_ENCRYPT_BIT, %eax
129	jc	.Ldone
130
131	/*
132	 * Memory encryption is enabled but the SME enable bit for this
133	 * CPU has has not been set.  It is safe to set it, so do so.
134	 */
135	wrmsr
136.Ldone:
137
138	movl	pa_tr_cr4, %eax
139	movl	%eax, %cr4		# Enable PAE mode
140
141	# Setup trampoline 4 level pagetables
142	movl	$pa_trampoline_pgd, %eax
143	movl	%eax, %cr3
144
145	# Set up EFER
146	movl	pa_tr_efer, %eax
147	movl	pa_tr_efer + 4, %edx
148	movl	$MSR_EFER, %ecx
149	wrmsr
150
151	# Enable paging and in turn activate Long Mode
152	movl	$(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax
153	movl	%eax, %cr0
154
155	/*
156	 * At this point we're in long mode but in 32bit compatibility mode
157	 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
158	 * EFER.LMA = 1). Now we want to jump in 64bit mode, to do that we use
159	 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
160	 */
161	ljmpl	$__KERNEL_CS, $pa_startup_64
162SYM_CODE_END(startup_32)
163
164	.section ".text64","ax"
165	.code64
166	.balign 4
167SYM_CODE_START(startup_64)
168	# Now jump into the kernel using virtual addresses
169	jmpq	*tr_start(%rip)
170SYM_CODE_END(startup_64)
171
172	.section ".rodata","a"
173	# Duplicate the global descriptor table
174	# so the kernel can live anywhere
175	.balign	16
176SYM_DATA_START(tr_gdt)
177	.short	tr_gdt_end - tr_gdt - 1	# gdt limit
178	.long	pa_tr_gdt
179	.short	0
180	.quad	0x00cf9b000000ffff	# __KERNEL32_CS
181	.quad	0x00af9b000000ffff	# __KERNEL_CS
182	.quad	0x00cf93000000ffff	# __KERNEL_DS
183SYM_DATA_END_LABEL(tr_gdt, SYM_L_LOCAL, tr_gdt_end)
184
185	.bss
186	.balign	PAGE_SIZE
187SYM_DATA(trampoline_pgd, .space PAGE_SIZE)
188
189	.balign	8
190SYM_DATA_START(trampoline_header)
191	SYM_DATA_LOCAL(tr_start,	.space 8)
192	SYM_DATA(tr_efer,		.space 8)
193	SYM_DATA(tr_cr4,		.space 4)
194	SYM_DATA(tr_flags,		.space 4)
195SYM_DATA_END(trampoline_header)
196
197#include "trampoline_common.S"
198