1 /* 2 * Suspend support specific for i386/x86-64. 3 * 4 * Distribute under GPLv2 5 * 6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl> 7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz> 8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> 9 */ 10 11 #include <linux/suspend.h> 12 #include <linux/export.h> 13 #include <linux/smp.h> 14 15 #include <asm/pgtable.h> 16 #include <asm/proto.h> 17 #include <asm/mtrr.h> 18 #include <asm/page.h> 19 #include <asm/mce.h> 20 #include <asm/xcr.h> 21 #include <asm/suspend.h> 22 #include <asm/debugreg.h> 23 24 #ifdef CONFIG_X86_32 25 static struct saved_context saved_context; 26 27 unsigned long saved_context_ebx; 28 unsigned long saved_context_esp, saved_context_ebp; 29 unsigned long saved_context_esi, saved_context_edi; 30 unsigned long saved_context_eflags; 31 #else 32 /* CONFIG_X86_64 */ 33 struct saved_context saved_context; 34 #endif 35 36 /** 37 * __save_processor_state - save CPU registers before creating a 38 * hibernation image and before restoring the memory state from it 39 * @ctxt - structure to store the registers contents in 40 * 41 * NOTE: If there is a CPU register the modification of which by the 42 * boot kernel (ie. the kernel used for loading the hibernation image) 43 * might affect the operations of the restored target kernel (ie. the one 44 * saved in the hibernation image), then its contents must be saved by this 45 * function. In other words, if kernel A is hibernated and different 46 * kernel B is used for loading the hibernation image into memory, the 47 * kernel A's __save_processor_state() function must save all registers 48 * needed by kernel A, so that it can operate correctly after the resume 49 * regardless of what kernel B does in the meantime. 50 */ 51 static void __save_processor_state(struct saved_context *ctxt) 52 { 53 #ifdef CONFIG_X86_32 54 mtrr_save_fixed_ranges(NULL); 55 #endif 56 kernel_fpu_begin(); 57 58 /* 59 * descriptor tables 60 */ 61 #ifdef CONFIG_X86_32 62 store_gdt(&ctxt->gdt); 63 store_idt(&ctxt->idt); 64 #else 65 /* CONFIG_X86_64 */ 66 store_gdt((struct desc_ptr *)&ctxt->gdt_limit); 67 store_idt((struct desc_ptr *)&ctxt->idt_limit); 68 #endif 69 store_tr(ctxt->tr); 70 71 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ 72 /* 73 * segment registers 74 */ 75 #ifdef CONFIG_X86_32 76 savesegment(es, ctxt->es); 77 savesegment(fs, ctxt->fs); 78 savesegment(gs, ctxt->gs); 79 savesegment(ss, ctxt->ss); 80 #else 81 /* CONFIG_X86_64 */ 82 asm volatile ("movw %%ds, %0" : "=m" (ctxt->ds)); 83 asm volatile ("movw %%es, %0" : "=m" (ctxt->es)); 84 asm volatile ("movw %%fs, %0" : "=m" (ctxt->fs)); 85 asm volatile ("movw %%gs, %0" : "=m" (ctxt->gs)); 86 asm volatile ("movw %%ss, %0" : "=m" (ctxt->ss)); 87 88 rdmsrl(MSR_FS_BASE, ctxt->fs_base); 89 rdmsrl(MSR_GS_BASE, ctxt->gs_base); 90 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); 91 mtrr_save_fixed_ranges(NULL); 92 93 rdmsrl(MSR_EFER, ctxt->efer); 94 #endif 95 96 /* 97 * control registers 98 */ 99 ctxt->cr0 = read_cr0(); 100 ctxt->cr2 = read_cr2(); 101 ctxt->cr3 = read_cr3(); 102 #ifdef CONFIG_X86_32 103 ctxt->cr4 = read_cr4_safe(); 104 #else 105 /* CONFIG_X86_64 */ 106 ctxt->cr4 = read_cr4(); 107 ctxt->cr8 = read_cr8(); 108 #endif 109 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, 110 &ctxt->misc_enable); 111 } 112 113 /* Needed by apm.c */ 114 void save_processor_state(void) 115 { 116 __save_processor_state(&saved_context); 117 save_sched_clock_state(); 118 } 119 #ifdef CONFIG_X86_32 120 EXPORT_SYMBOL(save_processor_state); 121 #endif 122 123 static void do_fpu_end(void) 124 { 125 /* 126 * Restore FPU regs if necessary. 127 */ 128 kernel_fpu_end(); 129 } 130 131 static void fix_processor_context(void) 132 { 133 int cpu = smp_processor_id(); 134 struct tss_struct *t = &per_cpu(init_tss, cpu); 135 136 set_tss_desc(cpu, t); /* 137 * This just modifies memory; should not be 138 * necessary. But... This is necessary, because 139 * 386 hardware has concept of busy TSS or some 140 * similar stupidity. 141 */ 142 143 #ifdef CONFIG_X86_64 144 get_cpu_gdt_table(cpu)[GDT_ENTRY_TSS].type = 9; 145 146 syscall_init(); /* This sets MSR_*STAR and related */ 147 #endif 148 load_TR_desc(); /* This does ltr */ 149 load_LDT(¤t->active_mm->context); /* This does lldt */ 150 } 151 152 /** 153 * __restore_processor_state - restore the contents of CPU registers saved 154 * by __save_processor_state() 155 * @ctxt - structure to load the registers contents from 156 */ 157 static void __restore_processor_state(struct saved_context *ctxt) 158 { 159 if (ctxt->misc_enable_saved) 160 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); 161 /* 162 * control registers 163 */ 164 /* cr4 was introduced in the Pentium CPU */ 165 #ifdef CONFIG_X86_32 166 if (ctxt->cr4) 167 write_cr4(ctxt->cr4); 168 #else 169 /* CONFIG X86_64 */ 170 wrmsrl(MSR_EFER, ctxt->efer); 171 write_cr8(ctxt->cr8); 172 write_cr4(ctxt->cr4); 173 #endif 174 write_cr3(ctxt->cr3); 175 write_cr2(ctxt->cr2); 176 write_cr0(ctxt->cr0); 177 178 /* 179 * now restore the descriptor tables to their proper values 180 * ltr is done i fix_processor_context(). 181 */ 182 #ifdef CONFIG_X86_32 183 load_gdt(&ctxt->gdt); 184 load_idt(&ctxt->idt); 185 #else 186 /* CONFIG_X86_64 */ 187 load_gdt((const struct desc_ptr *)&ctxt->gdt_limit); 188 load_idt((const struct desc_ptr *)&ctxt->idt_limit); 189 #endif 190 191 /* 192 * segment registers 193 */ 194 #ifdef CONFIG_X86_32 195 loadsegment(es, ctxt->es); 196 loadsegment(fs, ctxt->fs); 197 loadsegment(gs, ctxt->gs); 198 loadsegment(ss, ctxt->ss); 199 200 /* 201 * sysenter MSRs 202 */ 203 if (boot_cpu_has(X86_FEATURE_SEP)) 204 enable_sep_cpu(); 205 #else 206 /* CONFIG_X86_64 */ 207 asm volatile ("movw %0, %%ds" :: "r" (ctxt->ds)); 208 asm volatile ("movw %0, %%es" :: "r" (ctxt->es)); 209 asm volatile ("movw %0, %%fs" :: "r" (ctxt->fs)); 210 load_gs_index(ctxt->gs); 211 asm volatile ("movw %0, %%ss" :: "r" (ctxt->ss)); 212 213 wrmsrl(MSR_FS_BASE, ctxt->fs_base); 214 wrmsrl(MSR_GS_BASE, ctxt->gs_base); 215 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); 216 #endif 217 218 /* 219 * restore XCR0 for xsave capable cpu's. 220 */ 221 if (cpu_has_xsave) 222 xsetbv(XCR_XFEATURE_ENABLED_MASK, pcntxt_mask); 223 224 fix_processor_context(); 225 226 do_fpu_end(); 227 mtrr_bp_restore(); 228 } 229 230 /* Needed by apm.c */ 231 void restore_processor_state(void) 232 { 233 __restore_processor_state(&saved_context); 234 restore_sched_clock_state(); 235 } 236 #ifdef CONFIG_X86_32 237 EXPORT_SYMBOL(restore_processor_state); 238 #endif 239