1 /* 2 * Suspend support specific for i386/x86-64. 3 * 4 * Distribute under GPLv2 5 * 6 * Copyright (c) 2007 Rafael J. Wysocki <rjw@sisk.pl> 7 * Copyright (c) 2002 Pavel Machek <pavel@ucw.cz> 8 * Copyright (c) 2001 Patrick Mochel <mochel@osdl.org> 9 */ 10 11 #include <linux/suspend.h> 12 #include <linux/export.h> 13 #include <linux/smp.h> 14 #include <linux/perf_event.h> 15 #include <linux/tboot.h> 16 17 #include <asm/pgtable.h> 18 #include <asm/proto.h> 19 #include <asm/mtrr.h> 20 #include <asm/page.h> 21 #include <asm/mce.h> 22 #include <asm/suspend.h> 23 #include <asm/fpu/internal.h> 24 #include <asm/debugreg.h> 25 #include <asm/cpu.h> 26 #include <asm/mmu_context.h> 27 #include <linux/dmi.h> 28 29 #ifdef CONFIG_X86_32 30 __visible unsigned long saved_context_ebx; 31 __visible unsigned long saved_context_esp, saved_context_ebp; 32 __visible unsigned long saved_context_esi, saved_context_edi; 33 __visible unsigned long saved_context_eflags; 34 #endif 35 struct saved_context saved_context; 36 37 static void msr_save_context(struct saved_context *ctxt) 38 { 39 struct saved_msr *msr = ctxt->saved_msrs.array; 40 struct saved_msr *end = msr + ctxt->saved_msrs.num; 41 42 while (msr < end) { 43 msr->valid = !rdmsrl_safe(msr->info.msr_no, &msr->info.reg.q); 44 msr++; 45 } 46 } 47 48 static void msr_restore_context(struct saved_context *ctxt) 49 { 50 struct saved_msr *msr = ctxt->saved_msrs.array; 51 struct saved_msr *end = msr + ctxt->saved_msrs.num; 52 53 while (msr < end) { 54 if (msr->valid) 55 wrmsrl(msr->info.msr_no, msr->info.reg.q); 56 msr++; 57 } 58 } 59 60 /** 61 * __save_processor_state - save CPU registers before creating a 62 * hibernation image and before restoring the memory state from it 63 * @ctxt - structure to store the registers contents in 64 * 65 * NOTE: If there is a CPU register the modification of which by the 66 * boot kernel (ie. the kernel used for loading the hibernation image) 67 * might affect the operations of the restored target kernel (ie. the one 68 * saved in the hibernation image), then its contents must be saved by this 69 * function. In other words, if kernel A is hibernated and different 70 * kernel B is used for loading the hibernation image into memory, the 71 * kernel A's __save_processor_state() function must save all registers 72 * needed by kernel A, so that it can operate correctly after the resume 73 * regardless of what kernel B does in the meantime. 74 */ 75 static void __save_processor_state(struct saved_context *ctxt) 76 { 77 #ifdef CONFIG_X86_32 78 mtrr_save_fixed_ranges(NULL); 79 #endif 80 kernel_fpu_begin(); 81 82 /* 83 * descriptor tables 84 */ 85 store_idt(&ctxt->idt); 86 87 /* 88 * We save it here, but restore it only in the hibernate case. 89 * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit 90 * mode in "secondary_startup_64". In 32-bit mode it is done via 91 * 'pmode_gdt' in wakeup_start. 92 */ 93 ctxt->gdt_desc.size = GDT_SIZE - 1; 94 ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id()); 95 96 store_tr(ctxt->tr); 97 98 /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */ 99 /* 100 * segment registers 101 */ 102 #ifdef CONFIG_X86_32_LAZY_GS 103 savesegment(gs, ctxt->gs); 104 #endif 105 #ifdef CONFIG_X86_64 106 savesegment(gs, ctxt->gs); 107 savesegment(fs, ctxt->fs); 108 savesegment(ds, ctxt->ds); 109 savesegment(es, ctxt->es); 110 111 rdmsrl(MSR_FS_BASE, ctxt->fs_base); 112 rdmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); 113 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); 114 mtrr_save_fixed_ranges(NULL); 115 116 rdmsrl(MSR_EFER, ctxt->efer); 117 #endif 118 119 /* 120 * control registers 121 */ 122 ctxt->cr0 = read_cr0(); 123 ctxt->cr2 = read_cr2(); 124 ctxt->cr3 = __read_cr3(); 125 ctxt->cr4 = __read_cr4(); 126 #ifdef CONFIG_X86_64 127 ctxt->cr8 = read_cr8(); 128 #endif 129 ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, 130 &ctxt->misc_enable); 131 msr_save_context(ctxt); 132 } 133 134 /* Needed by apm.c */ 135 void save_processor_state(void) 136 { 137 __save_processor_state(&saved_context); 138 x86_platform.save_sched_clock_state(); 139 } 140 #ifdef CONFIG_X86_32 141 EXPORT_SYMBOL(save_processor_state); 142 #endif 143 144 static void do_fpu_end(void) 145 { 146 /* 147 * Restore FPU regs if necessary. 148 */ 149 kernel_fpu_end(); 150 } 151 152 static void fix_processor_context(void) 153 { 154 int cpu = smp_processor_id(); 155 #ifdef CONFIG_X86_64 156 struct desc_struct *desc = get_cpu_gdt_rw(cpu); 157 tss_desc tss; 158 #endif 159 160 /* 161 * We need to reload TR, which requires that we change the 162 * GDT entry to indicate "available" first. 163 * 164 * XXX: This could probably all be replaced by a call to 165 * force_reload_TR(). 166 */ 167 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss); 168 169 #ifdef CONFIG_X86_64 170 memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc)); 171 tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */ 172 write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS); 173 174 syscall_init(); /* This sets MSR_*STAR and related */ 175 #else 176 if (boot_cpu_has(X86_FEATURE_SEP)) 177 enable_sep_cpu(); 178 #endif 179 load_TR_desc(); /* This does ltr */ 180 load_mm_ldt(current->active_mm); /* This does lldt */ 181 initialize_tlbstate_and_flush(); 182 183 fpu__resume_cpu(); 184 185 /* The processor is back on the direct GDT, load back the fixmap */ 186 load_fixmap_gdt(cpu); 187 } 188 189 /** 190 * __restore_processor_state - restore the contents of CPU registers saved 191 * by __save_processor_state() 192 * @ctxt - structure to load the registers contents from 193 * 194 * The asm code that gets us here will have restored a usable GDT, although 195 * it will be pointing to the wrong alias. 196 */ 197 static void notrace __restore_processor_state(struct saved_context *ctxt) 198 { 199 if (ctxt->misc_enable_saved) 200 wrmsrl(MSR_IA32_MISC_ENABLE, ctxt->misc_enable); 201 /* 202 * control registers 203 */ 204 /* cr4 was introduced in the Pentium CPU */ 205 #ifdef CONFIG_X86_32 206 if (ctxt->cr4) 207 __write_cr4(ctxt->cr4); 208 #else 209 /* CONFIG X86_64 */ 210 wrmsrl(MSR_EFER, ctxt->efer); 211 write_cr8(ctxt->cr8); 212 __write_cr4(ctxt->cr4); 213 #endif 214 write_cr3(ctxt->cr3); 215 write_cr2(ctxt->cr2); 216 write_cr0(ctxt->cr0); 217 218 /* Restore the IDT. */ 219 load_idt(&ctxt->idt); 220 221 /* 222 * Just in case the asm code got us here with the SS, DS, or ES 223 * out of sync with the GDT, update them. 224 */ 225 loadsegment(ss, __KERNEL_DS); 226 loadsegment(ds, __USER_DS); 227 loadsegment(es, __USER_DS); 228 229 /* 230 * Restore percpu access. Percpu access can happen in exception 231 * handlers or in complicated helpers like load_gs_index(). 232 */ 233 #ifdef CONFIG_X86_64 234 wrmsrl(MSR_GS_BASE, ctxt->kernelmode_gs_base); 235 #else 236 loadsegment(fs, __KERNEL_PERCPU); 237 loadsegment(gs, __KERNEL_STACK_CANARY); 238 #endif 239 240 /* Restore the TSS, RO GDT, LDT, and usermode-relevant MSRs. */ 241 fix_processor_context(); 242 243 /* 244 * Now that we have descriptor tables fully restored and working 245 * exception handling, restore the usermode segments. 246 */ 247 #ifdef CONFIG_X86_64 248 loadsegment(ds, ctxt->es); 249 loadsegment(es, ctxt->es); 250 loadsegment(fs, ctxt->fs); 251 load_gs_index(ctxt->gs); 252 253 /* 254 * Restore FSBASE and GSBASE after restoring the selectors, since 255 * restoring the selectors clobbers the bases. Keep in mind 256 * that MSR_KERNEL_GS_BASE is horribly misnamed. 257 */ 258 wrmsrl(MSR_FS_BASE, ctxt->fs_base); 259 wrmsrl(MSR_KERNEL_GS_BASE, ctxt->usermode_gs_base); 260 #elif defined(CONFIG_X86_32_LAZY_GS) 261 loadsegment(gs, ctxt->gs); 262 #endif 263 264 do_fpu_end(); 265 tsc_verify_tsc_adjust(true); 266 x86_platform.restore_sched_clock_state(); 267 mtrr_bp_restore(); 268 perf_restore_debug_store(); 269 msr_restore_context(ctxt); 270 } 271 272 /* Needed by apm.c */ 273 void notrace restore_processor_state(void) 274 { 275 __restore_processor_state(&saved_context); 276 } 277 #ifdef CONFIG_X86_32 278 EXPORT_SYMBOL(restore_processor_state); 279 #endif 280 281 #if defined(CONFIG_HIBERNATION) && defined(CONFIG_HOTPLUG_CPU) 282 static void resume_play_dead(void) 283 { 284 play_dead_common(); 285 tboot_shutdown(TB_SHUTDOWN_WFS); 286 hlt_play_dead(); 287 } 288 289 int hibernate_resume_nonboot_cpu_disable(void) 290 { 291 void (*play_dead)(void) = smp_ops.play_dead; 292 int ret; 293 294 /* 295 * Ensure that MONITOR/MWAIT will not be used in the "play dead" loop 296 * during hibernate image restoration, because it is likely that the 297 * monitored address will be actually written to at that time and then 298 * the "dead" CPU will attempt to execute instructions again, but the 299 * address in its instruction pointer may not be possible to resolve 300 * any more at that point (the page tables used by it previously may 301 * have been overwritten by hibernate image data). 302 */ 303 smp_ops.play_dead = resume_play_dead; 304 ret = disable_nonboot_cpus(); 305 smp_ops.play_dead = play_dead; 306 return ret; 307 } 308 #endif 309 310 /* 311 * When bsp_check() is called in hibernate and suspend, cpu hotplug 312 * is disabled already. So it's unnessary to handle race condition between 313 * cpumask query and cpu hotplug. 314 */ 315 static int bsp_check(void) 316 { 317 if (cpumask_first(cpu_online_mask) != 0) { 318 pr_warn("CPU0 is offline.\n"); 319 return -ENODEV; 320 } 321 322 return 0; 323 } 324 325 static int bsp_pm_callback(struct notifier_block *nb, unsigned long action, 326 void *ptr) 327 { 328 int ret = 0; 329 330 switch (action) { 331 case PM_SUSPEND_PREPARE: 332 case PM_HIBERNATION_PREPARE: 333 ret = bsp_check(); 334 break; 335 #ifdef CONFIG_DEBUG_HOTPLUG_CPU0 336 case PM_RESTORE_PREPARE: 337 /* 338 * When system resumes from hibernation, online CPU0 because 339 * 1. it's required for resume and 340 * 2. the CPU was online before hibernation 341 */ 342 if (!cpu_online(0)) 343 _debug_hotplug_cpu(0, 1); 344 break; 345 case PM_POST_RESTORE: 346 /* 347 * When a resume really happens, this code won't be called. 348 * 349 * This code is called only when user space hibernation software 350 * prepares for snapshot device during boot time. So we just 351 * call _debug_hotplug_cpu() to restore to CPU0's state prior to 352 * preparing the snapshot device. 353 * 354 * This works for normal boot case in our CPU0 hotplug debug 355 * mode, i.e. CPU0 is offline and user mode hibernation 356 * software initializes during boot time. 357 * 358 * If CPU0 is online and user application accesses snapshot 359 * device after boot time, this will offline CPU0 and user may 360 * see different CPU0 state before and after accessing 361 * the snapshot device. But hopefully this is not a case when 362 * user debugging CPU0 hotplug. Even if users hit this case, 363 * they can easily online CPU0 back. 364 * 365 * To simplify this debug code, we only consider normal boot 366 * case. Otherwise we need to remember CPU0's state and restore 367 * to that state and resolve racy conditions etc. 368 */ 369 _debug_hotplug_cpu(0, 0); 370 break; 371 #endif 372 default: 373 break; 374 } 375 return notifier_from_errno(ret); 376 } 377 378 static int __init bsp_pm_check_init(void) 379 { 380 /* 381 * Set this bsp_pm_callback as lower priority than 382 * cpu_hotplug_pm_callback. So cpu_hotplug_pm_callback will be called 383 * earlier to disable cpu hotplug before bsp online check. 384 */ 385 pm_notifier(bsp_pm_callback, -INT_MAX); 386 return 0; 387 } 388 389 core_initcall(bsp_pm_check_init); 390 391 static int msr_init_context(const u32 *msr_id, const int total_num) 392 { 393 int i = 0; 394 struct saved_msr *msr_array; 395 396 if (saved_context.saved_msrs.array || saved_context.saved_msrs.num > 0) { 397 pr_err("x86/pm: MSR quirk already applied, please check your DMI match table.\n"); 398 return -EINVAL; 399 } 400 401 msr_array = kmalloc_array(total_num, sizeof(struct saved_msr), GFP_KERNEL); 402 if (!msr_array) { 403 pr_err("x86/pm: Can not allocate memory to save/restore MSRs during suspend.\n"); 404 return -ENOMEM; 405 } 406 407 for (i = 0; i < total_num; i++) { 408 msr_array[i].info.msr_no = msr_id[i]; 409 msr_array[i].valid = false; 410 msr_array[i].info.reg.q = 0; 411 } 412 saved_context.saved_msrs.num = total_num; 413 saved_context.saved_msrs.array = msr_array; 414 415 return 0; 416 } 417 418 /* 419 * The following section is a quirk framework for problematic BIOSen: 420 * Sometimes MSRs are modified by the BIOSen after suspended to 421 * RAM, this might cause unexpected behavior after wakeup. 422 * Thus we save/restore these specified MSRs across suspend/resume 423 * in order to work around it. 424 * 425 * For any further problematic BIOSen/platforms, 426 * please add your own function similar to msr_initialize_bdw. 427 */ 428 static int msr_initialize_bdw(const struct dmi_system_id *d) 429 { 430 /* Add any extra MSR ids into this array. */ 431 u32 bdw_msr_id[] = { MSR_IA32_THERM_CONTROL }; 432 433 pr_info("x86/pm: %s detected, MSR saving is needed during suspending.\n", d->ident); 434 return msr_init_context(bdw_msr_id, ARRAY_SIZE(bdw_msr_id)); 435 } 436 437 static const struct dmi_system_id msr_save_dmi_table[] = { 438 { 439 .callback = msr_initialize_bdw, 440 .ident = "BROADWELL BDX_EP", 441 .matches = { 442 DMI_MATCH(DMI_PRODUCT_NAME, "GRANTLEY"), 443 DMI_MATCH(DMI_PRODUCT_VERSION, "E63448-400"), 444 }, 445 }, 446 {} 447 }; 448 449 static int pm_check_save_msr(void) 450 { 451 dmi_check_system(msr_save_dmi_table); 452 return 0; 453 } 454 455 device_initcall(pm_check_save_msr); 456