1 /* 2 * SGI RTC clock/timer routines. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 * Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved. 19 * Copyright (c) Dimitri Sivanich 20 */ 21 #include <linux/clockchips.h> 22 #include <linux/slab.h> 23 24 #include <asm/uv/uv_mmrs.h> 25 #include <asm/uv/uv_hub.h> 26 #include <asm/uv/bios.h> 27 #include <asm/uv/uv.h> 28 #include <asm/apic.h> 29 #include <asm/cpu.h> 30 31 #define RTC_NAME "sgi_rtc" 32 33 static cycle_t uv_read_rtc(struct clocksource *cs); 34 static int uv_rtc_next_event(unsigned long, struct clock_event_device *); 35 static void uv_rtc_timer_setup(enum clock_event_mode, 36 struct clock_event_device *); 37 38 static struct clocksource clocksource_uv = { 39 .name = RTC_NAME, 40 .rating = 299, 41 .read = uv_read_rtc, 42 .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK, 43 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 44 }; 45 46 static struct clock_event_device clock_event_device_uv = { 47 .name = RTC_NAME, 48 .features = CLOCK_EVT_FEAT_ONESHOT, 49 .shift = 20, 50 .rating = 400, 51 .irq = -1, 52 .set_next_event = uv_rtc_next_event, 53 .set_mode = uv_rtc_timer_setup, 54 .event_handler = NULL, 55 }; 56 57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); 58 59 /* There is one of these allocated per node */ 60 struct uv_rtc_timer_head { 61 spinlock_t lock; 62 /* next cpu waiting for timer, local node relative: */ 63 int next_cpu; 64 /* number of cpus on this node: */ 65 int ncpus; 66 struct { 67 int lcpu; /* systemwide logical cpu number */ 68 u64 expires; /* next timer expiration for this cpu */ 69 } cpu[1]; 70 }; 71 72 /* 73 * Access to uv_rtc_timer_head via blade id. 74 */ 75 static struct uv_rtc_timer_head **blade_info __read_mostly; 76 77 static int uv_rtc_evt_enable; 78 79 /* 80 * Hardware interface routines 81 */ 82 83 /* Send IPIs to another node */ 84 static void uv_rtc_send_IPI(int cpu) 85 { 86 unsigned long apicid, val; 87 int pnode; 88 89 apicid = cpu_physical_id(cpu); 90 pnode = uv_apicid_to_pnode(apicid); 91 apicid |= uv_apicid_hibits; 92 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 93 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 94 (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT); 95 96 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 97 } 98 99 /* Check for an RTC interrupt pending */ 100 static int uv_intr_pending(int pnode) 101 { 102 if (is_uv1_hub()) 103 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & 104 UV1H_EVENT_OCCURRED0_RTC1_MASK; 105 else if (is_uvx_hub()) 106 return uv_read_global_mmr64(pnode, UVXH_EVENT_OCCURRED2) & 107 UVXH_EVENT_OCCURRED2_RTC_1_MASK; 108 return 0; 109 } 110 111 /* Setup interrupt and return non-zero if early expiration occurred. */ 112 static int uv_setup_intr(int cpu, u64 expires) 113 { 114 u64 val; 115 unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits; 116 int pnode = uv_cpu_to_pnode(cpu); 117 118 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, 119 UVH_RTC1_INT_CONFIG_M_MASK); 120 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); 121 122 if (is_uv1_hub()) 123 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, 124 UV1H_EVENT_OCCURRED0_RTC1_MASK); 125 else 126 uv_write_global_mmr64(pnode, UVXH_EVENT_OCCURRED2_ALIAS, 127 UVXH_EVENT_OCCURRED2_RTC_1_MASK); 128 129 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | 130 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT); 131 132 /* Set configuration */ 133 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val); 134 /* Initialize comparator value */ 135 uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); 136 137 if (uv_read_rtc(NULL) <= expires) 138 return 0; 139 140 return !uv_intr_pending(pnode); 141 } 142 143 /* 144 * Per-cpu timer tracking routines 145 */ 146 147 static __init void uv_rtc_deallocate_timers(void) 148 { 149 int bid; 150 151 for_each_possible_blade(bid) { 152 kfree(blade_info[bid]); 153 } 154 kfree(blade_info); 155 } 156 157 /* Allocate per-node list of cpu timer expiration times. */ 158 static __init int uv_rtc_allocate_timers(void) 159 { 160 int cpu; 161 162 blade_info = kzalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL); 163 if (!blade_info) 164 return -ENOMEM; 165 166 for_each_present_cpu(cpu) { 167 int nid = cpu_to_node(cpu); 168 int bid = uv_cpu_to_blade_id(cpu); 169 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 170 struct uv_rtc_timer_head *head = blade_info[bid]; 171 172 if (!head) { 173 head = kmalloc_node(sizeof(struct uv_rtc_timer_head) + 174 (uv_blade_nr_possible_cpus(bid) * 175 2 * sizeof(u64)), 176 GFP_KERNEL, nid); 177 if (!head) { 178 uv_rtc_deallocate_timers(); 179 return -ENOMEM; 180 } 181 spin_lock_init(&head->lock); 182 head->ncpus = uv_blade_nr_possible_cpus(bid); 183 head->next_cpu = -1; 184 blade_info[bid] = head; 185 } 186 187 head->cpu[bcpu].lcpu = cpu; 188 head->cpu[bcpu].expires = ULLONG_MAX; 189 } 190 191 return 0; 192 } 193 194 /* Find and set the next expiring timer. */ 195 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode) 196 { 197 u64 lowest = ULLONG_MAX; 198 int c, bcpu = -1; 199 200 head->next_cpu = -1; 201 for (c = 0; c < head->ncpus; c++) { 202 u64 exp = head->cpu[c].expires; 203 if (exp < lowest) { 204 bcpu = c; 205 lowest = exp; 206 } 207 } 208 if (bcpu >= 0) { 209 head->next_cpu = bcpu; 210 c = head->cpu[bcpu].lcpu; 211 if (uv_setup_intr(c, lowest)) 212 /* If we didn't set it up in time, trigger */ 213 uv_rtc_send_IPI(c); 214 } else { 215 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, 216 UVH_RTC1_INT_CONFIG_M_MASK); 217 } 218 } 219 220 /* 221 * Set expiration time for current cpu. 222 * 223 * Returns 1 if we missed the expiration time. 224 */ 225 static int uv_rtc_set_timer(int cpu, u64 expires) 226 { 227 int pnode = uv_cpu_to_pnode(cpu); 228 int bid = uv_cpu_to_blade_id(cpu); 229 struct uv_rtc_timer_head *head = blade_info[bid]; 230 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 231 u64 *t = &head->cpu[bcpu].expires; 232 unsigned long flags; 233 int next_cpu; 234 235 spin_lock_irqsave(&head->lock, flags); 236 237 next_cpu = head->next_cpu; 238 *t = expires; 239 240 /* Will this one be next to go off? */ 241 if (next_cpu < 0 || bcpu == next_cpu || 242 expires < head->cpu[next_cpu].expires) { 243 head->next_cpu = bcpu; 244 if (uv_setup_intr(cpu, expires)) { 245 *t = ULLONG_MAX; 246 uv_rtc_find_next_timer(head, pnode); 247 spin_unlock_irqrestore(&head->lock, flags); 248 return -ETIME; 249 } 250 } 251 252 spin_unlock_irqrestore(&head->lock, flags); 253 return 0; 254 } 255 256 /* 257 * Unset expiration time for current cpu. 258 * 259 * Returns 1 if this timer was pending. 260 */ 261 static int uv_rtc_unset_timer(int cpu, int force) 262 { 263 int pnode = uv_cpu_to_pnode(cpu); 264 int bid = uv_cpu_to_blade_id(cpu); 265 struct uv_rtc_timer_head *head = blade_info[bid]; 266 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 267 u64 *t = &head->cpu[bcpu].expires; 268 unsigned long flags; 269 int rc = 0; 270 271 spin_lock_irqsave(&head->lock, flags); 272 273 if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force) 274 rc = 1; 275 276 if (rc) { 277 *t = ULLONG_MAX; 278 /* Was the hardware setup for this timer? */ 279 if (head->next_cpu == bcpu) 280 uv_rtc_find_next_timer(head, pnode); 281 } 282 283 spin_unlock_irqrestore(&head->lock, flags); 284 285 return rc; 286 } 287 288 289 /* 290 * Kernel interface routines. 291 */ 292 293 /* 294 * Read the RTC. 295 * 296 * Starting with HUB rev 2.0, the UV RTC register is replicated across all 297 * cachelines of it's own page. This allows faster simultaneous reads 298 * from a given socket. 299 */ 300 static cycle_t uv_read_rtc(struct clocksource *cs) 301 { 302 unsigned long offset; 303 304 if (uv_get_min_hub_revision_id() == 1) 305 offset = 0; 306 else 307 offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE; 308 309 return (cycle_t)uv_read_local_mmr(UVH_RTC | offset); 310 } 311 312 /* 313 * Program the next event, relative to now 314 */ 315 static int uv_rtc_next_event(unsigned long delta, 316 struct clock_event_device *ced) 317 { 318 int ced_cpu = cpumask_first(ced->cpumask); 319 320 return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL)); 321 } 322 323 /* 324 * Setup the RTC timer in oneshot mode 325 */ 326 static void uv_rtc_timer_setup(enum clock_event_mode mode, 327 struct clock_event_device *evt) 328 { 329 int ced_cpu = cpumask_first(evt->cpumask); 330 331 switch (mode) { 332 case CLOCK_EVT_MODE_PERIODIC: 333 case CLOCK_EVT_MODE_ONESHOT: 334 case CLOCK_EVT_MODE_RESUME: 335 /* Nothing to do here yet */ 336 break; 337 case CLOCK_EVT_MODE_UNUSED: 338 case CLOCK_EVT_MODE_SHUTDOWN: 339 uv_rtc_unset_timer(ced_cpu, 1); 340 break; 341 } 342 } 343 344 static void uv_rtc_interrupt(void) 345 { 346 int cpu = smp_processor_id(); 347 struct clock_event_device *ced = &per_cpu(cpu_ced, cpu); 348 349 if (!ced || !ced->event_handler) 350 return; 351 352 if (uv_rtc_unset_timer(cpu, 0) != 1) 353 return; 354 355 ced->event_handler(ced); 356 } 357 358 static int __init uv_enable_evt_rtc(char *str) 359 { 360 uv_rtc_evt_enable = 1; 361 362 return 1; 363 } 364 __setup("uvrtcevt", uv_enable_evt_rtc); 365 366 static __init void uv_rtc_register_clockevents(struct work_struct *dummy) 367 { 368 struct clock_event_device *ced = &__get_cpu_var(cpu_ced); 369 370 *ced = clock_event_device_uv; 371 ced->cpumask = cpumask_of(smp_processor_id()); 372 clockevents_register_device(ced); 373 } 374 375 static __init int uv_rtc_setup_clock(void) 376 { 377 int rc; 378 379 if (!is_uv_system()) 380 return -ENODEV; 381 382 rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second); 383 if (rc) 384 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc); 385 else 386 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n", 387 sn_rtc_cycles_per_second/(unsigned long)1E6); 388 389 if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback) 390 return rc; 391 392 /* Setup and register clockevents */ 393 rc = uv_rtc_allocate_timers(); 394 if (rc) 395 goto error; 396 397 x86_platform_ipi_callback = uv_rtc_interrupt; 398 399 clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second, 400 NSEC_PER_SEC, clock_event_device_uv.shift); 401 402 clock_event_device_uv.min_delta_ns = NSEC_PER_SEC / 403 sn_rtc_cycles_per_second; 404 405 clock_event_device_uv.max_delta_ns = clocksource_uv.mask * 406 (NSEC_PER_SEC / sn_rtc_cycles_per_second); 407 408 rc = schedule_on_each_cpu(uv_rtc_register_clockevents); 409 if (rc) { 410 x86_platform_ipi_callback = NULL; 411 uv_rtc_deallocate_timers(); 412 goto error; 413 } 414 415 printk(KERN_INFO "UV RTC clockevents registered\n"); 416 417 return 0; 418 419 error: 420 clocksource_unregister(&clocksource_uv); 421 printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc); 422 423 return rc; 424 } 425 arch_initcall(uv_rtc_setup_clock); 426