1 /* 2 * SGI RTC clock/timer routines. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 17 * 18 * Copyright (c) 2009-2013 Silicon Graphics, Inc. All Rights Reserved. 19 * Copyright (c) Dimitri Sivanich 20 */ 21 #include <linux/clockchips.h> 22 #include <linux/slab.h> 23 24 #include <asm/uv/uv_mmrs.h> 25 #include <asm/uv/uv_hub.h> 26 #include <asm/uv/bios.h> 27 #include <asm/uv/uv.h> 28 #include <asm/apic.h> 29 #include <asm/cpu.h> 30 31 #define RTC_NAME "sgi_rtc" 32 33 static cycle_t uv_read_rtc(struct clocksource *cs); 34 static int uv_rtc_next_event(unsigned long, struct clock_event_device *); 35 static void uv_rtc_timer_setup(enum clock_event_mode, 36 struct clock_event_device *); 37 38 static struct clocksource clocksource_uv = { 39 .name = RTC_NAME, 40 .rating = 299, 41 .read = uv_read_rtc, 42 .mask = (cycle_t)UVH_RTC_REAL_TIME_CLOCK_MASK, 43 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 44 }; 45 46 static struct clock_event_device clock_event_device_uv = { 47 .name = RTC_NAME, 48 .features = CLOCK_EVT_FEAT_ONESHOT, 49 .shift = 20, 50 .rating = 400, 51 .irq = -1, 52 .set_next_event = uv_rtc_next_event, 53 .set_mode = uv_rtc_timer_setup, 54 .event_handler = NULL, 55 }; 56 57 static DEFINE_PER_CPU(struct clock_event_device, cpu_ced); 58 59 /* There is one of these allocated per node */ 60 struct uv_rtc_timer_head { 61 spinlock_t lock; 62 /* next cpu waiting for timer, local node relative: */ 63 int next_cpu; 64 /* number of cpus on this node: */ 65 int ncpus; 66 struct { 67 int lcpu; /* systemwide logical cpu number */ 68 u64 expires; /* next timer expiration for this cpu */ 69 } cpu[1]; 70 }; 71 72 /* 73 * Access to uv_rtc_timer_head via blade id. 74 */ 75 static struct uv_rtc_timer_head **blade_info __read_mostly; 76 77 static int uv_rtc_evt_enable; 78 79 /* 80 * Hardware interface routines 81 */ 82 83 /* Send IPIs to another node */ 84 static void uv_rtc_send_IPI(int cpu) 85 { 86 unsigned long apicid, val; 87 int pnode; 88 89 apicid = cpu_physical_id(cpu); 90 pnode = uv_apicid_to_pnode(apicid); 91 apicid |= uv_apicid_hibits; 92 val = (1UL << UVH_IPI_INT_SEND_SHFT) | 93 (apicid << UVH_IPI_INT_APIC_ID_SHFT) | 94 (X86_PLATFORM_IPI_VECTOR << UVH_IPI_INT_VECTOR_SHFT); 95 96 uv_write_global_mmr64(pnode, UVH_IPI_INT, val); 97 } 98 99 /* Check for an RTC interrupt pending */ 100 static int uv_intr_pending(int pnode) 101 { 102 if (is_uv1_hub()) 103 return uv_read_global_mmr64(pnode, UVH_EVENT_OCCURRED0) & 104 UV1H_EVENT_OCCURRED0_RTC1_MASK; 105 else if (is_uvx_hub()) 106 return uv_read_global_mmr64(pnode, UVXH_EVENT_OCCURRED2) & 107 UVXH_EVENT_OCCURRED2_RTC_1_MASK; 108 return 0; 109 } 110 111 /* Setup interrupt and return non-zero if early expiration occurred. */ 112 static int uv_setup_intr(int cpu, u64 expires) 113 { 114 u64 val; 115 unsigned long apicid = cpu_physical_id(cpu) | uv_apicid_hibits; 116 int pnode = uv_cpu_to_pnode(cpu); 117 118 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, 119 UVH_RTC1_INT_CONFIG_M_MASK); 120 uv_write_global_mmr64(pnode, UVH_INT_CMPB, -1L); 121 122 if (is_uv1_hub()) 123 uv_write_global_mmr64(pnode, UVH_EVENT_OCCURRED0_ALIAS, 124 UV1H_EVENT_OCCURRED0_RTC1_MASK); 125 else 126 uv_write_global_mmr64(pnode, UVXH_EVENT_OCCURRED2_ALIAS, 127 UVXH_EVENT_OCCURRED2_RTC_1_MASK); 128 129 val = (X86_PLATFORM_IPI_VECTOR << UVH_RTC1_INT_CONFIG_VECTOR_SHFT) | 130 ((u64)apicid << UVH_RTC1_INT_CONFIG_APIC_ID_SHFT); 131 132 /* Set configuration */ 133 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, val); 134 /* Initialize comparator value */ 135 uv_write_global_mmr64(pnode, UVH_INT_CMPB, expires); 136 137 if (uv_read_rtc(NULL) <= expires) 138 return 0; 139 140 return !uv_intr_pending(pnode); 141 } 142 143 /* 144 * Per-cpu timer tracking routines 145 */ 146 147 static __init void uv_rtc_deallocate_timers(void) 148 { 149 int bid; 150 151 for_each_possible_blade(bid) { 152 kfree(blade_info[bid]); 153 } 154 kfree(blade_info); 155 } 156 157 /* Allocate per-node list of cpu timer expiration times. */ 158 static __init int uv_rtc_allocate_timers(void) 159 { 160 int cpu; 161 162 blade_info = kmalloc(uv_possible_blades * sizeof(void *), GFP_KERNEL); 163 if (!blade_info) 164 return -ENOMEM; 165 memset(blade_info, 0, uv_possible_blades * sizeof(void *)); 166 167 for_each_present_cpu(cpu) { 168 int nid = cpu_to_node(cpu); 169 int bid = uv_cpu_to_blade_id(cpu); 170 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 171 struct uv_rtc_timer_head *head = blade_info[bid]; 172 173 if (!head) { 174 head = kmalloc_node(sizeof(struct uv_rtc_timer_head) + 175 (uv_blade_nr_possible_cpus(bid) * 176 2 * sizeof(u64)), 177 GFP_KERNEL, nid); 178 if (!head) { 179 uv_rtc_deallocate_timers(); 180 return -ENOMEM; 181 } 182 spin_lock_init(&head->lock); 183 head->ncpus = uv_blade_nr_possible_cpus(bid); 184 head->next_cpu = -1; 185 blade_info[bid] = head; 186 } 187 188 head->cpu[bcpu].lcpu = cpu; 189 head->cpu[bcpu].expires = ULLONG_MAX; 190 } 191 192 return 0; 193 } 194 195 /* Find and set the next expiring timer. */ 196 static void uv_rtc_find_next_timer(struct uv_rtc_timer_head *head, int pnode) 197 { 198 u64 lowest = ULLONG_MAX; 199 int c, bcpu = -1; 200 201 head->next_cpu = -1; 202 for (c = 0; c < head->ncpus; c++) { 203 u64 exp = head->cpu[c].expires; 204 if (exp < lowest) { 205 bcpu = c; 206 lowest = exp; 207 } 208 } 209 if (bcpu >= 0) { 210 head->next_cpu = bcpu; 211 c = head->cpu[bcpu].lcpu; 212 if (uv_setup_intr(c, lowest)) 213 /* If we didn't set it up in time, trigger */ 214 uv_rtc_send_IPI(c); 215 } else { 216 uv_write_global_mmr64(pnode, UVH_RTC1_INT_CONFIG, 217 UVH_RTC1_INT_CONFIG_M_MASK); 218 } 219 } 220 221 /* 222 * Set expiration time for current cpu. 223 * 224 * Returns 1 if we missed the expiration time. 225 */ 226 static int uv_rtc_set_timer(int cpu, u64 expires) 227 { 228 int pnode = uv_cpu_to_pnode(cpu); 229 int bid = uv_cpu_to_blade_id(cpu); 230 struct uv_rtc_timer_head *head = blade_info[bid]; 231 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 232 u64 *t = &head->cpu[bcpu].expires; 233 unsigned long flags; 234 int next_cpu; 235 236 spin_lock_irqsave(&head->lock, flags); 237 238 next_cpu = head->next_cpu; 239 *t = expires; 240 241 /* Will this one be next to go off? */ 242 if (next_cpu < 0 || bcpu == next_cpu || 243 expires < head->cpu[next_cpu].expires) { 244 head->next_cpu = bcpu; 245 if (uv_setup_intr(cpu, expires)) { 246 *t = ULLONG_MAX; 247 uv_rtc_find_next_timer(head, pnode); 248 spin_unlock_irqrestore(&head->lock, flags); 249 return -ETIME; 250 } 251 } 252 253 spin_unlock_irqrestore(&head->lock, flags); 254 return 0; 255 } 256 257 /* 258 * Unset expiration time for current cpu. 259 * 260 * Returns 1 if this timer was pending. 261 */ 262 static int uv_rtc_unset_timer(int cpu, int force) 263 { 264 int pnode = uv_cpu_to_pnode(cpu); 265 int bid = uv_cpu_to_blade_id(cpu); 266 struct uv_rtc_timer_head *head = blade_info[bid]; 267 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 268 u64 *t = &head->cpu[bcpu].expires; 269 unsigned long flags; 270 int rc = 0; 271 272 spin_lock_irqsave(&head->lock, flags); 273 274 if ((head->next_cpu == bcpu && uv_read_rtc(NULL) >= *t) || force) 275 rc = 1; 276 277 if (rc) { 278 *t = ULLONG_MAX; 279 /* Was the hardware setup for this timer? */ 280 if (head->next_cpu == bcpu) 281 uv_rtc_find_next_timer(head, pnode); 282 } 283 284 spin_unlock_irqrestore(&head->lock, flags); 285 286 return rc; 287 } 288 289 290 /* 291 * Kernel interface routines. 292 */ 293 294 /* 295 * Read the RTC. 296 * 297 * Starting with HUB rev 2.0, the UV RTC register is replicated across all 298 * cachelines of it's own page. This allows faster simultaneous reads 299 * from a given socket. 300 */ 301 static cycle_t uv_read_rtc(struct clocksource *cs) 302 { 303 unsigned long offset; 304 305 if (uv_get_min_hub_revision_id() == 1) 306 offset = 0; 307 else 308 offset = (uv_blade_processor_id() * L1_CACHE_BYTES) % PAGE_SIZE; 309 310 return (cycle_t)uv_read_local_mmr(UVH_RTC | offset); 311 } 312 313 /* 314 * Program the next event, relative to now 315 */ 316 static int uv_rtc_next_event(unsigned long delta, 317 struct clock_event_device *ced) 318 { 319 int ced_cpu = cpumask_first(ced->cpumask); 320 321 return uv_rtc_set_timer(ced_cpu, delta + uv_read_rtc(NULL)); 322 } 323 324 /* 325 * Setup the RTC timer in oneshot mode 326 */ 327 static void uv_rtc_timer_setup(enum clock_event_mode mode, 328 struct clock_event_device *evt) 329 { 330 int ced_cpu = cpumask_first(evt->cpumask); 331 332 switch (mode) { 333 case CLOCK_EVT_MODE_PERIODIC: 334 case CLOCK_EVT_MODE_ONESHOT: 335 case CLOCK_EVT_MODE_RESUME: 336 /* Nothing to do here yet */ 337 break; 338 case CLOCK_EVT_MODE_UNUSED: 339 case CLOCK_EVT_MODE_SHUTDOWN: 340 uv_rtc_unset_timer(ced_cpu, 1); 341 break; 342 } 343 } 344 345 static void uv_rtc_interrupt(void) 346 { 347 int cpu = smp_processor_id(); 348 struct clock_event_device *ced = &per_cpu(cpu_ced, cpu); 349 350 if (!ced || !ced->event_handler) 351 return; 352 353 if (uv_rtc_unset_timer(cpu, 0) != 1) 354 return; 355 356 ced->event_handler(ced); 357 } 358 359 static int __init uv_enable_evt_rtc(char *str) 360 { 361 uv_rtc_evt_enable = 1; 362 363 return 1; 364 } 365 __setup("uvrtcevt", uv_enable_evt_rtc); 366 367 static __init void uv_rtc_register_clockevents(struct work_struct *dummy) 368 { 369 struct clock_event_device *ced = &__get_cpu_var(cpu_ced); 370 371 *ced = clock_event_device_uv; 372 ced->cpumask = cpumask_of(smp_processor_id()); 373 clockevents_register_device(ced); 374 } 375 376 static __init int uv_rtc_setup_clock(void) 377 { 378 int rc; 379 380 if (!is_uv_system()) 381 return -ENODEV; 382 383 rc = clocksource_register_hz(&clocksource_uv, sn_rtc_cycles_per_second); 384 if (rc) 385 printk(KERN_INFO "UV RTC clocksource failed rc %d\n", rc); 386 else 387 printk(KERN_INFO "UV RTC clocksource registered freq %lu MHz\n", 388 sn_rtc_cycles_per_second/(unsigned long)1E6); 389 390 if (rc || !uv_rtc_evt_enable || x86_platform_ipi_callback) 391 return rc; 392 393 /* Setup and register clockevents */ 394 rc = uv_rtc_allocate_timers(); 395 if (rc) 396 goto error; 397 398 x86_platform_ipi_callback = uv_rtc_interrupt; 399 400 clock_event_device_uv.mult = div_sc(sn_rtc_cycles_per_second, 401 NSEC_PER_SEC, clock_event_device_uv.shift); 402 403 clock_event_device_uv.min_delta_ns = NSEC_PER_SEC / 404 sn_rtc_cycles_per_second; 405 406 clock_event_device_uv.max_delta_ns = clocksource_uv.mask * 407 (NSEC_PER_SEC / sn_rtc_cycles_per_second); 408 409 rc = schedule_on_each_cpu(uv_rtc_register_clockevents); 410 if (rc) { 411 x86_platform_ipi_callback = NULL; 412 uv_rtc_deallocate_timers(); 413 goto error; 414 } 415 416 printk(KERN_INFO "UV RTC clockevents registered\n"); 417 418 return 0; 419 420 error: 421 clocksource_unregister(&clocksource_uv); 422 printk(KERN_INFO "UV RTC clockevents failed rc %d\n", rc); 423 424 return rc; 425 } 426 arch_initcall(uv_rtc_setup_clock); 427