1 /* 2 * intel-mid.c: Intel MID platform setup code 3 * 4 * (C) Copyright 2008, 2012 Intel Corporation 5 * Author: Jacob Pan (jacob.jun.pan@intel.com) 6 * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; version 2 11 * of the License. 12 */ 13 14 #define pr_fmt(fmt) "intel_mid: " fmt 15 16 #include <linux/init.h> 17 #include <linux/kernel.h> 18 #include <linux/interrupt.h> 19 #include <linux/regulator/machine.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sfi.h> 22 #include <linux/irq.h> 23 #include <linux/export.h> 24 #include <linux/notifier.h> 25 26 #include <asm/setup.h> 27 #include <asm/mpspec_def.h> 28 #include <asm/hw_irq.h> 29 #include <asm/apic.h> 30 #include <asm/io_apic.h> 31 #include <asm/intel-mid.h> 32 #include <asm/intel_mid_vrtc.h> 33 #include <asm/io.h> 34 #include <asm/i8259.h> 35 #include <asm/intel_scu_ipc.h> 36 #include <asm/apb_timer.h> 37 #include <asm/reboot.h> 38 39 #include "intel_mid_weak_decls.h" 40 41 /* 42 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, 43 * cmdline option x86_intel_mid_timer can be used to override the configuration 44 * to prefer one or the other. 45 * at runtime, there are basically three timer configurations: 46 * 1. per cpu apbt clock only 47 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only 48 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. 49 * 50 * by default (without cmdline option), platform code first detects cpu type 51 * to see if we are on lincroft or penwell, then set up both lapic or apbt 52 * clocks accordingly. 53 * i.e. by default, medfield uses configuration #2, moorestown uses #1. 54 * config #3 is supported but not recommended on medfield. 55 * 56 * rating and feature summary: 57 * lapic (with C3STOP) --------- 100 58 * apbt (always-on) ------------ 110 59 * lapic (always-on,ARAT) ------ 150 60 */ 61 62 enum intel_mid_timer_options intel_mid_timer_options; 63 64 /* intel_mid_ops to store sub arch ops */ 65 static struct intel_mid_ops *intel_mid_ops; 66 /* getter function for sub arch ops*/ 67 static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; 68 enum intel_mid_cpu_type __intel_mid_cpu_chip; 69 EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); 70 71 static void intel_mid_power_off(void) 72 { 73 }; 74 75 static void intel_mid_reboot(void) 76 { 77 intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); 78 } 79 80 static unsigned long __init intel_mid_calibrate_tsc(void) 81 { 82 return 0; 83 } 84 85 static void __init intel_mid_setup_bp_timer(void) 86 { 87 apbt_time_init(); 88 setup_boot_APIC_clock(); 89 } 90 91 static void __init intel_mid_time_init(void) 92 { 93 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); 94 95 switch (intel_mid_timer_options) { 96 case INTEL_MID_TIMER_APBT_ONLY: 97 break; 98 case INTEL_MID_TIMER_LAPIC_APBT: 99 /* Use apbt and local apic */ 100 x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer; 101 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 102 return; 103 default: 104 if (!boot_cpu_has(X86_FEATURE_ARAT)) 105 break; 106 /* Lapic only, no apbt */ 107 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 108 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 109 return; 110 } 111 112 x86_init.timers.setup_percpu_clockev = apbt_time_init; 113 } 114 115 static void intel_mid_arch_setup(void) 116 { 117 if (boot_cpu_data.x86 != 6) { 118 pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", 119 boot_cpu_data.x86, boot_cpu_data.x86_model); 120 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 121 goto out; 122 } 123 124 switch (boot_cpu_data.x86_model) { 125 case 0x35: 126 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; 127 break; 128 case 0x3C: 129 case 0x4A: 130 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; 131 break; 132 case 0x27: 133 default: 134 __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 135 break; 136 } 137 138 if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) 139 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); 140 else { 141 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); 142 pr_info("ARCH: Unknown SoC, assuming Penwell!\n"); 143 } 144 145 out: 146 if (intel_mid_ops->arch_setup) 147 intel_mid_ops->arch_setup(); 148 149 /* 150 * Intel MID platforms are using explicitly defined regulators. 151 * 152 * Let the regulator core know that we do not have any additional 153 * regulators left. This lets it substitute unprovided regulators with 154 * dummy ones: 155 */ 156 regulator_has_full_constraints(); 157 } 158 159 /* MID systems don't have i8042 controller */ 160 static int intel_mid_i8042_detect(void) 161 { 162 return 0; 163 } 164 165 /* 166 * Moorestown does not have external NMI source nor port 0x61 to report 167 * NMI status. The possible NMI sources are from pmu as a result of NMI 168 * watchdog or lock debug. Reading io port 0x61 results in 0xff which 169 * misled NMI handler. 170 */ 171 static unsigned char intel_mid_get_nmi_reason(void) 172 { 173 return 0; 174 } 175 176 /* 177 * Moorestown specific x86_init function overrides and early setup 178 * calls. 179 */ 180 void __init x86_intel_mid_early_setup(void) 181 { 182 x86_init.resources.probe_roms = x86_init_noop; 183 x86_init.resources.reserve_resources = x86_init_noop; 184 185 x86_init.timers.timer_init = intel_mid_time_init; 186 x86_init.timers.setup_percpu_clockev = x86_init_noop; 187 188 x86_init.irqs.pre_vector_init = x86_init_noop; 189 190 x86_init.oem.arch_setup = intel_mid_arch_setup; 191 192 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; 193 194 x86_platform.calibrate_tsc = intel_mid_calibrate_tsc; 195 x86_platform.i8042_detect = intel_mid_i8042_detect; 196 x86_init.timers.wallclock_init = intel_mid_rtc_init; 197 x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; 198 199 x86_init.pci.init = intel_mid_pci_init; 200 x86_init.pci.fixup_irqs = x86_init_noop; 201 202 legacy_pic = &null_legacy_pic; 203 204 pm_power_off = intel_mid_power_off; 205 machine_ops.emergency_restart = intel_mid_reboot; 206 207 /* Avoid searching for BIOS MP tables */ 208 x86_init.mpparse.find_smp_config = x86_init_noop; 209 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 210 set_bit(MP_BUS_ISA, mp_bus_not_pci); 211 } 212 213 /* 214 * if user does not want to use per CPU apb timer, just give it a lower rating 215 * than local apic timer and skip the late per cpu timer init. 216 */ 217 static inline int __init setup_x86_intel_mid_timer(char *arg) 218 { 219 if (!arg) 220 return -EINVAL; 221 222 if (strcmp("apbt_only", arg) == 0) 223 intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; 224 else if (strcmp("lapic_and_apbt", arg) == 0) 225 intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; 226 else { 227 pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", 228 arg); 229 return -EINVAL; 230 } 231 return 0; 232 } 233 __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); 234