1b886d83cSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 205454c26SKuppuswamy Sathyanarayanan /* 305454c26SKuppuswamy Sathyanarayanan * intel-mid.c: Intel MID platform setup code 405454c26SKuppuswamy Sathyanarayanan * 505454c26SKuppuswamy Sathyanarayanan * (C) Copyright 2008, 2012 Intel Corporation 605454c26SKuppuswamy Sathyanarayanan * Author: Jacob Pan (jacob.jun.pan@intel.com) 705454c26SKuppuswamy Sathyanarayanan * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 805454c26SKuppuswamy Sathyanarayanan */ 905454c26SKuppuswamy Sathyanarayanan 10712b6aa8SKuppuswamy Sathyanarayanan #define pr_fmt(fmt) "intel_mid: " fmt 1105454c26SKuppuswamy Sathyanarayanan 1205454c26SKuppuswamy Sathyanarayanan #include <linux/init.h> 1305454c26SKuppuswamy Sathyanarayanan #include <linux/kernel.h> 1405454c26SKuppuswamy Sathyanarayanan #include <linux/interrupt.h> 15a11836faSAndy Shevchenko #include <linux/regulator/machine.h> 1605454c26SKuppuswamy Sathyanarayanan #include <linux/scatterlist.h> 1705454c26SKuppuswamy Sathyanarayanan #include <linux/sfi.h> 1805454c26SKuppuswamy Sathyanarayanan #include <linux/irq.h> 19cc3ae7b0SPaul Gortmaker #include <linux/export.h> 2005454c26SKuppuswamy Sathyanarayanan #include <linux/notifier.h> 2105454c26SKuppuswamy Sathyanarayanan 2205454c26SKuppuswamy Sathyanarayanan #include <asm/setup.h> 2305454c26SKuppuswamy Sathyanarayanan #include <asm/mpspec_def.h> 2405454c26SKuppuswamy Sathyanarayanan #include <asm/hw_irq.h> 2505454c26SKuppuswamy Sathyanarayanan #include <asm/apic.h> 2605454c26SKuppuswamy Sathyanarayanan #include <asm/io_apic.h> 2705454c26SKuppuswamy Sathyanarayanan #include <asm/intel-mid.h> 2805454c26SKuppuswamy Sathyanarayanan #include <asm/intel_mid_vrtc.h> 2905454c26SKuppuswamy Sathyanarayanan #include <asm/io.h> 3005454c26SKuppuswamy Sathyanarayanan #include <asm/i8259.h> 3105454c26SKuppuswamy Sathyanarayanan #include <asm/intel_scu_ipc.h> 3205454c26SKuppuswamy Sathyanarayanan #include <asm/apb_timer.h> 3305454c26SKuppuswamy Sathyanarayanan #include <asm/reboot.h> 3405454c26SKuppuswamy Sathyanarayanan 3505454c26SKuppuswamy Sathyanarayanan /* 3605454c26SKuppuswamy Sathyanarayanan * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, 37712b6aa8SKuppuswamy Sathyanarayanan * cmdline option x86_intel_mid_timer can be used to override the configuration 3805454c26SKuppuswamy Sathyanarayanan * to prefer one or the other. 3905454c26SKuppuswamy Sathyanarayanan * at runtime, there are basically three timer configurations: 4005454c26SKuppuswamy Sathyanarayanan * 1. per cpu apbt clock only 4105454c26SKuppuswamy Sathyanarayanan * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only 4205454c26SKuppuswamy Sathyanarayanan * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. 4305454c26SKuppuswamy Sathyanarayanan * 4405454c26SKuppuswamy Sathyanarayanan * by default (without cmdline option), platform code first detects cpu type 4505454c26SKuppuswamy Sathyanarayanan * to see if we are on lincroft or penwell, then set up both lapic or apbt 4605454c26SKuppuswamy Sathyanarayanan * clocks accordingly. 4705454c26SKuppuswamy Sathyanarayanan * i.e. by default, medfield uses configuration #2, moorestown uses #1. 4805454c26SKuppuswamy Sathyanarayanan * config #3 is supported but not recommended on medfield. 4905454c26SKuppuswamy Sathyanarayanan * 5005454c26SKuppuswamy Sathyanarayanan * rating and feature summary: 5105454c26SKuppuswamy Sathyanarayanan * lapic (with C3STOP) --------- 100 5205454c26SKuppuswamy Sathyanarayanan * apbt (always-on) ------------ 110 5305454c26SKuppuswamy Sathyanarayanan * lapic (always-on,ARAT) ------ 150 5405454c26SKuppuswamy Sathyanarayanan */ 5505454c26SKuppuswamy Sathyanarayanan 56712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_timer_options intel_mid_timer_options; 5705454c26SKuppuswamy Sathyanarayanan 58712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_cpu_type __intel_mid_cpu_chip; 59712b6aa8SKuppuswamy Sathyanarayanan EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); 6005454c26SKuppuswamy Sathyanarayanan 6185611e3fSKuppuswamy Sathyanarayanan static void intel_mid_power_off(void) 6285611e3fSKuppuswamy Sathyanarayanan { 63bda7b072SAndy Shevchenko /* Shut down South Complex via PWRMU */ 64bda7b072SAndy Shevchenko intel_mid_pwr_power_off(); 65bda7b072SAndy Shevchenko 66bda7b072SAndy Shevchenko /* Only for Tangier, the rest will ignore this command */ 67bda7b072SAndy Shevchenko intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1); 6885611e3fSKuppuswamy Sathyanarayanan }; 6985611e3fSKuppuswamy Sathyanarayanan 70712b6aa8SKuppuswamy Sathyanarayanan static void intel_mid_reboot(void) 7105454c26SKuppuswamy Sathyanarayanan { 72028091f8SSebastian Panceac intel_scu_ipc_simple_command(IPCMSG_COLD_RESET, 0); 7305454c26SKuppuswamy Sathyanarayanan } 7405454c26SKuppuswamy Sathyanarayanan 756648d1b4SThomas Gleixner static void __init intel_mid_setup_bp_timer(void) 766648d1b4SThomas Gleixner { 776648d1b4SThomas Gleixner apbt_time_init(); 786648d1b4SThomas Gleixner setup_boot_APIC_clock(); 796648d1b4SThomas Gleixner } 806648d1b4SThomas Gleixner 81712b6aa8SKuppuswamy Sathyanarayanan static void __init intel_mid_time_init(void) 8205454c26SKuppuswamy Sathyanarayanan { 8305454c26SKuppuswamy Sathyanarayanan sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); 846648d1b4SThomas Gleixner 85712b6aa8SKuppuswamy Sathyanarayanan switch (intel_mid_timer_options) { 86712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_APBT_ONLY: 8705454c26SKuppuswamy Sathyanarayanan break; 88712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_LAPIC_APBT: 896648d1b4SThomas Gleixner /* Use apbt and local apic */ 906648d1b4SThomas Gleixner x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer; 9105454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 926648d1b4SThomas Gleixner return; 9305454c26SKuppuswamy Sathyanarayanan default: 9405454c26SKuppuswamy Sathyanarayanan if (!boot_cpu_has(X86_FEATURE_ARAT)) 9505454c26SKuppuswamy Sathyanarayanan break; 966648d1b4SThomas Gleixner /* Lapic only, no apbt */ 9705454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 9805454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 9905454c26SKuppuswamy Sathyanarayanan return; 10005454c26SKuppuswamy Sathyanarayanan } 1016648d1b4SThomas Gleixner 1026648d1b4SThomas Gleixner x86_init.timers.setup_percpu_clockev = apbt_time_init; 10305454c26SKuppuswamy Sathyanarayanan } 10405454c26SKuppuswamy Sathyanarayanan 105aeeca404SPaul Gortmaker static void intel_mid_arch_setup(void) 10605454c26SKuppuswamy Sathyanarayanan { 10785611e3fSKuppuswamy Sathyanarayanan if (boot_cpu_data.x86 != 6) { 10805454c26SKuppuswamy Sathyanarayanan pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", 10905454c26SKuppuswamy Sathyanarayanan boot_cpu_data.x86, boot_cpu_data.x86_model); 110712b6aa8SKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 11185611e3fSKuppuswamy Sathyanarayanan goto out; 11205454c26SKuppuswamy Sathyanarayanan } 11385611e3fSKuppuswamy Sathyanarayanan 11485611e3fSKuppuswamy Sathyanarayanan switch (boot_cpu_data.x86_model) { 11585611e3fSKuppuswamy Sathyanarayanan case 0x35: 11685611e3fSKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; 11785611e3fSKuppuswamy Sathyanarayanan break; 118bc20aa48SDavid Cohen case 0x3C: 119bc20aa48SDavid Cohen case 0x4A: 120bc20aa48SDavid Cohen __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; 12141afb1dfSAndy Shevchenko x86_platform.legacy.rtc = 1; 122bc20aa48SDavid Cohen break; 12385611e3fSKuppuswamy Sathyanarayanan case 0x27: 12485611e3fSKuppuswamy Sathyanarayanan default: 12585611e3fSKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 12685611e3fSKuppuswamy Sathyanarayanan break; 12785611e3fSKuppuswamy Sathyanarayanan } 12885611e3fSKuppuswamy Sathyanarayanan 12985611e3fSKuppuswamy Sathyanarayanan out: 130a11836faSAndy Shevchenko /* 131a11836faSAndy Shevchenko * Intel MID platforms are using explicitly defined regulators. 132a11836faSAndy Shevchenko * 133a11836faSAndy Shevchenko * Let the regulator core know that we do not have any additional 134a11836faSAndy Shevchenko * regulators left. This lets it substitute unprovided regulators with 135a11836faSAndy Shevchenko * dummy ones: 136a11836faSAndy Shevchenko */ 137a11836faSAndy Shevchenko regulator_has_full_constraints(); 13805454c26SKuppuswamy Sathyanarayanan } 13905454c26SKuppuswamy Sathyanarayanan 14005454c26SKuppuswamy Sathyanarayanan /* 14105454c26SKuppuswamy Sathyanarayanan * Moorestown does not have external NMI source nor port 0x61 to report 14205454c26SKuppuswamy Sathyanarayanan * NMI status. The possible NMI sources are from pmu as a result of NMI 14305454c26SKuppuswamy Sathyanarayanan * watchdog or lock debug. Reading io port 0x61 results in 0xff which 14405454c26SKuppuswamy Sathyanarayanan * misled NMI handler. 14505454c26SKuppuswamy Sathyanarayanan */ 146712b6aa8SKuppuswamy Sathyanarayanan static unsigned char intel_mid_get_nmi_reason(void) 14705454c26SKuppuswamy Sathyanarayanan { 14805454c26SKuppuswamy Sathyanarayanan return 0; 14905454c26SKuppuswamy Sathyanarayanan } 15005454c26SKuppuswamy Sathyanarayanan 15105454c26SKuppuswamy Sathyanarayanan /* 15205454c26SKuppuswamy Sathyanarayanan * Moorestown specific x86_init function overrides and early setup 15305454c26SKuppuswamy Sathyanarayanan * calls. 15405454c26SKuppuswamy Sathyanarayanan */ 155712b6aa8SKuppuswamy Sathyanarayanan void __init x86_intel_mid_early_setup(void) 15605454c26SKuppuswamy Sathyanarayanan { 15705454c26SKuppuswamy Sathyanarayanan x86_init.resources.probe_roms = x86_init_noop; 15805454c26SKuppuswamy Sathyanarayanan x86_init.resources.reserve_resources = x86_init_noop; 15905454c26SKuppuswamy Sathyanarayanan 160712b6aa8SKuppuswamy Sathyanarayanan x86_init.timers.timer_init = intel_mid_time_init; 16105454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = x86_init_noop; 162b0ee9effSAndy Shevchenko x86_init.timers.wallclock_init = intel_mid_rtc_init; 16305454c26SKuppuswamy Sathyanarayanan 16405454c26SKuppuswamy Sathyanarayanan x86_init.irqs.pre_vector_init = x86_init_noop; 16505454c26SKuppuswamy Sathyanarayanan 166712b6aa8SKuppuswamy Sathyanarayanan x86_init.oem.arch_setup = intel_mid_arch_setup; 16705454c26SKuppuswamy Sathyanarayanan 16805454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; 16905454c26SKuppuswamy Sathyanarayanan 170712b6aa8SKuppuswamy Sathyanarayanan x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; 17105454c26SKuppuswamy Sathyanarayanan 172a912a758SAndy Shevchenko x86_init.pci.arch_init = intel_mid_pci_init; 17305454c26SKuppuswamy Sathyanarayanan x86_init.pci.fixup_irqs = x86_init_noop; 17405454c26SKuppuswamy Sathyanarayanan 17505454c26SKuppuswamy Sathyanarayanan legacy_pic = &null_legacy_pic; 17605454c26SKuppuswamy Sathyanarayanan 17702428742SAndy Shevchenko /* 17802428742SAndy Shevchenko * Do nothing for now as everything needed done in 17902428742SAndy Shevchenko * x86_intel_mid_early_setup() below. 18002428742SAndy Shevchenko */ 18102428742SAndy Shevchenko x86_init.acpi.reduced_hw_early_init = x86_init_noop; 18202428742SAndy Shevchenko 183712b6aa8SKuppuswamy Sathyanarayanan pm_power_off = intel_mid_power_off; 184712b6aa8SKuppuswamy Sathyanarayanan machine_ops.emergency_restart = intel_mid_reboot; 18505454c26SKuppuswamy Sathyanarayanan 18605454c26SKuppuswamy Sathyanarayanan /* Avoid searching for BIOS MP tables */ 18705454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.find_smp_config = x86_init_noop; 18805454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.get_smp_config = x86_init_uint_noop; 18905454c26SKuppuswamy Sathyanarayanan set_bit(MP_BUS_ISA, mp_bus_not_pci); 19005454c26SKuppuswamy Sathyanarayanan } 19105454c26SKuppuswamy Sathyanarayanan 19205454c26SKuppuswamy Sathyanarayanan /* 19305454c26SKuppuswamy Sathyanarayanan * if user does not want to use per CPU apb timer, just give it a lower rating 19405454c26SKuppuswamy Sathyanarayanan * than local apic timer and skip the late per cpu timer init. 19505454c26SKuppuswamy Sathyanarayanan */ 196712b6aa8SKuppuswamy Sathyanarayanan static inline int __init setup_x86_intel_mid_timer(char *arg) 19705454c26SKuppuswamy Sathyanarayanan { 19805454c26SKuppuswamy Sathyanarayanan if (!arg) 19905454c26SKuppuswamy Sathyanarayanan return -EINVAL; 20005454c26SKuppuswamy Sathyanarayanan 20105454c26SKuppuswamy Sathyanarayanan if (strcmp("apbt_only", arg) == 0) 202712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; 20305454c26SKuppuswamy Sathyanarayanan else if (strcmp("lapic_and_apbt", arg) == 0) 204712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; 20505454c26SKuppuswamy Sathyanarayanan else { 206b000de58SAndy Shevchenko pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", 20705454c26SKuppuswamy Sathyanarayanan arg); 20805454c26SKuppuswamy Sathyanarayanan return -EINVAL; 20905454c26SKuppuswamy Sathyanarayanan } 21005454c26SKuppuswamy Sathyanarayanan return 0; 21105454c26SKuppuswamy Sathyanarayanan } 212712b6aa8SKuppuswamy Sathyanarayanan __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); 213