105454c26SKuppuswamy Sathyanarayanan /* 205454c26SKuppuswamy Sathyanarayanan * intel-mid.c: Intel MID platform setup code 305454c26SKuppuswamy Sathyanarayanan * 405454c26SKuppuswamy Sathyanarayanan * (C) Copyright 2008, 2012 Intel Corporation 505454c26SKuppuswamy Sathyanarayanan * Author: Jacob Pan (jacob.jun.pan@intel.com) 605454c26SKuppuswamy Sathyanarayanan * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 705454c26SKuppuswamy Sathyanarayanan * 805454c26SKuppuswamy Sathyanarayanan * This program is free software; you can redistribute it and/or 905454c26SKuppuswamy Sathyanarayanan * modify it under the terms of the GNU General Public License 1005454c26SKuppuswamy Sathyanarayanan * as published by the Free Software Foundation; version 2 1105454c26SKuppuswamy Sathyanarayanan * of the License. 1205454c26SKuppuswamy Sathyanarayanan */ 1305454c26SKuppuswamy Sathyanarayanan 14712b6aa8SKuppuswamy Sathyanarayanan #define pr_fmt(fmt) "intel_mid: " fmt 1505454c26SKuppuswamy Sathyanarayanan 1605454c26SKuppuswamy Sathyanarayanan #include <linux/init.h> 1705454c26SKuppuswamy Sathyanarayanan #include <linux/kernel.h> 1805454c26SKuppuswamy Sathyanarayanan #include <linux/interrupt.h> 19a11836faSAndy Shevchenko #include <linux/regulator/machine.h> 2005454c26SKuppuswamy Sathyanarayanan #include <linux/scatterlist.h> 2105454c26SKuppuswamy Sathyanarayanan #include <linux/sfi.h> 2205454c26SKuppuswamy Sathyanarayanan #include <linux/irq.h> 23cc3ae7b0SPaul Gortmaker #include <linux/export.h> 2405454c26SKuppuswamy Sathyanarayanan #include <linux/notifier.h> 2505454c26SKuppuswamy Sathyanarayanan 2605454c26SKuppuswamy Sathyanarayanan #include <asm/setup.h> 2705454c26SKuppuswamy Sathyanarayanan #include <asm/mpspec_def.h> 2805454c26SKuppuswamy Sathyanarayanan #include <asm/hw_irq.h> 2905454c26SKuppuswamy Sathyanarayanan #include <asm/apic.h> 3005454c26SKuppuswamy Sathyanarayanan #include <asm/io_apic.h> 3105454c26SKuppuswamy Sathyanarayanan #include <asm/intel-mid.h> 3205454c26SKuppuswamy Sathyanarayanan #include <asm/intel_mid_vrtc.h> 3305454c26SKuppuswamy Sathyanarayanan #include <asm/io.h> 3405454c26SKuppuswamy Sathyanarayanan #include <asm/i8259.h> 3505454c26SKuppuswamy Sathyanarayanan #include <asm/intel_scu_ipc.h> 3605454c26SKuppuswamy Sathyanarayanan #include <asm/apb_timer.h> 3705454c26SKuppuswamy Sathyanarayanan #include <asm/reboot.h> 3805454c26SKuppuswamy Sathyanarayanan 39ecd6910dSDavid Cohen #include "intel_mid_weak_decls.h" 40ecd6910dSDavid Cohen 4105454c26SKuppuswamy Sathyanarayanan /* 4205454c26SKuppuswamy Sathyanarayanan * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, 43712b6aa8SKuppuswamy Sathyanarayanan * cmdline option x86_intel_mid_timer can be used to override the configuration 4405454c26SKuppuswamy Sathyanarayanan * to prefer one or the other. 4505454c26SKuppuswamy Sathyanarayanan * at runtime, there are basically three timer configurations: 4605454c26SKuppuswamy Sathyanarayanan * 1. per cpu apbt clock only 4705454c26SKuppuswamy Sathyanarayanan * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only 4805454c26SKuppuswamy Sathyanarayanan * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. 4905454c26SKuppuswamy Sathyanarayanan * 5005454c26SKuppuswamy Sathyanarayanan * by default (without cmdline option), platform code first detects cpu type 5105454c26SKuppuswamy Sathyanarayanan * to see if we are on lincroft or penwell, then set up both lapic or apbt 5205454c26SKuppuswamy Sathyanarayanan * clocks accordingly. 5305454c26SKuppuswamy Sathyanarayanan * i.e. by default, medfield uses configuration #2, moorestown uses #1. 5405454c26SKuppuswamy Sathyanarayanan * config #3 is supported but not recommended on medfield. 5505454c26SKuppuswamy Sathyanarayanan * 5605454c26SKuppuswamy Sathyanarayanan * rating and feature summary: 5705454c26SKuppuswamy Sathyanarayanan * lapic (with C3STOP) --------- 100 5805454c26SKuppuswamy Sathyanarayanan * apbt (always-on) ------------ 110 5905454c26SKuppuswamy Sathyanarayanan * lapic (always-on,ARAT) ------ 150 6005454c26SKuppuswamy Sathyanarayanan */ 6105454c26SKuppuswamy Sathyanarayanan 62712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_timer_options intel_mid_timer_options; 6305454c26SKuppuswamy Sathyanarayanan 6485611e3fSKuppuswamy Sathyanarayanan /* intel_mid_ops to store sub arch ops */ 65d1f0f6c7SAndy Shevchenko static struct intel_mid_ops *intel_mid_ops; 6685611e3fSKuppuswamy Sathyanarayanan /* getter function for sub arch ops*/ 6785611e3fSKuppuswamy Sathyanarayanan static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; 68712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_cpu_type __intel_mid_cpu_chip; 69712b6aa8SKuppuswamy Sathyanarayanan EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); 7005454c26SKuppuswamy Sathyanarayanan 7185611e3fSKuppuswamy Sathyanarayanan static void intel_mid_power_off(void) 7285611e3fSKuppuswamy Sathyanarayanan { 73bda7b072SAndy Shevchenko /* Shut down South Complex via PWRMU */ 74bda7b072SAndy Shevchenko intel_mid_pwr_power_off(); 75bda7b072SAndy Shevchenko 76bda7b072SAndy Shevchenko /* Only for Tangier, the rest will ignore this command */ 77bda7b072SAndy Shevchenko intel_scu_ipc_simple_command(IPCMSG_COLD_OFF, 1); 7885611e3fSKuppuswamy Sathyanarayanan }; 7985611e3fSKuppuswamy Sathyanarayanan 80712b6aa8SKuppuswamy Sathyanarayanan static void intel_mid_reboot(void) 8105454c26SKuppuswamy Sathyanarayanan { 8205454c26SKuppuswamy Sathyanarayanan intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); 8305454c26SKuppuswamy Sathyanarayanan } 8405454c26SKuppuswamy Sathyanarayanan 8585611e3fSKuppuswamy Sathyanarayanan static unsigned long __init intel_mid_calibrate_tsc(void) 8685611e3fSKuppuswamy Sathyanarayanan { 8785611e3fSKuppuswamy Sathyanarayanan return 0; 8885611e3fSKuppuswamy Sathyanarayanan } 8985611e3fSKuppuswamy Sathyanarayanan 906648d1b4SThomas Gleixner static void __init intel_mid_setup_bp_timer(void) 916648d1b4SThomas Gleixner { 926648d1b4SThomas Gleixner apbt_time_init(); 936648d1b4SThomas Gleixner setup_boot_APIC_clock(); 946648d1b4SThomas Gleixner } 956648d1b4SThomas Gleixner 96712b6aa8SKuppuswamy Sathyanarayanan static void __init intel_mid_time_init(void) 9705454c26SKuppuswamy Sathyanarayanan { 9805454c26SKuppuswamy Sathyanarayanan sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); 996648d1b4SThomas Gleixner 100712b6aa8SKuppuswamy Sathyanarayanan switch (intel_mid_timer_options) { 101712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_APBT_ONLY: 10205454c26SKuppuswamy Sathyanarayanan break; 103712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_LAPIC_APBT: 1046648d1b4SThomas Gleixner /* Use apbt and local apic */ 1056648d1b4SThomas Gleixner x86_init.timers.setup_percpu_clockev = intel_mid_setup_bp_timer; 10605454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 1076648d1b4SThomas Gleixner return; 10805454c26SKuppuswamy Sathyanarayanan default: 10905454c26SKuppuswamy Sathyanarayanan if (!boot_cpu_has(X86_FEATURE_ARAT)) 11005454c26SKuppuswamy Sathyanarayanan break; 1116648d1b4SThomas Gleixner /* Lapic only, no apbt */ 11205454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 11305454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 11405454c26SKuppuswamy Sathyanarayanan return; 11505454c26SKuppuswamy Sathyanarayanan } 1166648d1b4SThomas Gleixner 1176648d1b4SThomas Gleixner x86_init.timers.setup_percpu_clockev = apbt_time_init; 11805454c26SKuppuswamy Sathyanarayanan } 11905454c26SKuppuswamy Sathyanarayanan 120aeeca404SPaul Gortmaker static void intel_mid_arch_setup(void) 12105454c26SKuppuswamy Sathyanarayanan { 12285611e3fSKuppuswamy Sathyanarayanan if (boot_cpu_data.x86 != 6) { 12305454c26SKuppuswamy Sathyanarayanan pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", 12405454c26SKuppuswamy Sathyanarayanan boot_cpu_data.x86, boot_cpu_data.x86_model); 125712b6aa8SKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 12685611e3fSKuppuswamy Sathyanarayanan goto out; 12705454c26SKuppuswamy Sathyanarayanan } 12885611e3fSKuppuswamy Sathyanarayanan 12985611e3fSKuppuswamy Sathyanarayanan switch (boot_cpu_data.x86_model) { 13085611e3fSKuppuswamy Sathyanarayanan case 0x35: 13185611e3fSKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; 13285611e3fSKuppuswamy Sathyanarayanan break; 133bc20aa48SDavid Cohen case 0x3C: 134bc20aa48SDavid Cohen case 0x4A: 135bc20aa48SDavid Cohen __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; 136bc20aa48SDavid Cohen break; 13785611e3fSKuppuswamy Sathyanarayanan case 0x27: 13885611e3fSKuppuswamy Sathyanarayanan default: 13985611e3fSKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 14085611e3fSKuppuswamy Sathyanarayanan break; 14185611e3fSKuppuswamy Sathyanarayanan } 14285611e3fSKuppuswamy Sathyanarayanan 14385611e3fSKuppuswamy Sathyanarayanan if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) 14485611e3fSKuppuswamy Sathyanarayanan intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); 14585611e3fSKuppuswamy Sathyanarayanan else { 14685611e3fSKuppuswamy Sathyanarayanan intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); 147b000de58SAndy Shevchenko pr_info("ARCH: Unknown SoC, assuming Penwell!\n"); 14885611e3fSKuppuswamy Sathyanarayanan } 14985611e3fSKuppuswamy Sathyanarayanan 15085611e3fSKuppuswamy Sathyanarayanan out: 15185611e3fSKuppuswamy Sathyanarayanan if (intel_mid_ops->arch_setup) 15285611e3fSKuppuswamy Sathyanarayanan intel_mid_ops->arch_setup(); 153a11836faSAndy Shevchenko 154a11836faSAndy Shevchenko /* 155a11836faSAndy Shevchenko * Intel MID platforms are using explicitly defined regulators. 156a11836faSAndy Shevchenko * 157a11836faSAndy Shevchenko * Let the regulator core know that we do not have any additional 158a11836faSAndy Shevchenko * regulators left. This lets it substitute unprovided regulators with 159a11836faSAndy Shevchenko * dummy ones: 160a11836faSAndy Shevchenko */ 161a11836faSAndy Shevchenko regulator_has_full_constraints(); 16205454c26SKuppuswamy Sathyanarayanan } 16305454c26SKuppuswamy Sathyanarayanan 16405454c26SKuppuswamy Sathyanarayanan /* 16505454c26SKuppuswamy Sathyanarayanan * Moorestown does not have external NMI source nor port 0x61 to report 16605454c26SKuppuswamy Sathyanarayanan * NMI status. The possible NMI sources are from pmu as a result of NMI 16705454c26SKuppuswamy Sathyanarayanan * watchdog or lock debug. Reading io port 0x61 results in 0xff which 16805454c26SKuppuswamy Sathyanarayanan * misled NMI handler. 16905454c26SKuppuswamy Sathyanarayanan */ 170712b6aa8SKuppuswamy Sathyanarayanan static unsigned char intel_mid_get_nmi_reason(void) 17105454c26SKuppuswamy Sathyanarayanan { 17205454c26SKuppuswamy Sathyanarayanan return 0; 17305454c26SKuppuswamy Sathyanarayanan } 17405454c26SKuppuswamy Sathyanarayanan 17505454c26SKuppuswamy Sathyanarayanan /* 17605454c26SKuppuswamy Sathyanarayanan * Moorestown specific x86_init function overrides and early setup 17705454c26SKuppuswamy Sathyanarayanan * calls. 17805454c26SKuppuswamy Sathyanarayanan */ 179712b6aa8SKuppuswamy Sathyanarayanan void __init x86_intel_mid_early_setup(void) 18005454c26SKuppuswamy Sathyanarayanan { 18105454c26SKuppuswamy Sathyanarayanan x86_init.resources.probe_roms = x86_init_noop; 18205454c26SKuppuswamy Sathyanarayanan x86_init.resources.reserve_resources = x86_init_noop; 18305454c26SKuppuswamy Sathyanarayanan 184712b6aa8SKuppuswamy Sathyanarayanan x86_init.timers.timer_init = intel_mid_time_init; 18505454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = x86_init_noop; 186b0ee9effSAndy Shevchenko x86_init.timers.wallclock_init = intel_mid_rtc_init; 18705454c26SKuppuswamy Sathyanarayanan 18805454c26SKuppuswamy Sathyanarayanan x86_init.irqs.pre_vector_init = x86_init_noop; 18905454c26SKuppuswamy Sathyanarayanan 190712b6aa8SKuppuswamy Sathyanarayanan x86_init.oem.arch_setup = intel_mid_arch_setup; 19105454c26SKuppuswamy Sathyanarayanan 19205454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; 19305454c26SKuppuswamy Sathyanarayanan 194712b6aa8SKuppuswamy Sathyanarayanan x86_platform.calibrate_tsc = intel_mid_calibrate_tsc; 195712b6aa8SKuppuswamy Sathyanarayanan x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; 19605454c26SKuppuswamy Sathyanarayanan 197712b6aa8SKuppuswamy Sathyanarayanan x86_init.pci.init = intel_mid_pci_init; 19805454c26SKuppuswamy Sathyanarayanan x86_init.pci.fixup_irqs = x86_init_noop; 19905454c26SKuppuswamy Sathyanarayanan 20005454c26SKuppuswamy Sathyanarayanan legacy_pic = &null_legacy_pic; 20105454c26SKuppuswamy Sathyanarayanan 202712b6aa8SKuppuswamy Sathyanarayanan pm_power_off = intel_mid_power_off; 203712b6aa8SKuppuswamy Sathyanarayanan machine_ops.emergency_restart = intel_mid_reboot; 20405454c26SKuppuswamy Sathyanarayanan 20505454c26SKuppuswamy Sathyanarayanan /* Avoid searching for BIOS MP tables */ 20605454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.find_smp_config = x86_init_noop; 20705454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.get_smp_config = x86_init_uint_noop; 20805454c26SKuppuswamy Sathyanarayanan set_bit(MP_BUS_ISA, mp_bus_not_pci); 20905454c26SKuppuswamy Sathyanarayanan } 21005454c26SKuppuswamy Sathyanarayanan 21105454c26SKuppuswamy Sathyanarayanan /* 21205454c26SKuppuswamy Sathyanarayanan * if user does not want to use per CPU apb timer, just give it a lower rating 21305454c26SKuppuswamy Sathyanarayanan * than local apic timer and skip the late per cpu timer init. 21405454c26SKuppuswamy Sathyanarayanan */ 215712b6aa8SKuppuswamy Sathyanarayanan static inline int __init setup_x86_intel_mid_timer(char *arg) 21605454c26SKuppuswamy Sathyanarayanan { 21705454c26SKuppuswamy Sathyanarayanan if (!arg) 21805454c26SKuppuswamy Sathyanarayanan return -EINVAL; 21905454c26SKuppuswamy Sathyanarayanan 22005454c26SKuppuswamy Sathyanarayanan if (strcmp("apbt_only", arg) == 0) 221712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; 22205454c26SKuppuswamy Sathyanarayanan else if (strcmp("lapic_and_apbt", arg) == 0) 223712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; 22405454c26SKuppuswamy Sathyanarayanan else { 225b000de58SAndy Shevchenko pr_warn("X86 INTEL_MID timer option %s not recognised use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", 22605454c26SKuppuswamy Sathyanarayanan arg); 22705454c26SKuppuswamy Sathyanarayanan return -EINVAL; 22805454c26SKuppuswamy Sathyanarayanan } 22905454c26SKuppuswamy Sathyanarayanan return 0; 23005454c26SKuppuswamy Sathyanarayanan } 231712b6aa8SKuppuswamy Sathyanarayanan __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); 232