105454c26SKuppuswamy Sathyanarayanan /* 205454c26SKuppuswamy Sathyanarayanan * intel-mid.c: Intel MID platform setup code 305454c26SKuppuswamy Sathyanarayanan * 405454c26SKuppuswamy Sathyanarayanan * (C) Copyright 2008, 2012 Intel Corporation 505454c26SKuppuswamy Sathyanarayanan * Author: Jacob Pan (jacob.jun.pan@intel.com) 605454c26SKuppuswamy Sathyanarayanan * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 705454c26SKuppuswamy Sathyanarayanan * 805454c26SKuppuswamy Sathyanarayanan * This program is free software; you can redistribute it and/or 905454c26SKuppuswamy Sathyanarayanan * modify it under the terms of the GNU General Public License 1005454c26SKuppuswamy Sathyanarayanan * as published by the Free Software Foundation; version 2 1105454c26SKuppuswamy Sathyanarayanan * of the License. 1205454c26SKuppuswamy Sathyanarayanan */ 1305454c26SKuppuswamy Sathyanarayanan 14712b6aa8SKuppuswamy Sathyanarayanan #define pr_fmt(fmt) "intel_mid: " fmt 1505454c26SKuppuswamy Sathyanarayanan 1605454c26SKuppuswamy Sathyanarayanan #include <linux/init.h> 1705454c26SKuppuswamy Sathyanarayanan #include <linux/kernel.h> 1805454c26SKuppuswamy Sathyanarayanan #include <linux/interrupt.h> 1905454c26SKuppuswamy Sathyanarayanan #include <linux/scatterlist.h> 2005454c26SKuppuswamy Sathyanarayanan #include <linux/sfi.h> 2105454c26SKuppuswamy Sathyanarayanan #include <linux/irq.h> 2205454c26SKuppuswamy Sathyanarayanan #include <linux/module.h> 2305454c26SKuppuswamy Sathyanarayanan #include <linux/notifier.h> 2405454c26SKuppuswamy Sathyanarayanan 2505454c26SKuppuswamy Sathyanarayanan #include <asm/setup.h> 2605454c26SKuppuswamy Sathyanarayanan #include <asm/mpspec_def.h> 2705454c26SKuppuswamy Sathyanarayanan #include <asm/hw_irq.h> 2805454c26SKuppuswamy Sathyanarayanan #include <asm/apic.h> 2905454c26SKuppuswamy Sathyanarayanan #include <asm/io_apic.h> 3005454c26SKuppuswamy Sathyanarayanan #include <asm/intel-mid.h> 3105454c26SKuppuswamy Sathyanarayanan #include <asm/intel_mid_vrtc.h> 3205454c26SKuppuswamy Sathyanarayanan #include <asm/io.h> 3305454c26SKuppuswamy Sathyanarayanan #include <asm/i8259.h> 3405454c26SKuppuswamy Sathyanarayanan #include <asm/intel_scu_ipc.h> 3505454c26SKuppuswamy Sathyanarayanan #include <asm/apb_timer.h> 3605454c26SKuppuswamy Sathyanarayanan #include <asm/reboot.h> 3705454c26SKuppuswamy Sathyanarayanan 3805454c26SKuppuswamy Sathyanarayanan /* 3905454c26SKuppuswamy Sathyanarayanan * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, 40712b6aa8SKuppuswamy Sathyanarayanan * cmdline option x86_intel_mid_timer can be used to override the configuration 4105454c26SKuppuswamy Sathyanarayanan * to prefer one or the other. 4205454c26SKuppuswamy Sathyanarayanan * at runtime, there are basically three timer configurations: 4305454c26SKuppuswamy Sathyanarayanan * 1. per cpu apbt clock only 4405454c26SKuppuswamy Sathyanarayanan * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only 4505454c26SKuppuswamy Sathyanarayanan * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. 4605454c26SKuppuswamy Sathyanarayanan * 4705454c26SKuppuswamy Sathyanarayanan * by default (without cmdline option), platform code first detects cpu type 4805454c26SKuppuswamy Sathyanarayanan * to see if we are on lincroft or penwell, then set up both lapic or apbt 4905454c26SKuppuswamy Sathyanarayanan * clocks accordingly. 5005454c26SKuppuswamy Sathyanarayanan * i.e. by default, medfield uses configuration #2, moorestown uses #1. 5105454c26SKuppuswamy Sathyanarayanan * config #3 is supported but not recommended on medfield. 5205454c26SKuppuswamy Sathyanarayanan * 5305454c26SKuppuswamy Sathyanarayanan * rating and feature summary: 5405454c26SKuppuswamy Sathyanarayanan * lapic (with C3STOP) --------- 100 5505454c26SKuppuswamy Sathyanarayanan * apbt (always-on) ------------ 110 5605454c26SKuppuswamy Sathyanarayanan * lapic (always-on,ARAT) ------ 150 5705454c26SKuppuswamy Sathyanarayanan */ 5805454c26SKuppuswamy Sathyanarayanan 59712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_timer_options intel_mid_timer_options; 6005454c26SKuppuswamy Sathyanarayanan 61712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_cpu_type __intel_mid_cpu_chip; 62712b6aa8SKuppuswamy Sathyanarayanan EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); 6305454c26SKuppuswamy Sathyanarayanan 64712b6aa8SKuppuswamy Sathyanarayanan static void intel_mid_power_off(void) 6505454c26SKuppuswamy Sathyanarayanan { 6605454c26SKuppuswamy Sathyanarayanan } 6705454c26SKuppuswamy Sathyanarayanan 68712b6aa8SKuppuswamy Sathyanarayanan static void intel_mid_reboot(void) 6905454c26SKuppuswamy Sathyanarayanan { 7005454c26SKuppuswamy Sathyanarayanan intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); 7105454c26SKuppuswamy Sathyanarayanan } 7205454c26SKuppuswamy Sathyanarayanan 73712b6aa8SKuppuswamy Sathyanarayanan static unsigned long __init intel_mid_calibrate_tsc(void) 7405454c26SKuppuswamy Sathyanarayanan { 7505454c26SKuppuswamy Sathyanarayanan unsigned long fast_calibrate; 7605454c26SKuppuswamy Sathyanarayanan u32 lo, hi, ratio, fsb; 7705454c26SKuppuswamy Sathyanarayanan 7805454c26SKuppuswamy Sathyanarayanan rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 7905454c26SKuppuswamy Sathyanarayanan pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi); 8005454c26SKuppuswamy Sathyanarayanan ratio = (hi >> 8) & 0x1f; 8105454c26SKuppuswamy Sathyanarayanan pr_debug("ratio is %d\n", ratio); 8205454c26SKuppuswamy Sathyanarayanan if (!ratio) { 8305454c26SKuppuswamy Sathyanarayanan pr_err("read a zero ratio, should be incorrect!\n"); 8405454c26SKuppuswamy Sathyanarayanan pr_err("force tsc ratio to 16 ...\n"); 8505454c26SKuppuswamy Sathyanarayanan ratio = 16; 8605454c26SKuppuswamy Sathyanarayanan } 8705454c26SKuppuswamy Sathyanarayanan rdmsr(MSR_FSB_FREQ, lo, hi); 8805454c26SKuppuswamy Sathyanarayanan if ((lo & 0x7) == 0x7) 8905454c26SKuppuswamy Sathyanarayanan fsb = PENWELL_FSB_FREQ_83SKU; 9005454c26SKuppuswamy Sathyanarayanan else 9105454c26SKuppuswamy Sathyanarayanan fsb = PENWELL_FSB_FREQ_100SKU; 9205454c26SKuppuswamy Sathyanarayanan fast_calibrate = ratio * fsb; 9305454c26SKuppuswamy Sathyanarayanan pr_debug("read penwell tsc %lu khz\n", fast_calibrate); 9405454c26SKuppuswamy Sathyanarayanan lapic_timer_frequency = fsb * 1000 / HZ; 9505454c26SKuppuswamy Sathyanarayanan /* mark tsc clocksource as reliable */ 9605454c26SKuppuswamy Sathyanarayanan set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); 9705454c26SKuppuswamy Sathyanarayanan 9805454c26SKuppuswamy Sathyanarayanan if (fast_calibrate) 9905454c26SKuppuswamy Sathyanarayanan return fast_calibrate; 10005454c26SKuppuswamy Sathyanarayanan 10105454c26SKuppuswamy Sathyanarayanan return 0; 10205454c26SKuppuswamy Sathyanarayanan } 10305454c26SKuppuswamy Sathyanarayanan 104712b6aa8SKuppuswamy Sathyanarayanan static void __init intel_mid_time_init(void) 10505454c26SKuppuswamy Sathyanarayanan { 10605454c26SKuppuswamy Sathyanarayanan sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); 107712b6aa8SKuppuswamy Sathyanarayanan switch (intel_mid_timer_options) { 108712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_APBT_ONLY: 10905454c26SKuppuswamy Sathyanarayanan break; 110712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_LAPIC_APBT: 11105454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 11205454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 11305454c26SKuppuswamy Sathyanarayanan break; 11405454c26SKuppuswamy Sathyanarayanan default: 11505454c26SKuppuswamy Sathyanarayanan if (!boot_cpu_has(X86_FEATURE_ARAT)) 11605454c26SKuppuswamy Sathyanarayanan break; 11705454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 11805454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 11905454c26SKuppuswamy Sathyanarayanan return; 12005454c26SKuppuswamy Sathyanarayanan } 12105454c26SKuppuswamy Sathyanarayanan /* we need at least one APB timer */ 12205454c26SKuppuswamy Sathyanarayanan pre_init_apic_IRQ0(); 12305454c26SKuppuswamy Sathyanarayanan apbt_time_init(); 12405454c26SKuppuswamy Sathyanarayanan } 12505454c26SKuppuswamy Sathyanarayanan 126aeeca404SPaul Gortmaker static void intel_mid_arch_setup(void) 12705454c26SKuppuswamy Sathyanarayanan { 12805454c26SKuppuswamy Sathyanarayanan if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27) 129712b6aa8SKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 13005454c26SKuppuswamy Sathyanarayanan else { 13105454c26SKuppuswamy Sathyanarayanan pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", 13205454c26SKuppuswamy Sathyanarayanan boot_cpu_data.x86, boot_cpu_data.x86_model); 133712b6aa8SKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 13405454c26SKuppuswamy Sathyanarayanan } 13505454c26SKuppuswamy Sathyanarayanan } 13605454c26SKuppuswamy Sathyanarayanan 13705454c26SKuppuswamy Sathyanarayanan /* MID systems don't have i8042 controller */ 138712b6aa8SKuppuswamy Sathyanarayanan static int intel_mid_i8042_detect(void) 13905454c26SKuppuswamy Sathyanarayanan { 14005454c26SKuppuswamy Sathyanarayanan return 0; 14105454c26SKuppuswamy Sathyanarayanan } 14205454c26SKuppuswamy Sathyanarayanan 14305454c26SKuppuswamy Sathyanarayanan /* 14405454c26SKuppuswamy Sathyanarayanan * Moorestown does not have external NMI source nor port 0x61 to report 14505454c26SKuppuswamy Sathyanarayanan * NMI status. The possible NMI sources are from pmu as a result of NMI 14605454c26SKuppuswamy Sathyanarayanan * watchdog or lock debug. Reading io port 0x61 results in 0xff which 14705454c26SKuppuswamy Sathyanarayanan * misled NMI handler. 14805454c26SKuppuswamy Sathyanarayanan */ 149712b6aa8SKuppuswamy Sathyanarayanan static unsigned char intel_mid_get_nmi_reason(void) 15005454c26SKuppuswamy Sathyanarayanan { 15105454c26SKuppuswamy Sathyanarayanan return 0; 15205454c26SKuppuswamy Sathyanarayanan } 15305454c26SKuppuswamy Sathyanarayanan 15405454c26SKuppuswamy Sathyanarayanan /* 15505454c26SKuppuswamy Sathyanarayanan * Moorestown specific x86_init function overrides and early setup 15605454c26SKuppuswamy Sathyanarayanan * calls. 15705454c26SKuppuswamy Sathyanarayanan */ 158712b6aa8SKuppuswamy Sathyanarayanan void __init x86_intel_mid_early_setup(void) 15905454c26SKuppuswamy Sathyanarayanan { 16005454c26SKuppuswamy Sathyanarayanan x86_init.resources.probe_roms = x86_init_noop; 16105454c26SKuppuswamy Sathyanarayanan x86_init.resources.reserve_resources = x86_init_noop; 16205454c26SKuppuswamy Sathyanarayanan 163712b6aa8SKuppuswamy Sathyanarayanan x86_init.timers.timer_init = intel_mid_time_init; 16405454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = x86_init_noop; 16505454c26SKuppuswamy Sathyanarayanan 16605454c26SKuppuswamy Sathyanarayanan x86_init.irqs.pre_vector_init = x86_init_noop; 16705454c26SKuppuswamy Sathyanarayanan 168712b6aa8SKuppuswamy Sathyanarayanan x86_init.oem.arch_setup = intel_mid_arch_setup; 16905454c26SKuppuswamy Sathyanarayanan 17005454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; 17105454c26SKuppuswamy Sathyanarayanan 172712b6aa8SKuppuswamy Sathyanarayanan x86_platform.calibrate_tsc = intel_mid_calibrate_tsc; 173712b6aa8SKuppuswamy Sathyanarayanan x86_platform.i8042_detect = intel_mid_i8042_detect; 174712b6aa8SKuppuswamy Sathyanarayanan x86_init.timers.wallclock_init = intel_mid_rtc_init; 175712b6aa8SKuppuswamy Sathyanarayanan x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; 17605454c26SKuppuswamy Sathyanarayanan 177712b6aa8SKuppuswamy Sathyanarayanan x86_init.pci.init = intel_mid_pci_init; 17805454c26SKuppuswamy Sathyanarayanan x86_init.pci.fixup_irqs = x86_init_noop; 17905454c26SKuppuswamy Sathyanarayanan 18005454c26SKuppuswamy Sathyanarayanan legacy_pic = &null_legacy_pic; 18105454c26SKuppuswamy Sathyanarayanan 182712b6aa8SKuppuswamy Sathyanarayanan pm_power_off = intel_mid_power_off; 183712b6aa8SKuppuswamy Sathyanarayanan machine_ops.emergency_restart = intel_mid_reboot; 18405454c26SKuppuswamy Sathyanarayanan 18505454c26SKuppuswamy Sathyanarayanan /* Avoid searching for BIOS MP tables */ 18605454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.find_smp_config = x86_init_noop; 18705454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.get_smp_config = x86_init_uint_noop; 18805454c26SKuppuswamy Sathyanarayanan set_bit(MP_BUS_ISA, mp_bus_not_pci); 18905454c26SKuppuswamy Sathyanarayanan } 19005454c26SKuppuswamy Sathyanarayanan 19105454c26SKuppuswamy Sathyanarayanan /* 19205454c26SKuppuswamy Sathyanarayanan * if user does not want to use per CPU apb timer, just give it a lower rating 19305454c26SKuppuswamy Sathyanarayanan * than local apic timer and skip the late per cpu timer init. 19405454c26SKuppuswamy Sathyanarayanan */ 195712b6aa8SKuppuswamy Sathyanarayanan static inline int __init setup_x86_intel_mid_timer(char *arg) 19605454c26SKuppuswamy Sathyanarayanan { 19705454c26SKuppuswamy Sathyanarayanan if (!arg) 19805454c26SKuppuswamy Sathyanarayanan return -EINVAL; 19905454c26SKuppuswamy Sathyanarayanan 20005454c26SKuppuswamy Sathyanarayanan if (strcmp("apbt_only", arg) == 0) 201712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; 20205454c26SKuppuswamy Sathyanarayanan else if (strcmp("lapic_and_apbt", arg) == 0) 203712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; 20405454c26SKuppuswamy Sathyanarayanan else { 205712b6aa8SKuppuswamy Sathyanarayanan pr_warn("X86 INTEL_MID timer option %s not recognised" 206712b6aa8SKuppuswamy Sathyanarayanan " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", 20705454c26SKuppuswamy Sathyanarayanan arg); 20805454c26SKuppuswamy Sathyanarayanan return -EINVAL; 20905454c26SKuppuswamy Sathyanarayanan } 21005454c26SKuppuswamy Sathyanarayanan return 0; 21105454c26SKuppuswamy Sathyanarayanan } 212712b6aa8SKuppuswamy Sathyanarayanan __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); 21305454c26SKuppuswamy Sathyanarayanan 214