105454c26SKuppuswamy Sathyanarayanan /* 205454c26SKuppuswamy Sathyanarayanan * intel-mid.c: Intel MID platform setup code 305454c26SKuppuswamy Sathyanarayanan * 405454c26SKuppuswamy Sathyanarayanan * (C) Copyright 2008, 2012 Intel Corporation 505454c26SKuppuswamy Sathyanarayanan * Author: Jacob Pan (jacob.jun.pan@intel.com) 605454c26SKuppuswamy Sathyanarayanan * Author: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@intel.com> 705454c26SKuppuswamy Sathyanarayanan * 805454c26SKuppuswamy Sathyanarayanan * This program is free software; you can redistribute it and/or 905454c26SKuppuswamy Sathyanarayanan * modify it under the terms of the GNU General Public License 1005454c26SKuppuswamy Sathyanarayanan * as published by the Free Software Foundation; version 2 1105454c26SKuppuswamy Sathyanarayanan * of the License. 1205454c26SKuppuswamy Sathyanarayanan */ 1305454c26SKuppuswamy Sathyanarayanan 14712b6aa8SKuppuswamy Sathyanarayanan #define pr_fmt(fmt) "intel_mid: " fmt 1505454c26SKuppuswamy Sathyanarayanan 1605454c26SKuppuswamy Sathyanarayanan #include <linux/init.h> 1705454c26SKuppuswamy Sathyanarayanan #include <linux/kernel.h> 1805454c26SKuppuswamy Sathyanarayanan #include <linux/interrupt.h> 1905454c26SKuppuswamy Sathyanarayanan #include <linux/scatterlist.h> 2005454c26SKuppuswamy Sathyanarayanan #include <linux/sfi.h> 2105454c26SKuppuswamy Sathyanarayanan #include <linux/irq.h> 2205454c26SKuppuswamy Sathyanarayanan #include <linux/module.h> 2305454c26SKuppuswamy Sathyanarayanan #include <linux/notifier.h> 2405454c26SKuppuswamy Sathyanarayanan 2505454c26SKuppuswamy Sathyanarayanan #include <asm/setup.h> 2605454c26SKuppuswamy Sathyanarayanan #include <asm/mpspec_def.h> 2705454c26SKuppuswamy Sathyanarayanan #include <asm/hw_irq.h> 2805454c26SKuppuswamy Sathyanarayanan #include <asm/apic.h> 2905454c26SKuppuswamy Sathyanarayanan #include <asm/io_apic.h> 3005454c26SKuppuswamy Sathyanarayanan #include <asm/intel-mid.h> 3105454c26SKuppuswamy Sathyanarayanan #include <asm/intel_mid_vrtc.h> 3205454c26SKuppuswamy Sathyanarayanan #include <asm/io.h> 3305454c26SKuppuswamy Sathyanarayanan #include <asm/i8259.h> 3405454c26SKuppuswamy Sathyanarayanan #include <asm/intel_scu_ipc.h> 3505454c26SKuppuswamy Sathyanarayanan #include <asm/apb_timer.h> 3605454c26SKuppuswamy Sathyanarayanan #include <asm/reboot.h> 3705454c26SKuppuswamy Sathyanarayanan 38ecd6910dSDavid Cohen #include "intel_mid_weak_decls.h" 39ecd6910dSDavid Cohen 4005454c26SKuppuswamy Sathyanarayanan /* 4105454c26SKuppuswamy Sathyanarayanan * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock, 42712b6aa8SKuppuswamy Sathyanarayanan * cmdline option x86_intel_mid_timer can be used to override the configuration 4305454c26SKuppuswamy Sathyanarayanan * to prefer one or the other. 4405454c26SKuppuswamy Sathyanarayanan * at runtime, there are basically three timer configurations: 4505454c26SKuppuswamy Sathyanarayanan * 1. per cpu apbt clock only 4605454c26SKuppuswamy Sathyanarayanan * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only 4705454c26SKuppuswamy Sathyanarayanan * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast. 4805454c26SKuppuswamy Sathyanarayanan * 4905454c26SKuppuswamy Sathyanarayanan * by default (without cmdline option), platform code first detects cpu type 5005454c26SKuppuswamy Sathyanarayanan * to see if we are on lincroft or penwell, then set up both lapic or apbt 5105454c26SKuppuswamy Sathyanarayanan * clocks accordingly. 5205454c26SKuppuswamy Sathyanarayanan * i.e. by default, medfield uses configuration #2, moorestown uses #1. 5305454c26SKuppuswamy Sathyanarayanan * config #3 is supported but not recommended on medfield. 5405454c26SKuppuswamy Sathyanarayanan * 5505454c26SKuppuswamy Sathyanarayanan * rating and feature summary: 5605454c26SKuppuswamy Sathyanarayanan * lapic (with C3STOP) --------- 100 5705454c26SKuppuswamy Sathyanarayanan * apbt (always-on) ------------ 110 5805454c26SKuppuswamy Sathyanarayanan * lapic (always-on,ARAT) ------ 150 5905454c26SKuppuswamy Sathyanarayanan */ 6005454c26SKuppuswamy Sathyanarayanan 61712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_timer_options intel_mid_timer_options; 6205454c26SKuppuswamy Sathyanarayanan 6385611e3fSKuppuswamy Sathyanarayanan /* intel_mid_ops to store sub arch ops */ 6485611e3fSKuppuswamy Sathyanarayanan struct intel_mid_ops *intel_mid_ops; 6585611e3fSKuppuswamy Sathyanarayanan /* getter function for sub arch ops*/ 6685611e3fSKuppuswamy Sathyanarayanan static void *(*get_intel_mid_ops[])(void) = INTEL_MID_OPS_INIT; 67712b6aa8SKuppuswamy Sathyanarayanan enum intel_mid_cpu_type __intel_mid_cpu_chip; 68712b6aa8SKuppuswamy Sathyanarayanan EXPORT_SYMBOL_GPL(__intel_mid_cpu_chip); 6905454c26SKuppuswamy Sathyanarayanan 7085611e3fSKuppuswamy Sathyanarayanan static void intel_mid_power_off(void) 7185611e3fSKuppuswamy Sathyanarayanan { 7285611e3fSKuppuswamy Sathyanarayanan }; 7385611e3fSKuppuswamy Sathyanarayanan 74712b6aa8SKuppuswamy Sathyanarayanan static void intel_mid_reboot(void) 7505454c26SKuppuswamy Sathyanarayanan { 7605454c26SKuppuswamy Sathyanarayanan intel_scu_ipc_simple_command(IPCMSG_COLD_BOOT, 0); 7705454c26SKuppuswamy Sathyanarayanan } 7805454c26SKuppuswamy Sathyanarayanan 7985611e3fSKuppuswamy Sathyanarayanan static unsigned long __init intel_mid_calibrate_tsc(void) 8085611e3fSKuppuswamy Sathyanarayanan { 8185611e3fSKuppuswamy Sathyanarayanan return 0; 8285611e3fSKuppuswamy Sathyanarayanan } 8385611e3fSKuppuswamy Sathyanarayanan 84712b6aa8SKuppuswamy Sathyanarayanan static void __init intel_mid_time_init(void) 8505454c26SKuppuswamy Sathyanarayanan { 8605454c26SKuppuswamy Sathyanarayanan sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr); 87712b6aa8SKuppuswamy Sathyanarayanan switch (intel_mid_timer_options) { 88712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_APBT_ONLY: 8905454c26SKuppuswamy Sathyanarayanan break; 90712b6aa8SKuppuswamy Sathyanarayanan case INTEL_MID_TIMER_LAPIC_APBT: 9105454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 9205454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 9305454c26SKuppuswamy Sathyanarayanan break; 9405454c26SKuppuswamy Sathyanarayanan default: 9505454c26SKuppuswamy Sathyanarayanan if (!boot_cpu_has(X86_FEATURE_ARAT)) 9605454c26SKuppuswamy Sathyanarayanan break; 9705454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock; 9805454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock; 9905454c26SKuppuswamy Sathyanarayanan return; 10005454c26SKuppuswamy Sathyanarayanan } 10105454c26SKuppuswamy Sathyanarayanan /* we need at least one APB timer */ 10205454c26SKuppuswamy Sathyanarayanan pre_init_apic_IRQ0(); 10305454c26SKuppuswamy Sathyanarayanan apbt_time_init(); 10405454c26SKuppuswamy Sathyanarayanan } 10505454c26SKuppuswamy Sathyanarayanan 106aeeca404SPaul Gortmaker static void intel_mid_arch_setup(void) 10705454c26SKuppuswamy Sathyanarayanan { 10885611e3fSKuppuswamy Sathyanarayanan if (boot_cpu_data.x86 != 6) { 10905454c26SKuppuswamy Sathyanarayanan pr_err("Unknown Intel MID CPU (%d:%d), default to Penwell\n", 11005454c26SKuppuswamy Sathyanarayanan boot_cpu_data.x86, boot_cpu_data.x86_model); 111712b6aa8SKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 11285611e3fSKuppuswamy Sathyanarayanan goto out; 11305454c26SKuppuswamy Sathyanarayanan } 11485611e3fSKuppuswamy Sathyanarayanan 11585611e3fSKuppuswamy Sathyanarayanan switch (boot_cpu_data.x86_model) { 11685611e3fSKuppuswamy Sathyanarayanan case 0x35: 11785611e3fSKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_CLOVERVIEW; 11885611e3fSKuppuswamy Sathyanarayanan break; 119bc20aa48SDavid Cohen case 0x3C: 120bc20aa48SDavid Cohen case 0x4A: 121bc20aa48SDavid Cohen __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_TANGIER; 122bc20aa48SDavid Cohen break; 12385611e3fSKuppuswamy Sathyanarayanan case 0x27: 12485611e3fSKuppuswamy Sathyanarayanan default: 12585611e3fSKuppuswamy Sathyanarayanan __intel_mid_cpu_chip = INTEL_MID_CPU_CHIP_PENWELL; 12685611e3fSKuppuswamy Sathyanarayanan break; 12785611e3fSKuppuswamy Sathyanarayanan } 12885611e3fSKuppuswamy Sathyanarayanan 12985611e3fSKuppuswamy Sathyanarayanan if (__intel_mid_cpu_chip < MAX_CPU_OPS(get_intel_mid_ops)) 13085611e3fSKuppuswamy Sathyanarayanan intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); 13185611e3fSKuppuswamy Sathyanarayanan else { 13285611e3fSKuppuswamy Sathyanarayanan intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); 133579deee5SYannick Guerrini pr_info("ARCH: Unknown SoC, assuming PENWELL!\n"); 13485611e3fSKuppuswamy Sathyanarayanan } 13585611e3fSKuppuswamy Sathyanarayanan 13685611e3fSKuppuswamy Sathyanarayanan out: 13785611e3fSKuppuswamy Sathyanarayanan if (intel_mid_ops->arch_setup) 13885611e3fSKuppuswamy Sathyanarayanan intel_mid_ops->arch_setup(); 13905454c26SKuppuswamy Sathyanarayanan } 14005454c26SKuppuswamy Sathyanarayanan 14105454c26SKuppuswamy Sathyanarayanan /* MID systems don't have i8042 controller */ 142712b6aa8SKuppuswamy Sathyanarayanan static int intel_mid_i8042_detect(void) 14305454c26SKuppuswamy Sathyanarayanan { 14405454c26SKuppuswamy Sathyanarayanan return 0; 14505454c26SKuppuswamy Sathyanarayanan } 14605454c26SKuppuswamy Sathyanarayanan 14705454c26SKuppuswamy Sathyanarayanan /* 14805454c26SKuppuswamy Sathyanarayanan * Moorestown does not have external NMI source nor port 0x61 to report 14905454c26SKuppuswamy Sathyanarayanan * NMI status. The possible NMI sources are from pmu as a result of NMI 15005454c26SKuppuswamy Sathyanarayanan * watchdog or lock debug. Reading io port 0x61 results in 0xff which 15105454c26SKuppuswamy Sathyanarayanan * misled NMI handler. 15205454c26SKuppuswamy Sathyanarayanan */ 153712b6aa8SKuppuswamy Sathyanarayanan static unsigned char intel_mid_get_nmi_reason(void) 15405454c26SKuppuswamy Sathyanarayanan { 15505454c26SKuppuswamy Sathyanarayanan return 0; 15605454c26SKuppuswamy Sathyanarayanan } 15705454c26SKuppuswamy Sathyanarayanan 15805454c26SKuppuswamy Sathyanarayanan /* 15905454c26SKuppuswamy Sathyanarayanan * Moorestown specific x86_init function overrides and early setup 16005454c26SKuppuswamy Sathyanarayanan * calls. 16105454c26SKuppuswamy Sathyanarayanan */ 162712b6aa8SKuppuswamy Sathyanarayanan void __init x86_intel_mid_early_setup(void) 16305454c26SKuppuswamy Sathyanarayanan { 16405454c26SKuppuswamy Sathyanarayanan x86_init.resources.probe_roms = x86_init_noop; 16505454c26SKuppuswamy Sathyanarayanan x86_init.resources.reserve_resources = x86_init_noop; 16605454c26SKuppuswamy Sathyanarayanan 167712b6aa8SKuppuswamy Sathyanarayanan x86_init.timers.timer_init = intel_mid_time_init; 16805454c26SKuppuswamy Sathyanarayanan x86_init.timers.setup_percpu_clockev = x86_init_noop; 16905454c26SKuppuswamy Sathyanarayanan 17005454c26SKuppuswamy Sathyanarayanan x86_init.irqs.pre_vector_init = x86_init_noop; 17105454c26SKuppuswamy Sathyanarayanan 172712b6aa8SKuppuswamy Sathyanarayanan x86_init.oem.arch_setup = intel_mid_arch_setup; 17305454c26SKuppuswamy Sathyanarayanan 17405454c26SKuppuswamy Sathyanarayanan x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock; 17505454c26SKuppuswamy Sathyanarayanan 176712b6aa8SKuppuswamy Sathyanarayanan x86_platform.calibrate_tsc = intel_mid_calibrate_tsc; 177712b6aa8SKuppuswamy Sathyanarayanan x86_platform.i8042_detect = intel_mid_i8042_detect; 178712b6aa8SKuppuswamy Sathyanarayanan x86_init.timers.wallclock_init = intel_mid_rtc_init; 179712b6aa8SKuppuswamy Sathyanarayanan x86_platform.get_nmi_reason = intel_mid_get_nmi_reason; 18005454c26SKuppuswamy Sathyanarayanan 181712b6aa8SKuppuswamy Sathyanarayanan x86_init.pci.init = intel_mid_pci_init; 18205454c26SKuppuswamy Sathyanarayanan x86_init.pci.fixup_irqs = x86_init_noop; 18305454c26SKuppuswamy Sathyanarayanan 18405454c26SKuppuswamy Sathyanarayanan legacy_pic = &null_legacy_pic; 18505454c26SKuppuswamy Sathyanarayanan 186712b6aa8SKuppuswamy Sathyanarayanan pm_power_off = intel_mid_power_off; 187712b6aa8SKuppuswamy Sathyanarayanan machine_ops.emergency_restart = intel_mid_reboot; 18805454c26SKuppuswamy Sathyanarayanan 18905454c26SKuppuswamy Sathyanarayanan /* Avoid searching for BIOS MP tables */ 19005454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.find_smp_config = x86_init_noop; 19105454c26SKuppuswamy Sathyanarayanan x86_init.mpparse.get_smp_config = x86_init_uint_noop; 19205454c26SKuppuswamy Sathyanarayanan set_bit(MP_BUS_ISA, mp_bus_not_pci); 19305454c26SKuppuswamy Sathyanarayanan } 19405454c26SKuppuswamy Sathyanarayanan 19505454c26SKuppuswamy Sathyanarayanan /* 19605454c26SKuppuswamy Sathyanarayanan * if user does not want to use per CPU apb timer, just give it a lower rating 19705454c26SKuppuswamy Sathyanarayanan * than local apic timer and skip the late per cpu timer init. 19805454c26SKuppuswamy Sathyanarayanan */ 199712b6aa8SKuppuswamy Sathyanarayanan static inline int __init setup_x86_intel_mid_timer(char *arg) 20005454c26SKuppuswamy Sathyanarayanan { 20105454c26SKuppuswamy Sathyanarayanan if (!arg) 20205454c26SKuppuswamy Sathyanarayanan return -EINVAL; 20305454c26SKuppuswamy Sathyanarayanan 20405454c26SKuppuswamy Sathyanarayanan if (strcmp("apbt_only", arg) == 0) 205712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_APBT_ONLY; 20605454c26SKuppuswamy Sathyanarayanan else if (strcmp("lapic_and_apbt", arg) == 0) 207712b6aa8SKuppuswamy Sathyanarayanan intel_mid_timer_options = INTEL_MID_TIMER_LAPIC_APBT; 20805454c26SKuppuswamy Sathyanarayanan else { 209712b6aa8SKuppuswamy Sathyanarayanan pr_warn("X86 INTEL_MID timer option %s not recognised" 210712b6aa8SKuppuswamy Sathyanarayanan " use x86_intel_mid_timer=apbt_only or lapic_and_apbt\n", 21105454c26SKuppuswamy Sathyanarayanan arg); 21205454c26SKuppuswamy Sathyanarayanan return -EINVAL; 21305454c26SKuppuswamy Sathyanarayanan } 21405454c26SKuppuswamy Sathyanarayanan return 0; 21505454c26SKuppuswamy Sathyanarayanan } 216712b6aa8SKuppuswamy Sathyanarayanan __setup("x86_intel_mid_timer=", setup_x86_intel_mid_timer); 21705454c26SKuppuswamy Sathyanarayanan 218