1 /* 2 * Low-Level PCI Support for PC -- Routing of Interrupts 3 * 4 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 5 */ 6 7 #include <linux/types.h> 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/slab.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <asm/io_apic.h> 17 #include <linux/irq.h> 18 #include <linux/acpi.h> 19 20 #include "pci.h" 21 22 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 23 #define PIRQ_VERSION 0x0100 24 25 static int broken_hp_bios_irq9; 26 static int acer_tm360_irqrouting; 27 28 static struct irq_routing_table *pirq_table; 29 30 static int pirq_enable_irq(struct pci_dev *dev); 31 32 /* 33 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 34 * Avoid using: 13, 14 and 15 (FP error and IDE). 35 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 36 */ 37 unsigned int pcibios_irq_mask = 0xfff8; 38 39 static int pirq_penalty[16] = { 40 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 41 0, 0, 0, 0, 1000, 100000, 100000, 100000 42 }; 43 44 struct irq_router { 45 char *name; 46 u16 vendor, device; 47 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 48 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 49 int new); 50 }; 51 52 struct irq_router_handler { 53 u16 vendor; 54 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 55 }; 56 57 int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL; 58 void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; 59 60 /* 61 * Check passed address for the PCI IRQ Routing Table signature 62 * and perform checksum verification. 63 */ 64 65 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 66 { 67 struct irq_routing_table *rt; 68 int i; 69 u8 sum; 70 71 rt = (struct irq_routing_table *) addr; 72 if (rt->signature != PIRQ_SIGNATURE || 73 rt->version != PIRQ_VERSION || 74 rt->size % 16 || 75 rt->size < sizeof(struct irq_routing_table)) 76 return NULL; 77 sum = 0; 78 for (i = 0; i < rt->size; i++) 79 sum += addr[i]; 80 if (!sum) { 81 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 82 rt); 83 return rt; 84 } 85 return NULL; 86 } 87 88 89 90 /* 91 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 92 */ 93 94 static struct irq_routing_table * __init pirq_find_routing_table(void) 95 { 96 u8 *addr; 97 struct irq_routing_table *rt; 98 99 if (pirq_table_addr) { 100 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 101 if (rt) 102 return rt; 103 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 104 } 105 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 106 rt = pirq_check_routing_table(addr); 107 if (rt) 108 return rt; 109 } 110 return NULL; 111 } 112 113 /* 114 * If we have a IRQ routing table, use it to search for peer host 115 * bridges. It's a gross hack, but since there are no other known 116 * ways how to get a list of buses, we have to go this way. 117 */ 118 119 static void __init pirq_peer_trick(void) 120 { 121 struct irq_routing_table *rt = pirq_table; 122 u8 busmap[256]; 123 int i; 124 struct irq_info *e; 125 126 memset(busmap, 0, sizeof(busmap)); 127 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 128 e = &rt->slots[i]; 129 #ifdef DEBUG 130 { 131 int j; 132 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 133 for (j = 0; j < 4; j++) 134 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 135 DBG("\n"); 136 } 137 #endif 138 busmap[e->bus] = 1; 139 } 140 for (i = 1; i < 256; i++) { 141 int node; 142 if (!busmap[i] || pci_find_bus(0, i)) 143 continue; 144 node = get_mp_bus_to_node(i); 145 if (pci_scan_bus_on_node(i, &pci_root_ops, node)) 146 printk(KERN_INFO "PCI: Discovered primary peer " 147 "bus %02x [IRQ]\n", i); 148 } 149 pcibios_last_bus = -1; 150 } 151 152 /* 153 * Code for querying and setting of IRQ routes on various interrupt routers. 154 */ 155 156 void eisa_set_level_irq(unsigned int irq) 157 { 158 unsigned char mask = 1 << (irq & 7); 159 unsigned int port = 0x4d0 + (irq >> 3); 160 unsigned char val; 161 static u16 eisa_irq_mask; 162 163 if (irq >= 16 || (1 << irq) & eisa_irq_mask) 164 return; 165 166 eisa_irq_mask |= (1 << irq); 167 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 168 val = inb(port); 169 if (!(val & mask)) { 170 DBG(KERN_DEBUG " -> edge"); 171 outb(val | mask, port); 172 } 173 } 174 175 /* 176 * Common IRQ routing practice: nibbles in config space, 177 * offset by some magic constant. 178 */ 179 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 180 { 181 u8 x; 182 unsigned reg = offset + (nr >> 1); 183 184 pci_read_config_byte(router, reg, &x); 185 return (nr & 1) ? (x >> 4) : (x & 0xf); 186 } 187 188 static void write_config_nybble(struct pci_dev *router, unsigned offset, 189 unsigned nr, unsigned int val) 190 { 191 u8 x; 192 unsigned reg = offset + (nr >> 1); 193 194 pci_read_config_byte(router, reg, &x); 195 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 196 pci_write_config_byte(router, reg, x); 197 } 198 199 /* 200 * ALI pirq entries are damn ugly, and completely undocumented. 201 * This has been figured out from pirq tables, and it's not a pretty 202 * picture. 203 */ 204 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 205 { 206 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 207 208 WARN_ON_ONCE(pirq > 16); 209 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 210 } 211 212 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 213 { 214 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 215 unsigned int val = irqmap[irq]; 216 217 WARN_ON_ONCE(pirq > 16); 218 if (val) { 219 write_config_nybble(router, 0x48, pirq-1, val); 220 return 1; 221 } 222 return 0; 223 } 224 225 /* 226 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 227 * just a pointer to the config space. 228 */ 229 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 230 { 231 u8 x; 232 233 pci_read_config_byte(router, pirq, &x); 234 return (x < 16) ? x : 0; 235 } 236 237 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 238 { 239 pci_write_config_byte(router, pirq, irq); 240 return 1; 241 } 242 243 /* 244 * The VIA pirq rules are nibble-based, like ALI, 245 * but without the ugly irq number munging. 246 * However, PIRQD is in the upper instead of lower 4 bits. 247 */ 248 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 249 { 250 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 251 } 252 253 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 254 { 255 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 256 return 1; 257 } 258 259 /* 260 * The VIA pirq rules are nibble-based, like ALI, 261 * but without the ugly irq number munging. 262 * However, for 82C586, nibble map is different . 263 */ 264 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 265 { 266 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 267 268 WARN_ON_ONCE(pirq > 5); 269 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 270 } 271 272 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 273 { 274 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 275 276 WARN_ON_ONCE(pirq > 5); 277 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 278 return 1; 279 } 280 281 /* 282 * ITE 8330G pirq rules are nibble-based 283 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 284 * 2+3 are both mapped to irq 9 on my system 285 */ 286 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 287 { 288 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 289 290 WARN_ON_ONCE(pirq > 4); 291 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 292 } 293 294 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 295 { 296 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 297 298 WARN_ON_ONCE(pirq > 4); 299 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 300 return 1; 301 } 302 303 /* 304 * OPTI: high four bits are nibble pointer.. 305 * I wonder what the low bits do? 306 */ 307 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 308 { 309 return read_config_nybble(router, 0xb8, pirq >> 4); 310 } 311 312 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 313 { 314 write_config_nybble(router, 0xb8, pirq >> 4, irq); 315 return 1; 316 } 317 318 /* 319 * Cyrix: nibble offset 0x5C 320 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 321 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 322 */ 323 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 324 { 325 return read_config_nybble(router, 0x5C, (pirq-1)^1); 326 } 327 328 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 329 { 330 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 331 return 1; 332 } 333 334 /* 335 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 336 * We have to deal with the following issues here: 337 * - vendors have different ideas about the meaning of link values 338 * - some onboard devices (integrated in the chipset) have special 339 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 340 * - different revision of the router have a different layout for 341 * the routing registers, particularly for the onchip devices 342 * 343 * For all routing registers the common thing is we have one byte 344 * per routeable link which is defined as: 345 * bit 7 IRQ mapping enabled (0) or disabled (1) 346 * bits [6:4] reserved (sometimes used for onchip devices) 347 * bits [3:0] IRQ to map to 348 * allowed: 3-7, 9-12, 14-15 349 * reserved: 0, 1, 2, 8, 13 350 * 351 * The config-space registers located at 0x41/0x42/0x43/0x44 are 352 * always used to route the normal PCI INT A/B/C/D respectively. 353 * Apparently there are systems implementing PCI routing table using 354 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 355 * We try our best to handle both link mappings. 356 * 357 * Currently (2003-05-21) it appears most SiS chipsets follow the 358 * definition of routing registers from the SiS-5595 southbridge. 359 * According to the SiS 5595 datasheets the revision id's of the 360 * router (ISA-bridge) should be 0x01 or 0xb0. 361 * 362 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 363 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 364 * They seem to work with the current routing code. However there is 365 * some concern because of the two USB-OHCI HCs (original SiS 5595 366 * had only one). YMMV. 367 * 368 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 369 * 370 * 0x61: IDEIRQ: 371 * bits [6:5] must be written 01 372 * bit 4 channel-select primary (0), secondary (1) 373 * 374 * 0x62: USBIRQ: 375 * bit 6 OHCI function disabled (0), enabled (1) 376 * 377 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 378 * 379 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 380 * 381 * We support USBIRQ (in addition to INTA-INTD) and keep the 382 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 383 * 384 * Currently the only reported exception is the new SiS 65x chipset 385 * which includes the SiS 69x southbridge. Here we have the 85C503 386 * router revision 0x04 and there are changes in the register layout 387 * mostly related to the different USB HCs with USB 2.0 support. 388 * 389 * Onchip routing for router rev-id 0x04 (try-and-error observation) 390 * 391 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 392 * bit 6-4 are probably unused, not like 5595 393 */ 394 395 #define PIRQ_SIS_IRQ_MASK 0x0f 396 #define PIRQ_SIS_IRQ_DISABLE 0x80 397 #define PIRQ_SIS_USB_ENABLE 0x40 398 399 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 400 { 401 u8 x; 402 int reg; 403 404 reg = pirq; 405 if (reg >= 0x01 && reg <= 0x04) 406 reg += 0x40; 407 pci_read_config_byte(router, reg, &x); 408 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 409 } 410 411 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 412 { 413 u8 x; 414 int reg; 415 416 reg = pirq; 417 if (reg >= 0x01 && reg <= 0x04) 418 reg += 0x40; 419 pci_read_config_byte(router, reg, &x); 420 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 421 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 422 pci_write_config_byte(router, reg, x); 423 return 1; 424 } 425 426 427 /* 428 * VLSI: nibble offset 0x74 - educated guess due to routing table and 429 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 430 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 431 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 432 * for the busbridge to the docking station. 433 */ 434 435 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 436 { 437 WARN_ON_ONCE(pirq >= 9); 438 if (pirq > 8) { 439 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 440 return 0; 441 } 442 return read_config_nybble(router, 0x74, pirq-1); 443 } 444 445 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 446 { 447 WARN_ON_ONCE(pirq >= 9); 448 if (pirq > 8) { 449 printk(KERN_INFO "VLSI router pirq escape (%d)\n", pirq); 450 return 0; 451 } 452 write_config_nybble(router, 0x74, pirq-1, irq); 453 return 1; 454 } 455 456 /* 457 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 458 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 459 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 460 * register is a straight binary coding of desired PIC IRQ (low nibble). 461 * 462 * The 'link' value in the PIRQ table is already in the correct format 463 * for the Index register. There are some special index values: 464 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 465 * and 0x03 for SMBus. 466 */ 467 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 468 { 469 outb(pirq, 0xc00); 470 return inb(0xc01) & 0xf; 471 } 472 473 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 474 int pirq, int irq) 475 { 476 outb(pirq, 0xc00); 477 outb(irq, 0xc01); 478 return 1; 479 } 480 481 /* Support for AMD756 PCI IRQ Routing 482 * Jhon H. Caicedo <jhcaiced@osso.org.co> 483 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 484 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 485 * The AMD756 pirq rules are nibble-based 486 * offset 0x56 0-3 PIRQA 4-7 PIRQB 487 * offset 0x57 0-3 PIRQC 4-7 PIRQD 488 */ 489 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 490 { 491 u8 irq; 492 irq = 0; 493 if (pirq <= 4) 494 irq = read_config_nybble(router, 0x56, pirq - 1); 495 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d get irq : %2d\n", 496 dev->vendor, dev->device, pirq, irq); 497 return irq; 498 } 499 500 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 501 { 502 printk(KERN_INFO "AMD756: dev %04x:%04x, router pirq : %d SET irq : %2d\n", 503 dev->vendor, dev->device, pirq, irq); 504 if (pirq <= 4) 505 write_config_nybble(router, 0x56, pirq - 1, irq); 506 return 1; 507 } 508 509 /* 510 * PicoPower PT86C523 511 */ 512 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 513 { 514 outb(0x10 + ((pirq - 1) >> 1), 0x24); 515 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 516 } 517 518 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 519 int irq) 520 { 521 unsigned int x; 522 outb(0x10 + ((pirq - 1) >> 1), 0x24); 523 x = inb(0x26); 524 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 525 outb(x, 0x26); 526 return 1; 527 } 528 529 #ifdef CONFIG_PCI_BIOS 530 531 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 532 { 533 struct pci_dev *bridge; 534 int pin = pci_get_interrupt_pin(dev, &bridge); 535 return pcibios_set_irq_routing(bridge, pin, irq); 536 } 537 538 #endif 539 540 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 541 { 542 static struct pci_device_id __initdata pirq_440gx[] = { 543 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 544 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 545 { }, 546 }; 547 548 /* 440GX has a proprietary PIRQ router -- don't use it */ 549 if (pci_dev_present(pirq_440gx)) 550 return 0; 551 552 switch (device) { 553 case PCI_DEVICE_ID_INTEL_82371FB_0: 554 case PCI_DEVICE_ID_INTEL_82371SB_0: 555 case PCI_DEVICE_ID_INTEL_82371AB_0: 556 case PCI_DEVICE_ID_INTEL_82371MX: 557 case PCI_DEVICE_ID_INTEL_82443MX_0: 558 case PCI_DEVICE_ID_INTEL_82801AA_0: 559 case PCI_DEVICE_ID_INTEL_82801AB_0: 560 case PCI_DEVICE_ID_INTEL_82801BA_0: 561 case PCI_DEVICE_ID_INTEL_82801BA_10: 562 case PCI_DEVICE_ID_INTEL_82801CA_0: 563 case PCI_DEVICE_ID_INTEL_82801CA_12: 564 case PCI_DEVICE_ID_INTEL_82801DB_0: 565 case PCI_DEVICE_ID_INTEL_82801E_0: 566 case PCI_DEVICE_ID_INTEL_82801EB_0: 567 case PCI_DEVICE_ID_INTEL_ESB_1: 568 case PCI_DEVICE_ID_INTEL_ICH6_0: 569 case PCI_DEVICE_ID_INTEL_ICH6_1: 570 case PCI_DEVICE_ID_INTEL_ICH7_0: 571 case PCI_DEVICE_ID_INTEL_ICH7_1: 572 case PCI_DEVICE_ID_INTEL_ICH7_30: 573 case PCI_DEVICE_ID_INTEL_ICH7_31: 574 case PCI_DEVICE_ID_INTEL_ESB2_0: 575 case PCI_DEVICE_ID_INTEL_ICH8_0: 576 case PCI_DEVICE_ID_INTEL_ICH8_1: 577 case PCI_DEVICE_ID_INTEL_ICH8_2: 578 case PCI_DEVICE_ID_INTEL_ICH8_3: 579 case PCI_DEVICE_ID_INTEL_ICH8_4: 580 case PCI_DEVICE_ID_INTEL_ICH9_0: 581 case PCI_DEVICE_ID_INTEL_ICH9_1: 582 case PCI_DEVICE_ID_INTEL_ICH9_2: 583 case PCI_DEVICE_ID_INTEL_ICH9_3: 584 case PCI_DEVICE_ID_INTEL_ICH9_4: 585 case PCI_DEVICE_ID_INTEL_ICH9_5: 586 case PCI_DEVICE_ID_INTEL_TOLAPAI_0: 587 case PCI_DEVICE_ID_INTEL_ICH10_0: 588 case PCI_DEVICE_ID_INTEL_ICH10_1: 589 case PCI_DEVICE_ID_INTEL_ICH10_2: 590 case PCI_DEVICE_ID_INTEL_ICH10_3: 591 r->name = "PIIX/ICH"; 592 r->get = pirq_piix_get; 593 r->set = pirq_piix_set; 594 return 1; 595 } 596 return 0; 597 } 598 599 static __init int via_router_probe(struct irq_router *r, 600 struct pci_dev *router, u16 device) 601 { 602 /* FIXME: We should move some of the quirk fixup stuff here */ 603 604 /* 605 * workarounds for some buggy BIOSes 606 */ 607 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 608 switch (router->device) { 609 case PCI_DEVICE_ID_VIA_82C686: 610 /* 611 * Asus k7m bios wrongly reports 82C686A 612 * as 586-compatible 613 */ 614 device = PCI_DEVICE_ID_VIA_82C686; 615 break; 616 case PCI_DEVICE_ID_VIA_8235: 617 /** 618 * Asus a7v-x bios wrongly reports 8235 619 * as 586-compatible 620 */ 621 device = PCI_DEVICE_ID_VIA_8235; 622 break; 623 case PCI_DEVICE_ID_VIA_8237: 624 /** 625 * Asus a7v600 bios wrongly reports 8237 626 * as 586-compatible 627 */ 628 device = PCI_DEVICE_ID_VIA_8237; 629 break; 630 } 631 } 632 633 switch (device) { 634 case PCI_DEVICE_ID_VIA_82C586_0: 635 r->name = "VIA"; 636 r->get = pirq_via586_get; 637 r->set = pirq_via586_set; 638 return 1; 639 case PCI_DEVICE_ID_VIA_82C596: 640 case PCI_DEVICE_ID_VIA_82C686: 641 case PCI_DEVICE_ID_VIA_8231: 642 case PCI_DEVICE_ID_VIA_8233A: 643 case PCI_DEVICE_ID_VIA_8235: 644 case PCI_DEVICE_ID_VIA_8237: 645 /* FIXME: add new ones for 8233/5 */ 646 r->name = "VIA"; 647 r->get = pirq_via_get; 648 r->set = pirq_via_set; 649 return 1; 650 } 651 return 0; 652 } 653 654 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 655 { 656 switch (device) { 657 case PCI_DEVICE_ID_VLSI_82C534: 658 r->name = "VLSI 82C534"; 659 r->get = pirq_vlsi_get; 660 r->set = pirq_vlsi_set; 661 return 1; 662 } 663 return 0; 664 } 665 666 667 static __init int serverworks_router_probe(struct irq_router *r, 668 struct pci_dev *router, u16 device) 669 { 670 switch (device) { 671 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 672 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 673 r->name = "ServerWorks"; 674 r->get = pirq_serverworks_get; 675 r->set = pirq_serverworks_set; 676 return 1; 677 } 678 return 0; 679 } 680 681 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 682 { 683 if (device != PCI_DEVICE_ID_SI_503) 684 return 0; 685 686 r->name = "SIS"; 687 r->get = pirq_sis_get; 688 r->set = pirq_sis_set; 689 return 1; 690 } 691 692 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 693 { 694 switch (device) { 695 case PCI_DEVICE_ID_CYRIX_5520: 696 r->name = "NatSemi"; 697 r->get = pirq_cyrix_get; 698 r->set = pirq_cyrix_set; 699 return 1; 700 } 701 return 0; 702 } 703 704 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 705 { 706 switch (device) { 707 case PCI_DEVICE_ID_OPTI_82C700: 708 r->name = "OPTI"; 709 r->get = pirq_opti_get; 710 r->set = pirq_opti_set; 711 return 1; 712 } 713 return 0; 714 } 715 716 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 717 { 718 switch (device) { 719 case PCI_DEVICE_ID_ITE_IT8330G_0: 720 r->name = "ITE"; 721 r->get = pirq_ite_get; 722 r->set = pirq_ite_set; 723 return 1; 724 } 725 return 0; 726 } 727 728 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 729 { 730 switch (device) { 731 case PCI_DEVICE_ID_AL_M1533: 732 case PCI_DEVICE_ID_AL_M1563: 733 printk(KERN_DEBUG "PCI: Using ALI IRQ Router\n"); 734 r->name = "ALI"; 735 r->get = pirq_ali_get; 736 r->set = pirq_ali_set; 737 return 1; 738 } 739 return 0; 740 } 741 742 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 743 { 744 switch (device) { 745 case PCI_DEVICE_ID_AMD_VIPER_740B: 746 r->name = "AMD756"; 747 break; 748 case PCI_DEVICE_ID_AMD_VIPER_7413: 749 r->name = "AMD766"; 750 break; 751 case PCI_DEVICE_ID_AMD_VIPER_7443: 752 r->name = "AMD768"; 753 break; 754 default: 755 return 0; 756 } 757 r->get = pirq_amd756_get; 758 r->set = pirq_amd756_set; 759 return 1; 760 } 761 762 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 763 { 764 switch (device) { 765 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 766 r->name = "PicoPower PT86C523"; 767 r->get = pirq_pico_get; 768 r->set = pirq_pico_set; 769 return 1; 770 771 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 772 r->name = "PicoPower PT86C523 rev. BB+"; 773 r->get = pirq_pico_get; 774 r->set = pirq_pico_set; 775 return 1; 776 } 777 return 0; 778 } 779 780 static __initdata struct irq_router_handler pirq_routers[] = { 781 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 782 { PCI_VENDOR_ID_AL, ali_router_probe }, 783 { PCI_VENDOR_ID_ITE, ite_router_probe }, 784 { PCI_VENDOR_ID_VIA, via_router_probe }, 785 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 786 { PCI_VENDOR_ID_SI, sis_router_probe }, 787 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 788 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 789 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 790 { PCI_VENDOR_ID_AMD, amd_router_probe }, 791 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 792 /* Someone with docs needs to add the ATI Radeon IGP */ 793 { 0, NULL } 794 }; 795 static struct irq_router pirq_router; 796 static struct pci_dev *pirq_router_dev; 797 798 799 /* 800 * FIXME: should we have an option to say "generic for 801 * chipset" ? 802 */ 803 804 static void __init pirq_find_router(struct irq_router *r) 805 { 806 struct irq_routing_table *rt = pirq_table; 807 struct irq_router_handler *h; 808 809 #ifdef CONFIG_PCI_BIOS 810 if (!rt->signature) { 811 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 812 r->set = pirq_bios_set; 813 r->name = "BIOS"; 814 return; 815 } 816 #endif 817 818 /* Default unless a driver reloads it */ 819 r->name = "default"; 820 r->get = NULL; 821 r->set = NULL; 822 823 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for %04x:%04x\n", 824 rt->rtr_vendor, rt->rtr_device); 825 826 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn); 827 if (!pirq_router_dev) { 828 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 829 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 830 return; 831 } 832 833 for (h = pirq_routers; h->vendor; h++) { 834 /* First look for a router match */ 835 if (rt->rtr_vendor == h->vendor && 836 h->probe(r, pirq_router_dev, rt->rtr_device)) 837 break; 838 /* Fall back to a device match */ 839 if (pirq_router_dev->vendor == h->vendor && 840 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 841 break; 842 } 843 printk(KERN_INFO "PCI: Using IRQ router %s [%04x/%04x] at %s\n", 844 pirq_router.name, 845 pirq_router_dev->vendor, 846 pirq_router_dev->device, 847 pci_name(pirq_router_dev)); 848 849 /* The device remains referenced for the kernel lifetime */ 850 } 851 852 static struct irq_info *pirq_get_info(struct pci_dev *dev) 853 { 854 struct irq_routing_table *rt = pirq_table; 855 int entries = (rt->size - sizeof(struct irq_routing_table)) / 856 sizeof(struct irq_info); 857 struct irq_info *info; 858 859 for (info = rt->slots; entries--; info++) 860 if (info->bus == dev->bus->number && 861 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 862 return info; 863 return NULL; 864 } 865 866 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 867 { 868 u8 pin; 869 struct irq_info *info; 870 int i, pirq, newirq; 871 int irq = 0; 872 u32 mask; 873 struct irq_router *r = &pirq_router; 874 struct pci_dev *dev2 = NULL; 875 char *msg = NULL; 876 877 /* Find IRQ pin */ 878 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 879 if (!pin) { 880 DBG(KERN_DEBUG " -> no interrupt pin\n"); 881 return 0; 882 } 883 pin = pin - 1; 884 885 /* Find IRQ routing entry */ 886 887 if (!pirq_table) 888 return 0; 889 890 DBG(KERN_DEBUG "IRQ for %s[%c]", pci_name(dev), 'A' + pin); 891 info = pirq_get_info(dev); 892 if (!info) { 893 DBG(" -> not found in routing table\n" KERN_DEBUG); 894 return 0; 895 } 896 pirq = info->irq[pin].link; 897 mask = info->irq[pin].bitmap; 898 if (!pirq) { 899 DBG(" -> not routed\n" KERN_DEBUG); 900 return 0; 901 } 902 DBG(" -> PIRQ %02x, mask %04x, excl %04x", pirq, mask, 903 pirq_table->exclusive_irqs); 904 mask &= pcibios_irq_mask; 905 906 /* Work around broken HP Pavilion Notebooks which assign USB to 907 IRQ 9 even though it is actually wired to IRQ 11 */ 908 909 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 910 dev->irq = 11; 911 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 912 r->set(pirq_router_dev, dev, pirq, 11); 913 } 914 915 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 916 if (acer_tm360_irqrouting && dev->irq == 11 && 917 dev->vendor == PCI_VENDOR_ID_O2) { 918 pirq = 0x68; 919 mask = 0x400; 920 dev->irq = r->get(pirq_router_dev, dev, pirq); 921 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 922 } 923 924 /* 925 * Find the best IRQ to assign: use the one 926 * reported by the device if possible. 927 */ 928 newirq = dev->irq; 929 if (newirq && !((1 << newirq) & mask)) { 930 if (pci_probe & PCI_USE_PIRQ_MASK) 931 newirq = 0; 932 else 933 printk("\n" KERN_WARNING 934 "PCI: IRQ %i for device %s doesn't match PIRQ mask - try pci=usepirqmask\n" 935 KERN_DEBUG, newirq, 936 pci_name(dev)); 937 } 938 if (!newirq && assign) { 939 for (i = 0; i < 16; i++) { 940 if (!(mask & (1 << i))) 941 continue; 942 if (pirq_penalty[i] < pirq_penalty[newirq] && 943 can_request_irq(i, IRQF_SHARED)) 944 newirq = i; 945 } 946 } 947 DBG(" -> newirq=%d", newirq); 948 949 /* Check if it is hardcoded */ 950 if ((pirq & 0xf0) == 0xf0) { 951 irq = pirq & 0xf; 952 DBG(" -> hardcoded IRQ %d\n", irq); 953 msg = "Hardcoded"; 954 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 955 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 956 DBG(" -> got IRQ %d\n", irq); 957 msg = "Found"; 958 eisa_set_level_irq(irq); 959 } else if (newirq && r->set && 960 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 961 DBG(" -> assigning IRQ %d", newirq); 962 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 963 eisa_set_level_irq(newirq); 964 DBG(" ... OK\n"); 965 msg = "Assigned"; 966 irq = newirq; 967 } 968 } 969 970 if (!irq) { 971 DBG(" ... failed\n"); 972 if (newirq && mask == (1 << newirq)) { 973 msg = "Guessed"; 974 irq = newirq; 975 } else 976 return 0; 977 } 978 printk(KERN_INFO "PCI: %s IRQ %d for device %s\n", msg, irq, 979 pci_name(dev)); 980 981 /* Update IRQ for all devices with the same pirq value */ 982 while ((dev2 = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev2)) != NULL) { 983 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 984 if (!pin) 985 continue; 986 pin--; 987 info = pirq_get_info(dev2); 988 if (!info) 989 continue; 990 if (info->irq[pin].link == pirq) { 991 /* 992 * We refuse to override the dev->irq 993 * information. Give a warning! 994 */ 995 if (dev2->irq && dev2->irq != irq && \ 996 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 997 ((1 << dev2->irq) & mask))) { 998 #ifndef CONFIG_PCI_MSI 999 printk(KERN_INFO "IRQ routing conflict for %s, have irq %d, want irq %d\n", 1000 pci_name(dev2), dev2->irq, irq); 1001 #endif 1002 continue; 1003 } 1004 dev2->irq = irq; 1005 pirq_penalty[irq]++; 1006 if (dev != dev2) 1007 printk(KERN_INFO 1008 "PCI: Sharing IRQ %d with %s\n", 1009 irq, pci_name(dev2)); 1010 } 1011 } 1012 return 1; 1013 } 1014 1015 static void __init pcibios_fixup_irqs(void) 1016 { 1017 struct pci_dev *dev = NULL; 1018 u8 pin; 1019 1020 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1021 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1022 /* 1023 * If the BIOS has set an out of range IRQ number, just 1024 * ignore it. Also keep track of which IRQ's are 1025 * already in use. 1026 */ 1027 if (dev->irq >= 16) { 1028 DBG(KERN_DEBUG "%s: ignoring bogus IRQ %d\n", 1029 pci_name(dev), dev->irq); 1030 dev->irq = 0; 1031 } 1032 /* 1033 * If the IRQ is already assigned to a PCI device, 1034 * ignore its ISA use penalty 1035 */ 1036 if (pirq_penalty[dev->irq] >= 100 && 1037 pirq_penalty[dev->irq] < 100000) 1038 pirq_penalty[dev->irq] = 0; 1039 pirq_penalty[dev->irq]++; 1040 } 1041 1042 dev = NULL; 1043 while ((dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { 1044 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1045 #ifdef CONFIG_X86_IO_APIC 1046 /* 1047 * Recalculate IRQ numbers if we use the I/O APIC. 1048 */ 1049 if (io_apic_assign_pci_irqs) { 1050 int irq; 1051 1052 if (pin) { 1053 /* 1054 * interrupt pins are numbered starting 1055 * from 1 1056 */ 1057 pin--; 1058 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1059 PCI_SLOT(dev->devfn), pin); 1060 /* 1061 * Busses behind bridges are typically not listed in the MP-table. 1062 * In this case we have to look up the IRQ based on the parent bus, 1063 * parent slot, and pin number. The SMP code detects such bridged 1064 * busses itself so we should get into this branch reliably. 1065 */ 1066 if (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1067 struct pci_dev *bridge = dev->bus->self; 1068 1069 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1070 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1071 PCI_SLOT(bridge->devfn), pin); 1072 if (irq >= 0) 1073 printk(KERN_WARNING "PCI: using PPB %s[%c] to get irq %d\n", 1074 pci_name(bridge), 'A' + pin, irq); 1075 } 1076 if (irq >= 0) { 1077 printk(KERN_INFO "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", 1078 pci_name(dev), 'A' + pin, irq); 1079 dev->irq = irq; 1080 } 1081 } 1082 } 1083 #endif 1084 /* 1085 * Still no IRQ? Try to lookup one... 1086 */ 1087 if (pin && !dev->irq) 1088 pcibios_lookup_irq(dev, 0); 1089 } 1090 } 1091 1092 /* 1093 * Work around broken HP Pavilion Notebooks which assign USB to 1094 * IRQ 9 even though it is actually wired to IRQ 11 1095 */ 1096 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1097 { 1098 if (!broken_hp_bios_irq9) { 1099 broken_hp_bios_irq9 = 1; 1100 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1101 d->ident); 1102 } 1103 return 0; 1104 } 1105 1106 /* 1107 * Work around broken Acer TravelMate 360 Notebooks which assign 1108 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1109 */ 1110 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1111 { 1112 if (!acer_tm360_irqrouting) { 1113 acer_tm360_irqrouting = 1; 1114 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1115 d->ident); 1116 } 1117 return 0; 1118 } 1119 1120 static struct dmi_system_id __initdata pciirq_dmi_table[] = { 1121 { 1122 .callback = fix_broken_hp_bios_irq9, 1123 .ident = "HP Pavilion N5400 Series Laptop", 1124 .matches = { 1125 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1126 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1127 DMI_MATCH(DMI_PRODUCT_VERSION, 1128 "HP Pavilion Notebook Model GE"), 1129 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1130 }, 1131 }, 1132 { 1133 .callback = fix_acer_tm360_irqrouting, 1134 .ident = "Acer TravelMate 36x Laptop", 1135 .matches = { 1136 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1137 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1138 }, 1139 }, 1140 { } 1141 }; 1142 1143 int __init pcibios_irq_init(void) 1144 { 1145 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1146 1147 if (pcibios_enable_irq || raw_pci_ops == NULL) 1148 return 0; 1149 1150 dmi_check_system(pciirq_dmi_table); 1151 1152 pirq_table = pirq_find_routing_table(); 1153 1154 #ifdef CONFIG_PCI_BIOS 1155 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 1156 pirq_table = pcibios_get_irq_routing_table(); 1157 #endif 1158 if (pirq_table) { 1159 pirq_peer_trick(); 1160 pirq_find_router(&pirq_router); 1161 if (pirq_table->exclusive_irqs) { 1162 int i; 1163 for (i = 0; i < 16; i++) 1164 if (!(pirq_table->exclusive_irqs & (1 << i))) 1165 pirq_penalty[i] += 100; 1166 } 1167 /* 1168 * If we're using the I/O APIC, avoid using the PCI IRQ 1169 * routing table 1170 */ 1171 if (io_apic_assign_pci_irqs) 1172 pirq_table = NULL; 1173 } 1174 1175 pcibios_enable_irq = pirq_enable_irq; 1176 1177 pcibios_fixup_irqs(); 1178 return 0; 1179 } 1180 1181 static void pirq_penalize_isa_irq(int irq, int active) 1182 { 1183 /* 1184 * If any ISAPnP device reports an IRQ in its list of possible 1185 * IRQ's, we try to avoid assigning it to PCI devices. 1186 */ 1187 if (irq < 16) { 1188 if (active) 1189 pirq_penalty[irq] += 1000; 1190 else 1191 pirq_penalty[irq] += 100; 1192 } 1193 } 1194 1195 void pcibios_penalize_isa_irq(int irq, int active) 1196 { 1197 #ifdef CONFIG_ACPI 1198 if (!acpi_noirq) 1199 acpi_penalize_isa_irq(irq, active); 1200 else 1201 #endif 1202 pirq_penalize_isa_irq(irq, active); 1203 } 1204 1205 static int pirq_enable_irq(struct pci_dev *dev) 1206 { 1207 u8 pin; 1208 struct pci_dev *temp_dev; 1209 1210 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1211 if (pin && !pcibios_lookup_irq(dev, 1) && !dev->irq) { 1212 char *msg = ""; 1213 1214 pin--; /* interrupt pins are numbered starting from 1 */ 1215 1216 if (io_apic_assign_pci_irqs) { 1217 int irq; 1218 1219 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, PCI_SLOT(dev->devfn), pin); 1220 /* 1221 * Busses behind bridges are typically not listed in the MP-table. 1222 * In this case we have to look up the IRQ based on the parent bus, 1223 * parent slot, and pin number. The SMP code detects such bridged 1224 * busses itself so we should get into this branch reliably. 1225 */ 1226 temp_dev = dev; 1227 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1228 struct pci_dev *bridge = dev->bus->self; 1229 1230 pin = (pin + PCI_SLOT(dev->devfn)) % 4; 1231 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1232 PCI_SLOT(bridge->devfn), pin); 1233 if (irq >= 0) 1234 printk(KERN_WARNING 1235 "PCI: using PPB %s[%c] to get irq %d\n", 1236 pci_name(bridge), 1237 'A' + pin, irq); 1238 dev = bridge; 1239 } 1240 dev = temp_dev; 1241 if (irq >= 0) { 1242 printk(KERN_INFO 1243 "PCI->APIC IRQ transform: %s[%c] -> IRQ %d\n", 1244 pci_name(dev), 'A' + pin, irq); 1245 dev->irq = irq; 1246 return 0; 1247 } else 1248 msg = " Probably buggy MP table."; 1249 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1250 msg = ""; 1251 else 1252 msg = " Please try using pci=biosirq."; 1253 1254 /* 1255 * With IDE legacy devices the IRQ lookup failure is not 1256 * a problem.. 1257 */ 1258 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1259 !(dev->class & 0x5)) 1260 return 0; 1261 1262 printk(KERN_WARNING 1263 "PCI: No IRQ known for interrupt pin %c of device %s.%s\n", 1264 'A' + pin, pci_name(dev), msg); 1265 } 1266 return 0; 1267 } 1268