1 /* 2 * Low-Level PCI Support for PC -- Routing of Interrupts 3 * 4 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 5 */ 6 7 #include <linux/types.h> 8 #include <linux/kernel.h> 9 #include <linux/pci.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/dmi.h> 13 #include <linux/io.h> 14 #include <linux/smp.h> 15 #include <asm/io_apic.h> 16 #include <linux/irq.h> 17 #include <linux/acpi.h> 18 #include <asm/pci_x86.h> 19 20 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 21 #define PIRQ_VERSION 0x0100 22 23 static int broken_hp_bios_irq9; 24 static int acer_tm360_irqrouting; 25 26 static struct irq_routing_table *pirq_table; 27 28 static int pirq_enable_irq(struct pci_dev *dev); 29 static void pirq_disable_irq(struct pci_dev *dev); 30 31 /* 32 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 33 * Avoid using: 13, 14 and 15 (FP error and IDE). 34 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 35 */ 36 unsigned int pcibios_irq_mask = 0xfff8; 37 38 static int pirq_penalty[16] = { 39 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 40 0, 0, 0, 0, 1000, 100000, 100000, 100000 41 }; 42 43 struct irq_router { 44 char *name; 45 u16 vendor, device; 46 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 47 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 48 int new); 49 }; 50 51 struct irq_router_handler { 52 u16 vendor; 53 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 54 }; 55 56 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 57 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq; 58 59 /* 60 * Check passed address for the PCI IRQ Routing Table signature 61 * and perform checksum verification. 62 */ 63 64 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 65 { 66 struct irq_routing_table *rt; 67 int i; 68 u8 sum; 69 70 rt = (struct irq_routing_table *) addr; 71 if (rt->signature != PIRQ_SIGNATURE || 72 rt->version != PIRQ_VERSION || 73 rt->size % 16 || 74 rt->size < sizeof(struct irq_routing_table)) 75 return NULL; 76 sum = 0; 77 for (i = 0; i < rt->size; i++) 78 sum += addr[i]; 79 if (!sum) { 80 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 81 rt); 82 return rt; 83 } 84 return NULL; 85 } 86 87 88 89 /* 90 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 91 */ 92 93 static struct irq_routing_table * __init pirq_find_routing_table(void) 94 { 95 u8 *addr; 96 struct irq_routing_table *rt; 97 98 if (pirq_table_addr) { 99 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 100 if (rt) 101 return rt; 102 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 103 } 104 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 105 rt = pirq_check_routing_table(addr); 106 if (rt) 107 return rt; 108 } 109 return NULL; 110 } 111 112 /* 113 * If we have a IRQ routing table, use it to search for peer host 114 * bridges. It's a gross hack, but since there are no other known 115 * ways how to get a list of buses, we have to go this way. 116 */ 117 118 static void __init pirq_peer_trick(void) 119 { 120 struct irq_routing_table *rt = pirq_table; 121 u8 busmap[256]; 122 int i; 123 struct irq_info *e; 124 125 memset(busmap, 0, sizeof(busmap)); 126 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 127 e = &rt->slots[i]; 128 #ifdef DEBUG 129 { 130 int j; 131 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 132 for (j = 0; j < 4; j++) 133 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 134 DBG("\n"); 135 } 136 #endif 137 busmap[e->bus] = 1; 138 } 139 for (i = 1; i < 256; i++) { 140 if (!busmap[i] || pci_find_bus(0, i)) 141 continue; 142 pcibios_scan_root(i); 143 } 144 pcibios_last_bus = -1; 145 } 146 147 /* 148 * Code for querying and setting of IRQ routes on various interrupt routers. 149 */ 150 151 void eisa_set_level_irq(unsigned int irq) 152 { 153 unsigned char mask = 1 << (irq & 7); 154 unsigned int port = 0x4d0 + (irq >> 3); 155 unsigned char val; 156 static u16 eisa_irq_mask; 157 158 if (irq >= 16 || (1 << irq) & eisa_irq_mask) 159 return; 160 161 eisa_irq_mask |= (1 << irq); 162 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 163 val = inb(port); 164 if (!(val & mask)) { 165 DBG(KERN_DEBUG " -> edge"); 166 outb(val | mask, port); 167 } 168 } 169 170 /* 171 * Common IRQ routing practice: nibbles in config space, 172 * offset by some magic constant. 173 */ 174 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 175 { 176 u8 x; 177 unsigned reg = offset + (nr >> 1); 178 179 pci_read_config_byte(router, reg, &x); 180 return (nr & 1) ? (x >> 4) : (x & 0xf); 181 } 182 183 static void write_config_nybble(struct pci_dev *router, unsigned offset, 184 unsigned nr, unsigned int val) 185 { 186 u8 x; 187 unsigned reg = offset + (nr >> 1); 188 189 pci_read_config_byte(router, reg, &x); 190 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 191 pci_write_config_byte(router, reg, x); 192 } 193 194 /* 195 * ALI pirq entries are damn ugly, and completely undocumented. 196 * This has been figured out from pirq tables, and it's not a pretty 197 * picture. 198 */ 199 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 200 { 201 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 202 203 WARN_ON_ONCE(pirq > 16); 204 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 205 } 206 207 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 208 { 209 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 210 unsigned int val = irqmap[irq]; 211 212 WARN_ON_ONCE(pirq > 16); 213 if (val) { 214 write_config_nybble(router, 0x48, pirq-1, val); 215 return 1; 216 } 217 return 0; 218 } 219 220 /* 221 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 222 * just a pointer to the config space. 223 */ 224 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 225 { 226 u8 x; 227 228 pci_read_config_byte(router, pirq, &x); 229 return (x < 16) ? x : 0; 230 } 231 232 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 233 { 234 pci_write_config_byte(router, pirq, irq); 235 return 1; 236 } 237 238 /* 239 * The VIA pirq rules are nibble-based, like ALI, 240 * but without the ugly irq number munging. 241 * However, PIRQD is in the upper instead of lower 4 bits. 242 */ 243 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 244 { 245 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 246 } 247 248 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 249 { 250 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 251 return 1; 252 } 253 254 /* 255 * The VIA pirq rules are nibble-based, like ALI, 256 * but without the ugly irq number munging. 257 * However, for 82C586, nibble map is different . 258 */ 259 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 260 { 261 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 262 263 WARN_ON_ONCE(pirq > 5); 264 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 265 } 266 267 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 268 { 269 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 270 271 WARN_ON_ONCE(pirq > 5); 272 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 273 return 1; 274 } 275 276 /* 277 * ITE 8330G pirq rules are nibble-based 278 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 279 * 2+3 are both mapped to irq 9 on my system 280 */ 281 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 282 { 283 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 284 285 WARN_ON_ONCE(pirq > 4); 286 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 287 } 288 289 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 290 { 291 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 292 293 WARN_ON_ONCE(pirq > 4); 294 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 295 return 1; 296 } 297 298 /* 299 * OPTI: high four bits are nibble pointer.. 300 * I wonder what the low bits do? 301 */ 302 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 303 { 304 return read_config_nybble(router, 0xb8, pirq >> 4); 305 } 306 307 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 308 { 309 write_config_nybble(router, 0xb8, pirq >> 4, irq); 310 return 1; 311 } 312 313 /* 314 * Cyrix: nibble offset 0x5C 315 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 316 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 317 */ 318 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 319 { 320 return read_config_nybble(router, 0x5C, (pirq-1)^1); 321 } 322 323 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 324 { 325 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 326 return 1; 327 } 328 329 /* 330 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 331 * We have to deal with the following issues here: 332 * - vendors have different ideas about the meaning of link values 333 * - some onboard devices (integrated in the chipset) have special 334 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 335 * - different revision of the router have a different layout for 336 * the routing registers, particularly for the onchip devices 337 * 338 * For all routing registers the common thing is we have one byte 339 * per routeable link which is defined as: 340 * bit 7 IRQ mapping enabled (0) or disabled (1) 341 * bits [6:4] reserved (sometimes used for onchip devices) 342 * bits [3:0] IRQ to map to 343 * allowed: 3-7, 9-12, 14-15 344 * reserved: 0, 1, 2, 8, 13 345 * 346 * The config-space registers located at 0x41/0x42/0x43/0x44 are 347 * always used to route the normal PCI INT A/B/C/D respectively. 348 * Apparently there are systems implementing PCI routing table using 349 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 350 * We try our best to handle both link mappings. 351 * 352 * Currently (2003-05-21) it appears most SiS chipsets follow the 353 * definition of routing registers from the SiS-5595 southbridge. 354 * According to the SiS 5595 datasheets the revision id's of the 355 * router (ISA-bridge) should be 0x01 or 0xb0. 356 * 357 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 358 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 359 * They seem to work with the current routing code. However there is 360 * some concern because of the two USB-OHCI HCs (original SiS 5595 361 * had only one). YMMV. 362 * 363 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 364 * 365 * 0x61: IDEIRQ: 366 * bits [6:5] must be written 01 367 * bit 4 channel-select primary (0), secondary (1) 368 * 369 * 0x62: USBIRQ: 370 * bit 6 OHCI function disabled (0), enabled (1) 371 * 372 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 373 * 374 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 375 * 376 * We support USBIRQ (in addition to INTA-INTD) and keep the 377 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 378 * 379 * Currently the only reported exception is the new SiS 65x chipset 380 * which includes the SiS 69x southbridge. Here we have the 85C503 381 * router revision 0x04 and there are changes in the register layout 382 * mostly related to the different USB HCs with USB 2.0 support. 383 * 384 * Onchip routing for router rev-id 0x04 (try-and-error observation) 385 * 386 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 387 * bit 6-4 are probably unused, not like 5595 388 */ 389 390 #define PIRQ_SIS_IRQ_MASK 0x0f 391 #define PIRQ_SIS_IRQ_DISABLE 0x80 392 #define PIRQ_SIS_USB_ENABLE 0x40 393 394 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 395 { 396 u8 x; 397 int reg; 398 399 reg = pirq; 400 if (reg >= 0x01 && reg <= 0x04) 401 reg += 0x40; 402 pci_read_config_byte(router, reg, &x); 403 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 404 } 405 406 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 407 { 408 u8 x; 409 int reg; 410 411 reg = pirq; 412 if (reg >= 0x01 && reg <= 0x04) 413 reg += 0x40; 414 pci_read_config_byte(router, reg, &x); 415 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 416 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 417 pci_write_config_byte(router, reg, x); 418 return 1; 419 } 420 421 422 /* 423 * VLSI: nibble offset 0x74 - educated guess due to routing table and 424 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 425 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 426 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 427 * for the busbridge to the docking station. 428 */ 429 430 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 431 { 432 WARN_ON_ONCE(pirq >= 9); 433 if (pirq > 8) { 434 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 435 return 0; 436 } 437 return read_config_nybble(router, 0x74, pirq-1); 438 } 439 440 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 441 { 442 WARN_ON_ONCE(pirq >= 9); 443 if (pirq > 8) { 444 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 445 return 0; 446 } 447 write_config_nybble(router, 0x74, pirq-1, irq); 448 return 1; 449 } 450 451 /* 452 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 453 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 454 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 455 * register is a straight binary coding of desired PIC IRQ (low nibble). 456 * 457 * The 'link' value in the PIRQ table is already in the correct format 458 * for the Index register. There are some special index values: 459 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 460 * and 0x03 for SMBus. 461 */ 462 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 463 { 464 outb(pirq, 0xc00); 465 return inb(0xc01) & 0xf; 466 } 467 468 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 469 int pirq, int irq) 470 { 471 outb(pirq, 0xc00); 472 outb(irq, 0xc01); 473 return 1; 474 } 475 476 /* Support for AMD756 PCI IRQ Routing 477 * Jhon H. Caicedo <jhcaiced@osso.org.co> 478 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 479 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 480 * The AMD756 pirq rules are nibble-based 481 * offset 0x56 0-3 PIRQA 4-7 PIRQB 482 * offset 0x57 0-3 PIRQC 4-7 PIRQD 483 */ 484 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 485 { 486 u8 irq; 487 irq = 0; 488 if (pirq <= 4) 489 irq = read_config_nybble(router, 0x56, pirq - 1); 490 dev_info(&dev->dev, 491 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 492 dev->vendor, dev->device, pirq, irq); 493 return irq; 494 } 495 496 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 497 { 498 dev_info(&dev->dev, 499 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 500 dev->vendor, dev->device, pirq, irq); 501 if (pirq <= 4) 502 write_config_nybble(router, 0x56, pirq - 1, irq); 503 return 1; 504 } 505 506 /* 507 * PicoPower PT86C523 508 */ 509 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 510 { 511 outb(0x10 + ((pirq - 1) >> 1), 0x24); 512 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 513 } 514 515 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 516 int irq) 517 { 518 unsigned int x; 519 outb(0x10 + ((pirq - 1) >> 1), 0x24); 520 x = inb(0x26); 521 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 522 outb(x, 0x26); 523 return 1; 524 } 525 526 #ifdef CONFIG_PCI_BIOS 527 528 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 529 { 530 struct pci_dev *bridge; 531 int pin = pci_get_interrupt_pin(dev, &bridge); 532 return pcibios_set_irq_routing(bridge, pin - 1, irq); 533 } 534 535 #endif 536 537 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 538 { 539 static struct pci_device_id __initdata pirq_440gx[] = { 540 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 541 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 542 { }, 543 }; 544 545 /* 440GX has a proprietary PIRQ router -- don't use it */ 546 if (pci_dev_present(pirq_440gx)) 547 return 0; 548 549 switch (device) { 550 case PCI_DEVICE_ID_INTEL_82371FB_0: 551 case PCI_DEVICE_ID_INTEL_82371SB_0: 552 case PCI_DEVICE_ID_INTEL_82371AB_0: 553 case PCI_DEVICE_ID_INTEL_82371MX: 554 case PCI_DEVICE_ID_INTEL_82443MX_0: 555 case PCI_DEVICE_ID_INTEL_82801AA_0: 556 case PCI_DEVICE_ID_INTEL_82801AB_0: 557 case PCI_DEVICE_ID_INTEL_82801BA_0: 558 case PCI_DEVICE_ID_INTEL_82801BA_10: 559 case PCI_DEVICE_ID_INTEL_82801CA_0: 560 case PCI_DEVICE_ID_INTEL_82801CA_12: 561 case PCI_DEVICE_ID_INTEL_82801DB_0: 562 case PCI_DEVICE_ID_INTEL_82801E_0: 563 case PCI_DEVICE_ID_INTEL_82801EB_0: 564 case PCI_DEVICE_ID_INTEL_ESB_1: 565 case PCI_DEVICE_ID_INTEL_ICH6_0: 566 case PCI_DEVICE_ID_INTEL_ICH6_1: 567 case PCI_DEVICE_ID_INTEL_ICH7_0: 568 case PCI_DEVICE_ID_INTEL_ICH7_1: 569 case PCI_DEVICE_ID_INTEL_ICH7_30: 570 case PCI_DEVICE_ID_INTEL_ICH7_31: 571 case PCI_DEVICE_ID_INTEL_TGP_LPC: 572 case PCI_DEVICE_ID_INTEL_ESB2_0: 573 case PCI_DEVICE_ID_INTEL_ICH8_0: 574 case PCI_DEVICE_ID_INTEL_ICH8_1: 575 case PCI_DEVICE_ID_INTEL_ICH8_2: 576 case PCI_DEVICE_ID_INTEL_ICH8_3: 577 case PCI_DEVICE_ID_INTEL_ICH8_4: 578 case PCI_DEVICE_ID_INTEL_ICH9_0: 579 case PCI_DEVICE_ID_INTEL_ICH9_1: 580 case PCI_DEVICE_ID_INTEL_ICH9_2: 581 case PCI_DEVICE_ID_INTEL_ICH9_3: 582 case PCI_DEVICE_ID_INTEL_ICH9_4: 583 case PCI_DEVICE_ID_INTEL_ICH9_5: 584 case PCI_DEVICE_ID_INTEL_EP80579_0: 585 case PCI_DEVICE_ID_INTEL_ICH10_0: 586 case PCI_DEVICE_ID_INTEL_ICH10_1: 587 case PCI_DEVICE_ID_INTEL_ICH10_2: 588 case PCI_DEVICE_ID_INTEL_ICH10_3: 589 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: 590 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: 591 r->name = "PIIX/ICH"; 592 r->get = pirq_piix_get; 593 r->set = pirq_piix_set; 594 return 1; 595 } 596 597 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 598 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 599 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 600 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) 601 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN && 602 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) 603 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 604 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { 605 r->name = "PIIX/ICH"; 606 r->get = pirq_piix_get; 607 r->set = pirq_piix_set; 608 return 1; 609 } 610 611 return 0; 612 } 613 614 static __init int via_router_probe(struct irq_router *r, 615 struct pci_dev *router, u16 device) 616 { 617 /* FIXME: We should move some of the quirk fixup stuff here */ 618 619 /* 620 * workarounds for some buggy BIOSes 621 */ 622 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 623 switch (router->device) { 624 case PCI_DEVICE_ID_VIA_82C686: 625 /* 626 * Asus k7m bios wrongly reports 82C686A 627 * as 586-compatible 628 */ 629 device = PCI_DEVICE_ID_VIA_82C686; 630 break; 631 case PCI_DEVICE_ID_VIA_8235: 632 /** 633 * Asus a7v-x bios wrongly reports 8235 634 * as 586-compatible 635 */ 636 device = PCI_DEVICE_ID_VIA_8235; 637 break; 638 case PCI_DEVICE_ID_VIA_8237: 639 /** 640 * Asus a7v600 bios wrongly reports 8237 641 * as 586-compatible 642 */ 643 device = PCI_DEVICE_ID_VIA_8237; 644 break; 645 } 646 } 647 648 switch (device) { 649 case PCI_DEVICE_ID_VIA_82C586_0: 650 r->name = "VIA"; 651 r->get = pirq_via586_get; 652 r->set = pirq_via586_set; 653 return 1; 654 case PCI_DEVICE_ID_VIA_82C596: 655 case PCI_DEVICE_ID_VIA_82C686: 656 case PCI_DEVICE_ID_VIA_8231: 657 case PCI_DEVICE_ID_VIA_8233A: 658 case PCI_DEVICE_ID_VIA_8235: 659 case PCI_DEVICE_ID_VIA_8237: 660 /* FIXME: add new ones for 8233/5 */ 661 r->name = "VIA"; 662 r->get = pirq_via_get; 663 r->set = pirq_via_set; 664 return 1; 665 } 666 return 0; 667 } 668 669 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 670 { 671 switch (device) { 672 case PCI_DEVICE_ID_VLSI_82C534: 673 r->name = "VLSI 82C534"; 674 r->get = pirq_vlsi_get; 675 r->set = pirq_vlsi_set; 676 return 1; 677 } 678 return 0; 679 } 680 681 682 static __init int serverworks_router_probe(struct irq_router *r, 683 struct pci_dev *router, u16 device) 684 { 685 switch (device) { 686 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 687 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 688 r->name = "ServerWorks"; 689 r->get = pirq_serverworks_get; 690 r->set = pirq_serverworks_set; 691 return 1; 692 } 693 return 0; 694 } 695 696 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 697 { 698 if (device != PCI_DEVICE_ID_SI_503) 699 return 0; 700 701 r->name = "SIS"; 702 r->get = pirq_sis_get; 703 r->set = pirq_sis_set; 704 return 1; 705 } 706 707 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 708 { 709 switch (device) { 710 case PCI_DEVICE_ID_CYRIX_5520: 711 r->name = "NatSemi"; 712 r->get = pirq_cyrix_get; 713 r->set = pirq_cyrix_set; 714 return 1; 715 } 716 return 0; 717 } 718 719 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 720 { 721 switch (device) { 722 case PCI_DEVICE_ID_OPTI_82C700: 723 r->name = "OPTI"; 724 r->get = pirq_opti_get; 725 r->set = pirq_opti_set; 726 return 1; 727 } 728 return 0; 729 } 730 731 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 732 { 733 switch (device) { 734 case PCI_DEVICE_ID_ITE_IT8330G_0: 735 r->name = "ITE"; 736 r->get = pirq_ite_get; 737 r->set = pirq_ite_set; 738 return 1; 739 } 740 return 0; 741 } 742 743 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 744 { 745 switch (device) { 746 case PCI_DEVICE_ID_AL_M1533: 747 case PCI_DEVICE_ID_AL_M1563: 748 r->name = "ALI"; 749 r->get = pirq_ali_get; 750 r->set = pirq_ali_set; 751 return 1; 752 } 753 return 0; 754 } 755 756 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 757 { 758 switch (device) { 759 case PCI_DEVICE_ID_AMD_VIPER_740B: 760 r->name = "AMD756"; 761 break; 762 case PCI_DEVICE_ID_AMD_VIPER_7413: 763 r->name = "AMD766"; 764 break; 765 case PCI_DEVICE_ID_AMD_VIPER_7443: 766 r->name = "AMD768"; 767 break; 768 default: 769 return 0; 770 } 771 r->get = pirq_amd756_get; 772 r->set = pirq_amd756_set; 773 return 1; 774 } 775 776 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 777 { 778 switch (device) { 779 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 780 r->name = "PicoPower PT86C523"; 781 r->get = pirq_pico_get; 782 r->set = pirq_pico_set; 783 return 1; 784 785 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 786 r->name = "PicoPower PT86C523 rev. BB+"; 787 r->get = pirq_pico_get; 788 r->set = pirq_pico_set; 789 return 1; 790 } 791 return 0; 792 } 793 794 static __initdata struct irq_router_handler pirq_routers[] = { 795 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 796 { PCI_VENDOR_ID_AL, ali_router_probe }, 797 { PCI_VENDOR_ID_ITE, ite_router_probe }, 798 { PCI_VENDOR_ID_VIA, via_router_probe }, 799 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 800 { PCI_VENDOR_ID_SI, sis_router_probe }, 801 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 802 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 803 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 804 { PCI_VENDOR_ID_AMD, amd_router_probe }, 805 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 806 /* Someone with docs needs to add the ATI Radeon IGP */ 807 { 0, NULL } 808 }; 809 static struct irq_router pirq_router; 810 static struct pci_dev *pirq_router_dev; 811 812 813 /* 814 * FIXME: should we have an option to say "generic for 815 * chipset" ? 816 */ 817 818 static void __init pirq_find_router(struct irq_router *r) 819 { 820 struct irq_routing_table *rt = pirq_table; 821 struct irq_router_handler *h; 822 823 #ifdef CONFIG_PCI_BIOS 824 if (!rt->signature) { 825 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 826 r->set = pirq_bios_set; 827 r->name = "BIOS"; 828 return; 829 } 830 #endif 831 832 /* Default unless a driver reloads it */ 833 r->name = "default"; 834 r->get = NULL; 835 r->set = NULL; 836 837 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 838 rt->rtr_vendor, rt->rtr_device); 839 840 pirq_router_dev = pci_get_bus_and_slot(rt->rtr_bus, rt->rtr_devfn); 841 if (!pirq_router_dev) { 842 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 843 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 844 return; 845 } 846 847 for (h = pirq_routers; h->vendor; h++) { 848 /* First look for a router match */ 849 if (rt->rtr_vendor == h->vendor && 850 h->probe(r, pirq_router_dev, rt->rtr_device)) 851 break; 852 /* Fall back to a device match */ 853 if (pirq_router_dev->vendor == h->vendor && 854 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 855 break; 856 } 857 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 858 pirq_router.name, 859 pirq_router_dev->vendor, pirq_router_dev->device); 860 861 /* The device remains referenced for the kernel lifetime */ 862 } 863 864 static struct irq_info *pirq_get_info(struct pci_dev *dev) 865 { 866 struct irq_routing_table *rt = pirq_table; 867 int entries = (rt->size - sizeof(struct irq_routing_table)) / 868 sizeof(struct irq_info); 869 struct irq_info *info; 870 871 for (info = rt->slots; entries--; info++) 872 if (info->bus == dev->bus->number && 873 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 874 return info; 875 return NULL; 876 } 877 878 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 879 { 880 u8 pin; 881 struct irq_info *info; 882 int i, pirq, newirq; 883 int irq = 0; 884 u32 mask; 885 struct irq_router *r = &pirq_router; 886 struct pci_dev *dev2 = NULL; 887 char *msg = NULL; 888 889 /* Find IRQ pin */ 890 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 891 if (!pin) { 892 dev_dbg(&dev->dev, "no interrupt pin\n"); 893 return 0; 894 } 895 896 if (io_apic_assign_pci_irqs) 897 return 0; 898 899 /* Find IRQ routing entry */ 900 901 if (!pirq_table) 902 return 0; 903 904 info = pirq_get_info(dev); 905 if (!info) { 906 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 907 'A' + pin - 1); 908 return 0; 909 } 910 pirq = info->irq[pin - 1].link; 911 mask = info->irq[pin - 1].bitmap; 912 if (!pirq) { 913 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); 914 return 0; 915 } 916 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 917 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); 918 mask &= pcibios_irq_mask; 919 920 /* Work around broken HP Pavilion Notebooks which assign USB to 921 IRQ 9 even though it is actually wired to IRQ 11 */ 922 923 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 924 dev->irq = 11; 925 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 926 r->set(pirq_router_dev, dev, pirq, 11); 927 } 928 929 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 930 if (acer_tm360_irqrouting && dev->irq == 11 && 931 dev->vendor == PCI_VENDOR_ID_O2) { 932 pirq = 0x68; 933 mask = 0x400; 934 dev->irq = r->get(pirq_router_dev, dev, pirq); 935 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 936 } 937 938 /* 939 * Find the best IRQ to assign: use the one 940 * reported by the device if possible. 941 */ 942 newirq = dev->irq; 943 if (newirq && !((1 << newirq) & mask)) { 944 if (pci_probe & PCI_USE_PIRQ_MASK) 945 newirq = 0; 946 else 947 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 948 "%#x; try pci=usepirqmask\n", newirq, mask); 949 } 950 if (!newirq && assign) { 951 for (i = 0; i < 16; i++) { 952 if (!(mask & (1 << i))) 953 continue; 954 if (pirq_penalty[i] < pirq_penalty[newirq] && 955 can_request_irq(i, IRQF_SHARED)) 956 newirq = i; 957 } 958 } 959 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq); 960 961 /* Check if it is hardcoded */ 962 if ((pirq & 0xf0) == 0xf0) { 963 irq = pirq & 0xf; 964 msg = "hardcoded"; 965 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 966 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 967 msg = "found"; 968 eisa_set_level_irq(irq); 969 } else if (newirq && r->set && 970 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 971 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 972 eisa_set_level_irq(newirq); 973 msg = "assigned"; 974 irq = newirq; 975 } 976 } 977 978 if (!irq) { 979 if (newirq && mask == (1 << newirq)) { 980 msg = "guessed"; 981 irq = newirq; 982 } else { 983 dev_dbg(&dev->dev, "can't route interrupt\n"); 984 return 0; 985 } 986 } 987 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq); 988 989 /* Update IRQ for all devices with the same pirq value */ 990 for_each_pci_dev(dev2) { 991 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 992 if (!pin) 993 continue; 994 995 info = pirq_get_info(dev2); 996 if (!info) 997 continue; 998 if (info->irq[pin - 1].link == pirq) { 999 /* 1000 * We refuse to override the dev->irq 1001 * information. Give a warning! 1002 */ 1003 if (dev2->irq && dev2->irq != irq && \ 1004 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 1005 ((1 << dev2->irq) & mask))) { 1006 #ifndef CONFIG_PCI_MSI 1007 dev_info(&dev2->dev, "IRQ routing conflict: " 1008 "have IRQ %d, want IRQ %d\n", 1009 dev2->irq, irq); 1010 #endif 1011 continue; 1012 } 1013 dev2->irq = irq; 1014 pirq_penalty[irq]++; 1015 if (dev != dev2) 1016 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1017 irq, pci_name(dev2)); 1018 } 1019 } 1020 return 1; 1021 } 1022 1023 void __init pcibios_fixup_irqs(void) 1024 { 1025 struct pci_dev *dev = NULL; 1026 u8 pin; 1027 1028 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1029 for_each_pci_dev(dev) { 1030 /* 1031 * If the BIOS has set an out of range IRQ number, just 1032 * ignore it. Also keep track of which IRQ's are 1033 * already in use. 1034 */ 1035 if (dev->irq >= 16) { 1036 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1037 dev->irq = 0; 1038 } 1039 /* 1040 * If the IRQ is already assigned to a PCI device, 1041 * ignore its ISA use penalty 1042 */ 1043 if (pirq_penalty[dev->irq] >= 100 && 1044 pirq_penalty[dev->irq] < 100000) 1045 pirq_penalty[dev->irq] = 0; 1046 pirq_penalty[dev->irq]++; 1047 } 1048 1049 if (io_apic_assign_pci_irqs) 1050 return; 1051 1052 dev = NULL; 1053 for_each_pci_dev(dev) { 1054 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1055 if (!pin) 1056 continue; 1057 1058 /* 1059 * Still no IRQ? Try to lookup one... 1060 */ 1061 if (!dev->irq) 1062 pcibios_lookup_irq(dev, 0); 1063 } 1064 } 1065 1066 /* 1067 * Work around broken HP Pavilion Notebooks which assign USB to 1068 * IRQ 9 even though it is actually wired to IRQ 11 1069 */ 1070 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1071 { 1072 if (!broken_hp_bios_irq9) { 1073 broken_hp_bios_irq9 = 1; 1074 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1075 d->ident); 1076 } 1077 return 0; 1078 } 1079 1080 /* 1081 * Work around broken Acer TravelMate 360 Notebooks which assign 1082 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1083 */ 1084 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1085 { 1086 if (!acer_tm360_irqrouting) { 1087 acer_tm360_irqrouting = 1; 1088 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1089 d->ident); 1090 } 1091 return 0; 1092 } 1093 1094 static struct dmi_system_id __initdata pciirq_dmi_table[] = { 1095 { 1096 .callback = fix_broken_hp_bios_irq9, 1097 .ident = "HP Pavilion N5400 Series Laptop", 1098 .matches = { 1099 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1100 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1101 DMI_MATCH(DMI_PRODUCT_VERSION, 1102 "HP Pavilion Notebook Model GE"), 1103 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1104 }, 1105 }, 1106 { 1107 .callback = fix_acer_tm360_irqrouting, 1108 .ident = "Acer TravelMate 36x Laptop", 1109 .matches = { 1110 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1111 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1112 }, 1113 }, 1114 { } 1115 }; 1116 1117 void __init pcibios_irq_init(void) 1118 { 1119 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1120 1121 if (raw_pci_ops == NULL) 1122 return; 1123 1124 dmi_check_system(pciirq_dmi_table); 1125 1126 pirq_table = pirq_find_routing_table(); 1127 1128 #ifdef CONFIG_PCI_BIOS 1129 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) 1130 pirq_table = pcibios_get_irq_routing_table(); 1131 #endif 1132 if (pirq_table) { 1133 pirq_peer_trick(); 1134 pirq_find_router(&pirq_router); 1135 if (pirq_table->exclusive_irqs) { 1136 int i; 1137 for (i = 0; i < 16; i++) 1138 if (!(pirq_table->exclusive_irqs & (1 << i))) 1139 pirq_penalty[i] += 100; 1140 } 1141 /* 1142 * If we're using the I/O APIC, avoid using the PCI IRQ 1143 * routing table 1144 */ 1145 if (io_apic_assign_pci_irqs) 1146 pirq_table = NULL; 1147 } 1148 1149 x86_init.pci.fixup_irqs(); 1150 1151 if (io_apic_assign_pci_irqs && pci_routeirq) { 1152 struct pci_dev *dev = NULL; 1153 /* 1154 * PCI IRQ routing is set up by pci_enable_device(), but we 1155 * also do it here in case there are still broken drivers that 1156 * don't use pci_enable_device(). 1157 */ 1158 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n"); 1159 for_each_pci_dev(dev) 1160 pirq_enable_irq(dev); 1161 } 1162 } 1163 1164 static void pirq_penalize_isa_irq(int irq, int active) 1165 { 1166 /* 1167 * If any ISAPnP device reports an IRQ in its list of possible 1168 * IRQ's, we try to avoid assigning it to PCI devices. 1169 */ 1170 if (irq < 16) { 1171 if (active) 1172 pirq_penalty[irq] += 1000; 1173 else 1174 pirq_penalty[irq] += 100; 1175 } 1176 } 1177 1178 void pcibios_penalize_isa_irq(int irq, int active) 1179 { 1180 #ifdef CONFIG_ACPI 1181 if (!acpi_noirq) 1182 acpi_penalize_isa_irq(irq, active); 1183 else 1184 #endif 1185 pirq_penalize_isa_irq(irq, active); 1186 } 1187 1188 static int pirq_enable_irq(struct pci_dev *dev) 1189 { 1190 u8 pin = 0; 1191 1192 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1193 if (pin && !pcibios_lookup_irq(dev, 1)) { 1194 char *msg = ""; 1195 1196 if (!io_apic_assign_pci_irqs && dev->irq) 1197 return 0; 1198 1199 if (io_apic_assign_pci_irqs) { 1200 #ifdef CONFIG_X86_IO_APIC 1201 struct pci_dev *temp_dev; 1202 int irq; 1203 1204 if (dev->irq_managed && dev->irq > 0) 1205 return 0; 1206 1207 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1208 PCI_SLOT(dev->devfn), pin - 1); 1209 /* 1210 * Busses behind bridges are typically not listed in the MP-table. 1211 * In this case we have to look up the IRQ based on the parent bus, 1212 * parent slot, and pin number. The SMP code detects such bridged 1213 * busses itself so we should get into this branch reliably. 1214 */ 1215 temp_dev = dev; 1216 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1217 struct pci_dev *bridge = dev->bus->self; 1218 1219 pin = pci_swizzle_interrupt_pin(dev, pin); 1220 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1221 PCI_SLOT(bridge->devfn), 1222 pin - 1); 1223 if (irq >= 0) 1224 dev_warn(&dev->dev, "using bridge %s " 1225 "INT %c to get IRQ %d\n", 1226 pci_name(bridge), 'A' + pin - 1, 1227 irq); 1228 dev = bridge; 1229 } 1230 dev = temp_dev; 1231 if (irq >= 0) { 1232 dev->irq_managed = 1; 1233 dev->irq = irq; 1234 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1235 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1236 return 0; 1237 } else 1238 msg = "; probably buggy MP table"; 1239 #endif 1240 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1241 msg = ""; 1242 else 1243 msg = "; please try using pci=biosirq"; 1244 1245 /* 1246 * With IDE legacy devices the IRQ lookup failure is not 1247 * a problem.. 1248 */ 1249 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1250 !(dev->class & 0x5)) 1251 return 0; 1252 1253 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1254 'A' + pin - 1, msg); 1255 } 1256 return 0; 1257 } 1258 1259 bool mp_should_keep_irq(struct device *dev) 1260 { 1261 if (dev->power.is_prepared) 1262 return true; 1263 #ifdef CONFIG_PM 1264 if (dev->power.runtime_status == RPM_SUSPENDING) 1265 return true; 1266 #endif 1267 1268 return false; 1269 } 1270 1271 static void pirq_disable_irq(struct pci_dev *dev) 1272 { 1273 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1274 dev->irq_managed && dev->irq) { 1275 mp_unmap_irq(dev->irq); 1276 dev->irq = 0; 1277 dev->irq_managed = 0; 1278 } 1279 } 1280