1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Low-Level PCI Support for PC -- Routing of Interrupts 4 * 5 * (c) 1999--2000 Martin Mares <mj@ucw.cz> 6 */ 7 8 #include <linux/types.h> 9 #include <linux/kernel.h> 10 #include <linux/pci.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/dmi.h> 14 #include <linux/io.h> 15 #include <linux/smp.h> 16 #include <linux/spinlock.h> 17 #include <asm/io_apic.h> 18 #include <linux/irq.h> 19 #include <linux/acpi.h> 20 21 #include <asm/i8259.h> 22 #include <asm/pc-conf-reg.h> 23 #include <asm/pci_x86.h> 24 25 #define PIRQ_SIGNATURE (('$' << 0) + ('P' << 8) + ('I' << 16) + ('R' << 24)) 26 #define PIRQ_VERSION 0x0100 27 28 static int broken_hp_bios_irq9; 29 static int acer_tm360_irqrouting; 30 31 static struct irq_routing_table *pirq_table; 32 33 static int pirq_enable_irq(struct pci_dev *dev); 34 static void pirq_disable_irq(struct pci_dev *dev); 35 36 /* 37 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 38 * Avoid using: 13, 14 and 15 (FP error and IDE). 39 * Penalize: 3, 4, 6, 7, 12 (known ISA uses: serial, floppy, parallel and mouse) 40 */ 41 unsigned int pcibios_irq_mask = 0xfff8; 42 43 static int pirq_penalty[16] = { 44 1000000, 1000000, 1000000, 1000, 1000, 0, 1000, 1000, 45 0, 0, 0, 0, 1000, 100000, 100000, 100000 46 }; 47 48 struct irq_router { 49 char *name; 50 u16 vendor, device; 51 int (*get)(struct pci_dev *router, struct pci_dev *dev, int pirq); 52 int (*set)(struct pci_dev *router, struct pci_dev *dev, int pirq, 53 int new); 54 int (*lvl)(struct pci_dev *router, struct pci_dev *dev, int pirq, 55 int irq); 56 }; 57 58 struct irq_router_handler { 59 u16 vendor; 60 int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); 61 }; 62 63 int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 64 void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq; 65 66 /* 67 * Check passed address for the PCI IRQ Routing Table signature 68 * and perform checksum verification. 69 */ 70 71 static inline struct irq_routing_table *pirq_check_routing_table(u8 *addr) 72 { 73 struct irq_routing_table *rt; 74 int i; 75 u8 sum; 76 77 rt = (struct irq_routing_table *) addr; 78 if (rt->signature != PIRQ_SIGNATURE || 79 rt->version != PIRQ_VERSION || 80 rt->size % 16 || 81 rt->size < sizeof(struct irq_routing_table)) 82 return NULL; 83 sum = 0; 84 for (i = 0; i < rt->size; i++) 85 sum += addr[i]; 86 if (!sum) { 87 DBG(KERN_DEBUG "PCI: Interrupt Routing Table found at 0x%p\n", 88 rt); 89 return rt; 90 } 91 return NULL; 92 } 93 94 95 96 /* 97 * Search 0xf0000 -- 0xfffff for the PCI IRQ Routing Table. 98 */ 99 100 static struct irq_routing_table * __init pirq_find_routing_table(void) 101 { 102 u8 *addr; 103 struct irq_routing_table *rt; 104 105 if (pirq_table_addr) { 106 rt = pirq_check_routing_table((u8 *) __va(pirq_table_addr)); 107 if (rt) 108 return rt; 109 printk(KERN_WARNING "PCI: PIRQ table NOT found at pirqaddr\n"); 110 } 111 for (addr = (u8 *) __va(0xf0000); addr < (u8 *) __va(0x100000); addr += 16) { 112 rt = pirq_check_routing_table(addr); 113 if (rt) 114 return rt; 115 } 116 return NULL; 117 } 118 119 /* 120 * If we have a IRQ routing table, use it to search for peer host 121 * bridges. It's a gross hack, but since there are no other known 122 * ways how to get a list of buses, we have to go this way. 123 */ 124 125 static void __init pirq_peer_trick(void) 126 { 127 struct irq_routing_table *rt = pirq_table; 128 u8 busmap[256]; 129 int i; 130 struct irq_info *e; 131 132 memset(busmap, 0, sizeof(busmap)); 133 for (i = 0; i < (rt->size - sizeof(struct irq_routing_table)) / sizeof(struct irq_info); i++) { 134 e = &rt->slots[i]; 135 #ifdef DEBUG 136 { 137 int j; 138 DBG(KERN_DEBUG "%02x:%02x slot=%02x", e->bus, e->devfn/8, e->slot); 139 for (j = 0; j < 4; j++) 140 DBG(" %d:%02x/%04x", j, e->irq[j].link, e->irq[j].bitmap); 141 DBG("\n"); 142 } 143 #endif 144 busmap[e->bus] = 1; 145 } 146 for (i = 1; i < 256; i++) { 147 if (!busmap[i] || pci_find_bus(0, i)) 148 continue; 149 pcibios_scan_root(i); 150 } 151 pcibios_last_bus = -1; 152 } 153 154 /* 155 * Code for querying and setting of IRQ routes on various interrupt routers. 156 * PIC Edge/Level Control Registers (ELCR) 0x4d0 & 0x4d1. 157 */ 158 159 void elcr_set_level_irq(unsigned int irq) 160 { 161 unsigned char mask = 1 << (irq & 7); 162 unsigned int port = PIC_ELCR1 + (irq >> 3); 163 unsigned char val; 164 static u16 elcr_irq_mask; 165 166 if (irq >= 16 || (1 << irq) & elcr_irq_mask) 167 return; 168 169 elcr_irq_mask |= (1 << irq); 170 printk(KERN_DEBUG "PCI: setting IRQ %u as level-triggered\n", irq); 171 val = inb(port); 172 if (!(val & mask)) { 173 DBG(KERN_DEBUG " -> edge"); 174 outb(val | mask, port); 175 } 176 } 177 178 /* 179 * PIRQ routing for the M1487 ISA Bus Controller (IBC) ASIC used 180 * with the ALi FinALi 486 chipset. The IBC is not decoded in the 181 * PCI configuration space, so we identify it by the accompanying 182 * M1489 Cache-Memory PCI Controller (CMP) ASIC. 183 * 184 * There are four 4-bit mappings provided, spread across two PCI 185 * INTx Routing Table Mapping Registers, available in the port I/O 186 * space accessible indirectly via the index/data register pair at 187 * 0x22/0x23, located at indices 0x42 and 0x43 for the INT1/INT2 188 * and INT3/INT4 lines respectively. The INT1/INT3 and INT2/INT4 189 * lines are mapped in the low and the high 4-bit nibble of the 190 * corresponding register as follows: 191 * 192 * 0000 : Disabled 193 * 0001 : IRQ9 194 * 0010 : IRQ3 195 * 0011 : IRQ10 196 * 0100 : IRQ4 197 * 0101 : IRQ5 198 * 0110 : IRQ7 199 * 0111 : IRQ6 200 * 1000 : Reserved 201 * 1001 : IRQ11 202 * 1010 : Reserved 203 * 1011 : IRQ12 204 * 1100 : Reserved 205 * 1101 : IRQ14 206 * 1110 : Reserved 207 * 1111 : IRQ15 208 * 209 * In addition to the usual ELCR register pair there is a separate 210 * PCI INTx Sensitivity Register at index 0x44 in the same port I/O 211 * space, whose bits 3:0 select the trigger mode for INT[4:1] lines 212 * respectively. Any bit set to 1 causes interrupts coming on the 213 * corresponding line to be passed to ISA as edge-triggered and 214 * otherwise they are passed as level-triggered. Manufacturer's 215 * documentation says this register has to be set consistently with 216 * the relevant ELCR register. 217 * 218 * Accesses to the port I/O space concerned here need to be unlocked 219 * by writing the value of 0xc5 to the Lock Register at index 0x03 220 * beforehand. Any other value written to said register prevents 221 * further accesses from reaching the register file, except for the 222 * Lock Register being written with 0xc5 again. 223 * 224 * References: 225 * 226 * "M1489/M1487: 486 PCI Chip Set", Version 1.2, Acer Laboratories 227 * Inc., July 1997 228 */ 229 230 #define PC_CONF_FINALI_LOCK 0x03u 231 #define PC_CONF_FINALI_PCI_INTX_RT1 0x42u 232 #define PC_CONF_FINALI_PCI_INTX_RT2 0x43u 233 #define PC_CONF_FINALI_PCI_INTX_SENS 0x44u 234 235 #define PC_CONF_FINALI_LOCK_KEY 0xc5u 236 237 static u8 read_pc_conf_nybble(u8 base, u8 index) 238 { 239 u8 reg = base + (index >> 1); 240 u8 x; 241 242 x = pc_conf_get(reg); 243 return index & 1 ? x >> 4 : x & 0xf; 244 } 245 246 static void write_pc_conf_nybble(u8 base, u8 index, u8 val) 247 { 248 u8 reg = base + (index >> 1); 249 u8 x; 250 251 x = pc_conf_get(reg); 252 x = index & 1 ? (x & 0x0f) | (val << 4) : (x & 0xf0) | val; 253 pc_conf_set(reg, x); 254 } 255 256 static int pirq_finali_get(struct pci_dev *router, struct pci_dev *dev, 257 int pirq) 258 { 259 static const u8 irqmap[16] = { 260 0, 9, 3, 10, 4, 5, 7, 6, 0, 11, 0, 12, 0, 14, 0, 15 261 }; 262 unsigned long flags; 263 u8 x; 264 265 raw_spin_lock_irqsave(&pc_conf_lock, flags); 266 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 267 x = irqmap[read_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, pirq - 1)]; 268 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 269 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 270 return x; 271 } 272 273 static int pirq_finali_set(struct pci_dev *router, struct pci_dev *dev, 274 int pirq, int irq) 275 { 276 static const u8 irqmap[16] = { 277 0, 0, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 278 }; 279 u8 val = irqmap[irq]; 280 unsigned long flags; 281 282 if (!val) 283 return 0; 284 285 raw_spin_lock_irqsave(&pc_conf_lock, flags); 286 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 287 write_pc_conf_nybble(PC_CONF_FINALI_PCI_INTX_RT1, pirq - 1, val); 288 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 289 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 290 return 1; 291 } 292 293 static int pirq_finali_lvl(struct pci_dev *router, struct pci_dev *dev, 294 int pirq, int irq) 295 { 296 u8 mask = ~(1u << (pirq - 1)); 297 unsigned long flags; 298 u8 trig; 299 300 elcr_set_level_irq(irq); 301 raw_spin_lock_irqsave(&pc_conf_lock, flags); 302 pc_conf_set(PC_CONF_FINALI_LOCK, PC_CONF_FINALI_LOCK_KEY); 303 trig = pc_conf_get(PC_CONF_FINALI_PCI_INTX_SENS); 304 trig &= mask; 305 pc_conf_set(PC_CONF_FINALI_PCI_INTX_SENS, trig); 306 pc_conf_set(PC_CONF_FINALI_LOCK, 0); 307 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 308 return 1; 309 } 310 311 /* 312 * Common IRQ routing practice: nibbles in config space, 313 * offset by some magic constant. 314 */ 315 static unsigned int read_config_nybble(struct pci_dev *router, unsigned offset, unsigned nr) 316 { 317 u8 x; 318 unsigned reg = offset + (nr >> 1); 319 320 pci_read_config_byte(router, reg, &x); 321 return (nr & 1) ? (x >> 4) : (x & 0xf); 322 } 323 324 static void write_config_nybble(struct pci_dev *router, unsigned offset, 325 unsigned nr, unsigned int val) 326 { 327 u8 x; 328 unsigned reg = offset + (nr >> 1); 329 330 pci_read_config_byte(router, reg, &x); 331 x = (nr & 1) ? ((x & 0x0f) | (val << 4)) : ((x & 0xf0) | val); 332 pci_write_config_byte(router, reg, x); 333 } 334 335 /* 336 * ALI pirq entries are damn ugly, and completely undocumented. 337 * This has been figured out from pirq tables, and it's not a pretty 338 * picture. 339 */ 340 static int pirq_ali_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 341 { 342 static const unsigned char irqmap[16] = { 0, 9, 3, 10, 4, 5, 7, 6, 1, 11, 0, 12, 0, 14, 0, 15 }; 343 344 WARN_ON_ONCE(pirq > 16); 345 return irqmap[read_config_nybble(router, 0x48, pirq-1)]; 346 } 347 348 static int pirq_ali_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 349 { 350 static const unsigned char irqmap[16] = { 0, 8, 0, 2, 4, 5, 7, 6, 0, 1, 3, 9, 11, 0, 13, 15 }; 351 unsigned int val = irqmap[irq]; 352 353 WARN_ON_ONCE(pirq > 16); 354 if (val) { 355 write_config_nybble(router, 0x48, pirq-1, val); 356 return 1; 357 } 358 return 0; 359 } 360 361 /* 362 * PIRQ routing for the 82374EB/82374SB EISA System Component (ESC) 363 * ASIC used with the Intel 82420 and 82430 PCIsets. The ESC is not 364 * decoded in the PCI configuration space, so we identify it by the 365 * accompanying 82375EB/82375SB PCI-EISA Bridge (PCEB) ASIC. 366 * 367 * There are four PIRQ Route Control registers, available in the 368 * port I/O space accessible indirectly via the index/data register 369 * pair at 0x22/0x23, located at indices 0x60/0x61/0x62/0x63 for the 370 * PIRQ0/1/2/3# lines respectively. The semantics is the same as 371 * with the PIIX router. 372 * 373 * Accesses to the port I/O space concerned here need to be unlocked 374 * by writing the value of 0x0f to the ESC ID Register at index 0x02 375 * beforehand. Any other value written to said register prevents 376 * further accesses from reaching the register file, except for the 377 * ESC ID Register being written with 0x0f again. 378 * 379 * References: 380 * 381 * "82374EB/82374SB EISA System Component (ESC)", Intel Corporation, 382 * Order Number: 290476-004, March 1996 383 * 384 * "82375EB/82375SB PCI-EISA Bridge (PCEB)", Intel Corporation, Order 385 * Number: 290477-004, March 1996 386 */ 387 388 #define PC_CONF_I82374_ESC_ID 0x02u 389 #define PC_CONF_I82374_PIRQ_ROUTE_CONTROL 0x60u 390 391 #define PC_CONF_I82374_ESC_ID_KEY 0x0fu 392 393 static int pirq_esc_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 394 { 395 unsigned long flags; 396 int reg; 397 u8 x; 398 399 reg = pirq; 400 if (reg >= 1 && reg <= 4) 401 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1; 402 403 raw_spin_lock_irqsave(&pc_conf_lock, flags); 404 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY); 405 x = pc_conf_get(reg); 406 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); 407 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 408 return (x < 16) ? x : 0; 409 } 410 411 static int pirq_esc_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 412 int irq) 413 { 414 unsigned long flags; 415 int reg; 416 417 reg = pirq; 418 if (reg >= 1 && reg <= 4) 419 reg += PC_CONF_I82374_PIRQ_ROUTE_CONTROL - 1; 420 421 raw_spin_lock_irqsave(&pc_conf_lock, flags); 422 pc_conf_set(PC_CONF_I82374_ESC_ID, PC_CONF_I82374_ESC_ID_KEY); 423 pc_conf_set(reg, irq); 424 pc_conf_set(PC_CONF_I82374_ESC_ID, 0); 425 raw_spin_unlock_irqrestore(&pc_conf_lock, flags); 426 return 1; 427 } 428 429 /* 430 * The Intel PIIX4 pirq rules are fairly simple: "pirq" is 431 * just a pointer to the config space. 432 */ 433 static int pirq_piix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 434 { 435 u8 x; 436 437 pci_read_config_byte(router, pirq, &x); 438 return (x < 16) ? x : 0; 439 } 440 441 static int pirq_piix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 442 { 443 pci_write_config_byte(router, pirq, irq); 444 return 1; 445 } 446 447 /* 448 * PIRQ routing for the 82426EX ISA Bridge (IB) ASIC used with the 449 * Intel 82420EX PCIset. 450 * 451 * There are only two PIRQ Route Control registers, available in the 452 * combined 82425EX/82426EX PCI configuration space, at 0x66 and 0x67 453 * for the PIRQ0# and PIRQ1# lines respectively. The semantics is 454 * the same as with the PIIX router. 455 * 456 * References: 457 * 458 * "82420EX PCIset Data Sheet, 82425EX PCI System Controller (PSC) 459 * and 82426EX ISA Bridge (IB)", Intel Corporation, Order Number: 460 * 290488-004, December 1995 461 */ 462 463 #define PCI_I82426EX_PIRQ_ROUTE_CONTROL 0x66u 464 465 static int pirq_ib_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 466 { 467 int reg; 468 u8 x; 469 470 reg = pirq; 471 if (reg >= 1 && reg <= 2) 472 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1; 473 474 pci_read_config_byte(router, reg, &x); 475 return (x < 16) ? x : 0; 476 } 477 478 static int pirq_ib_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 479 int irq) 480 { 481 int reg; 482 483 reg = pirq; 484 if (reg >= 1 && reg <= 2) 485 reg += PCI_I82426EX_PIRQ_ROUTE_CONTROL - 1; 486 487 pci_write_config_byte(router, reg, irq); 488 return 1; 489 } 490 491 /* 492 * The VIA pirq rules are nibble-based, like ALI, 493 * but without the ugly irq number munging. 494 * However, PIRQD is in the upper instead of lower 4 bits. 495 */ 496 static int pirq_via_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 497 { 498 return read_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq); 499 } 500 501 static int pirq_via_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 502 { 503 write_config_nybble(router, 0x55, pirq == 4 ? 5 : pirq, irq); 504 return 1; 505 } 506 507 /* 508 * The VIA pirq rules are nibble-based, like ALI, 509 * but without the ugly irq number munging. 510 * However, for 82C586, nibble map is different . 511 */ 512 static int pirq_via586_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 513 { 514 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 515 516 WARN_ON_ONCE(pirq > 5); 517 return read_config_nybble(router, 0x55, pirqmap[pirq-1]); 518 } 519 520 static int pirq_via586_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 521 { 522 static const unsigned int pirqmap[5] = { 3, 2, 5, 1, 1 }; 523 524 WARN_ON_ONCE(pirq > 5); 525 write_config_nybble(router, 0x55, pirqmap[pirq-1], irq); 526 return 1; 527 } 528 529 /* 530 * ITE 8330G pirq rules are nibble-based 531 * FIXME: pirqmap may be { 1, 0, 3, 2 }, 532 * 2+3 are both mapped to irq 9 on my system 533 */ 534 static int pirq_ite_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 535 { 536 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 537 538 WARN_ON_ONCE(pirq > 4); 539 return read_config_nybble(router, 0x43, pirqmap[pirq-1]); 540 } 541 542 static int pirq_ite_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 543 { 544 static const unsigned char pirqmap[4] = { 1, 0, 2, 3 }; 545 546 WARN_ON_ONCE(pirq > 4); 547 write_config_nybble(router, 0x43, pirqmap[pirq-1], irq); 548 return 1; 549 } 550 551 /* 552 * OPTI: high four bits are nibble pointer.. 553 * I wonder what the low bits do? 554 */ 555 static int pirq_opti_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 556 { 557 return read_config_nybble(router, 0xb8, pirq >> 4); 558 } 559 560 static int pirq_opti_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 561 { 562 write_config_nybble(router, 0xb8, pirq >> 4, irq); 563 return 1; 564 } 565 566 /* 567 * Cyrix: nibble offset 0x5C 568 * 0x5C bits 7:4 is INTB bits 3:0 is INTA 569 * 0x5D bits 7:4 is INTD bits 3:0 is INTC 570 */ 571 static int pirq_cyrix_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 572 { 573 return read_config_nybble(router, 0x5C, (pirq-1)^1); 574 } 575 576 static int pirq_cyrix_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 577 { 578 write_config_nybble(router, 0x5C, (pirq-1)^1, irq); 579 return 1; 580 } 581 582 /* 583 * PIRQ routing for SiS 85C503 router used in several SiS chipsets. 584 * We have to deal with the following issues here: 585 * - vendors have different ideas about the meaning of link values 586 * - some onboard devices (integrated in the chipset) have special 587 * links and are thus routed differently (i.e. not via PCI INTA-INTD) 588 * - different revision of the router have a different layout for 589 * the routing registers, particularly for the onchip devices 590 * 591 * For all routing registers the common thing is we have one byte 592 * per routeable link which is defined as: 593 * bit 7 IRQ mapping enabled (0) or disabled (1) 594 * bits [6:4] reserved (sometimes used for onchip devices) 595 * bits [3:0] IRQ to map to 596 * allowed: 3-7, 9-12, 14-15 597 * reserved: 0, 1, 2, 8, 13 598 * 599 * The config-space registers located at 0x41/0x42/0x43/0x44 are 600 * always used to route the normal PCI INT A/B/C/D respectively. 601 * Apparently there are systems implementing PCI routing table using 602 * link values 0x01-0x04 and others using 0x41-0x44 for PCI INTA..D. 603 * We try our best to handle both link mappings. 604 * 605 * Currently (2003-05-21) it appears most SiS chipsets follow the 606 * definition of routing registers from the SiS-5595 southbridge. 607 * According to the SiS 5595 datasheets the revision id's of the 608 * router (ISA-bridge) should be 0x01 or 0xb0. 609 * 610 * Furthermore we've also seen lspci dumps with revision 0x00 and 0xb1. 611 * Looks like these are used in a number of SiS 5xx/6xx/7xx chipsets. 612 * They seem to work with the current routing code. However there is 613 * some concern because of the two USB-OHCI HCs (original SiS 5595 614 * had only one). YMMV. 615 * 616 * Onchip routing for router rev-id 0x01/0xb0 and probably 0x00/0xb1: 617 * 618 * 0x61: IDEIRQ: 619 * bits [6:5] must be written 01 620 * bit 4 channel-select primary (0), secondary (1) 621 * 622 * 0x62: USBIRQ: 623 * bit 6 OHCI function disabled (0), enabled (1) 624 * 625 * 0x6a: ACPI/SCI IRQ: bits 4-6 reserved 626 * 627 * 0x7e: Data Acq. Module IRQ - bits 4-6 reserved 628 * 629 * We support USBIRQ (in addition to INTA-INTD) and keep the 630 * IDE, ACPI and DAQ routing untouched as set by the BIOS. 631 * 632 * Currently the only reported exception is the new SiS 65x chipset 633 * which includes the SiS 69x southbridge. Here we have the 85C503 634 * router revision 0x04 and there are changes in the register layout 635 * mostly related to the different USB HCs with USB 2.0 support. 636 * 637 * Onchip routing for router rev-id 0x04 (try-and-error observation) 638 * 639 * 0x60/0x61/0x62/0x63: 1xEHCI and 3xOHCI (companion) USB-HCs 640 * bit 6-4 are probably unused, not like 5595 641 */ 642 643 #define PIRQ_SIS_IRQ_MASK 0x0f 644 #define PIRQ_SIS_IRQ_DISABLE 0x80 645 #define PIRQ_SIS_USB_ENABLE 0x40 646 647 static int pirq_sis_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 648 { 649 u8 x; 650 int reg; 651 652 reg = pirq; 653 if (reg >= 0x01 && reg <= 0x04) 654 reg += 0x40; 655 pci_read_config_byte(router, reg, &x); 656 return (x & PIRQ_SIS_IRQ_DISABLE) ? 0 : (x & PIRQ_SIS_IRQ_MASK); 657 } 658 659 static int pirq_sis_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 660 { 661 u8 x; 662 int reg; 663 664 reg = pirq; 665 if (reg >= 0x01 && reg <= 0x04) 666 reg += 0x40; 667 pci_read_config_byte(router, reg, &x); 668 x &= ~(PIRQ_SIS_IRQ_MASK | PIRQ_SIS_IRQ_DISABLE); 669 x |= irq ? irq: PIRQ_SIS_IRQ_DISABLE; 670 pci_write_config_byte(router, reg, x); 671 return 1; 672 } 673 674 675 /* 676 * VLSI: nibble offset 0x74 - educated guess due to routing table and 677 * config space of VLSI 82C534 PCI-bridge/router (1004:0102) 678 * Tested on HP OmniBook 800 covering PIRQ 1, 2, 4, 8 for onboard 679 * devices, PIRQ 3 for non-pci(!) soundchip and (untested) PIRQ 6 680 * for the busbridge to the docking station. 681 */ 682 683 static int pirq_vlsi_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 684 { 685 WARN_ON_ONCE(pirq >= 9); 686 if (pirq > 8) { 687 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 688 return 0; 689 } 690 return read_config_nybble(router, 0x74, pirq-1); 691 } 692 693 static int pirq_vlsi_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 694 { 695 WARN_ON_ONCE(pirq >= 9); 696 if (pirq > 8) { 697 dev_info(&dev->dev, "VLSI router PIRQ escape (%d)\n", pirq); 698 return 0; 699 } 700 write_config_nybble(router, 0x74, pirq-1, irq); 701 return 1; 702 } 703 704 /* 705 * ServerWorks: PCI interrupts mapped to system IRQ lines through Index 706 * and Redirect I/O registers (0x0c00 and 0x0c01). The Index register 707 * format is (PCIIRQ## | 0x10), e.g.: PCIIRQ10=0x1a. The Redirect 708 * register is a straight binary coding of desired PIC IRQ (low nibble). 709 * 710 * The 'link' value in the PIRQ table is already in the correct format 711 * for the Index register. There are some special index values: 712 * 0x00 for ACPI (SCI), 0x01 for USB, 0x02 for IDE0, 0x04 for IDE1, 713 * and 0x03 for SMBus. 714 */ 715 static int pirq_serverworks_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 716 { 717 outb(pirq, 0xc00); 718 return inb(0xc01) & 0xf; 719 } 720 721 static int pirq_serverworks_set(struct pci_dev *router, struct pci_dev *dev, 722 int pirq, int irq) 723 { 724 outb(pirq, 0xc00); 725 outb(irq, 0xc01); 726 return 1; 727 } 728 729 /* Support for AMD756 PCI IRQ Routing 730 * Jhon H. Caicedo <jhcaiced@osso.org.co> 731 * Jun/21/2001 0.2.0 Release, fixed to use "nybble" functions... (jhcaiced) 732 * Jun/19/2001 Alpha Release 0.1.0 (jhcaiced) 733 * The AMD756 pirq rules are nibble-based 734 * offset 0x56 0-3 PIRQA 4-7 PIRQB 735 * offset 0x57 0-3 PIRQC 4-7 PIRQD 736 */ 737 static int pirq_amd756_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 738 { 739 u8 irq; 740 irq = 0; 741 if (pirq <= 4) 742 irq = read_config_nybble(router, 0x56, pirq - 1); 743 dev_info(&dev->dev, 744 "AMD756: dev [%04x:%04x], router PIRQ %d get IRQ %d\n", 745 dev->vendor, dev->device, pirq, irq); 746 return irq; 747 } 748 749 static int pirq_amd756_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 750 { 751 dev_info(&dev->dev, 752 "AMD756: dev [%04x:%04x], router PIRQ %d set IRQ %d\n", 753 dev->vendor, dev->device, pirq, irq); 754 if (pirq <= 4) 755 write_config_nybble(router, 0x56, pirq - 1, irq); 756 return 1; 757 } 758 759 /* 760 * PicoPower PT86C523 761 */ 762 static int pirq_pico_get(struct pci_dev *router, struct pci_dev *dev, int pirq) 763 { 764 outb(0x10 + ((pirq - 1) >> 1), 0x24); 765 return ((pirq - 1) & 1) ? (inb(0x26) >> 4) : (inb(0x26) & 0xf); 766 } 767 768 static int pirq_pico_set(struct pci_dev *router, struct pci_dev *dev, int pirq, 769 int irq) 770 { 771 unsigned int x; 772 outb(0x10 + ((pirq - 1) >> 1), 0x24); 773 x = inb(0x26); 774 x = ((pirq - 1) & 1) ? ((x & 0x0f) | (irq << 4)) : ((x & 0xf0) | (irq)); 775 outb(x, 0x26); 776 return 1; 777 } 778 779 #ifdef CONFIG_PCI_BIOS 780 781 static int pirq_bios_set(struct pci_dev *router, struct pci_dev *dev, int pirq, int irq) 782 { 783 struct pci_dev *bridge; 784 int pin = pci_get_interrupt_pin(dev, &bridge); 785 return pcibios_set_irq_routing(bridge, pin - 1, irq); 786 } 787 788 #endif 789 790 static __init int intel_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 791 { 792 static struct pci_device_id __initdata pirq_440gx[] = { 793 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_0) }, 794 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443GX_2) }, 795 { }, 796 }; 797 798 /* 440GX has a proprietary PIRQ router -- don't use it */ 799 if (pci_dev_present(pirq_440gx)) 800 return 0; 801 802 switch (device) { 803 case PCI_DEVICE_ID_INTEL_82375: 804 r->name = "PCEB/ESC"; 805 r->get = pirq_esc_get; 806 r->set = pirq_esc_set; 807 return 1; 808 case PCI_DEVICE_ID_INTEL_82371FB_0: 809 case PCI_DEVICE_ID_INTEL_82371SB_0: 810 case PCI_DEVICE_ID_INTEL_82371AB_0: 811 case PCI_DEVICE_ID_INTEL_82371MX: 812 case PCI_DEVICE_ID_INTEL_82443MX_0: 813 case PCI_DEVICE_ID_INTEL_82801AA_0: 814 case PCI_DEVICE_ID_INTEL_82801AB_0: 815 case PCI_DEVICE_ID_INTEL_82801BA_0: 816 case PCI_DEVICE_ID_INTEL_82801BA_10: 817 case PCI_DEVICE_ID_INTEL_82801CA_0: 818 case PCI_DEVICE_ID_INTEL_82801CA_12: 819 case PCI_DEVICE_ID_INTEL_82801DB_0: 820 case PCI_DEVICE_ID_INTEL_82801E_0: 821 case PCI_DEVICE_ID_INTEL_82801EB_0: 822 case PCI_DEVICE_ID_INTEL_ESB_1: 823 case PCI_DEVICE_ID_INTEL_ICH6_0: 824 case PCI_DEVICE_ID_INTEL_ICH6_1: 825 case PCI_DEVICE_ID_INTEL_ICH7_0: 826 case PCI_DEVICE_ID_INTEL_ICH7_1: 827 case PCI_DEVICE_ID_INTEL_ICH7_30: 828 case PCI_DEVICE_ID_INTEL_ICH7_31: 829 case PCI_DEVICE_ID_INTEL_TGP_LPC: 830 case PCI_DEVICE_ID_INTEL_ESB2_0: 831 case PCI_DEVICE_ID_INTEL_ICH8_0: 832 case PCI_DEVICE_ID_INTEL_ICH8_1: 833 case PCI_DEVICE_ID_INTEL_ICH8_2: 834 case PCI_DEVICE_ID_INTEL_ICH8_3: 835 case PCI_DEVICE_ID_INTEL_ICH8_4: 836 case PCI_DEVICE_ID_INTEL_ICH9_0: 837 case PCI_DEVICE_ID_INTEL_ICH9_1: 838 case PCI_DEVICE_ID_INTEL_ICH9_2: 839 case PCI_DEVICE_ID_INTEL_ICH9_3: 840 case PCI_DEVICE_ID_INTEL_ICH9_4: 841 case PCI_DEVICE_ID_INTEL_ICH9_5: 842 case PCI_DEVICE_ID_INTEL_EP80579_0: 843 case PCI_DEVICE_ID_INTEL_ICH10_0: 844 case PCI_DEVICE_ID_INTEL_ICH10_1: 845 case PCI_DEVICE_ID_INTEL_ICH10_2: 846 case PCI_DEVICE_ID_INTEL_ICH10_3: 847 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0: 848 case PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1: 849 r->name = "PIIX/ICH"; 850 r->get = pirq_piix_get; 851 r->set = pirq_piix_set; 852 return 1; 853 case PCI_DEVICE_ID_INTEL_82425: 854 r->name = "PSC/IB"; 855 r->get = pirq_ib_get; 856 r->set = pirq_ib_set; 857 return 1; 858 } 859 860 if ((device >= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN && 861 device <= PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX) 862 || (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN && 863 device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) 864 || (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN && 865 device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX) 866 || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && 867 device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) { 868 r->name = "PIIX/ICH"; 869 r->get = pirq_piix_get; 870 r->set = pirq_piix_set; 871 return 1; 872 } 873 874 return 0; 875 } 876 877 static __init int via_router_probe(struct irq_router *r, 878 struct pci_dev *router, u16 device) 879 { 880 /* FIXME: We should move some of the quirk fixup stuff here */ 881 882 /* 883 * workarounds for some buggy BIOSes 884 */ 885 if (device == PCI_DEVICE_ID_VIA_82C586_0) { 886 switch (router->device) { 887 case PCI_DEVICE_ID_VIA_82C686: 888 /* 889 * Asus k7m bios wrongly reports 82C686A 890 * as 586-compatible 891 */ 892 device = PCI_DEVICE_ID_VIA_82C686; 893 break; 894 case PCI_DEVICE_ID_VIA_8235: 895 /** 896 * Asus a7v-x bios wrongly reports 8235 897 * as 586-compatible 898 */ 899 device = PCI_DEVICE_ID_VIA_8235; 900 break; 901 case PCI_DEVICE_ID_VIA_8237: 902 /** 903 * Asus a7v600 bios wrongly reports 8237 904 * as 586-compatible 905 */ 906 device = PCI_DEVICE_ID_VIA_8237; 907 break; 908 } 909 } 910 911 switch (device) { 912 case PCI_DEVICE_ID_VIA_82C586_0: 913 r->name = "VIA"; 914 r->get = pirq_via586_get; 915 r->set = pirq_via586_set; 916 return 1; 917 case PCI_DEVICE_ID_VIA_82C596: 918 case PCI_DEVICE_ID_VIA_82C686: 919 case PCI_DEVICE_ID_VIA_8231: 920 case PCI_DEVICE_ID_VIA_8233A: 921 case PCI_DEVICE_ID_VIA_8235: 922 case PCI_DEVICE_ID_VIA_8237: 923 /* FIXME: add new ones for 8233/5 */ 924 r->name = "VIA"; 925 r->get = pirq_via_get; 926 r->set = pirq_via_set; 927 return 1; 928 } 929 return 0; 930 } 931 932 static __init int vlsi_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 933 { 934 switch (device) { 935 case PCI_DEVICE_ID_VLSI_82C534: 936 r->name = "VLSI 82C534"; 937 r->get = pirq_vlsi_get; 938 r->set = pirq_vlsi_set; 939 return 1; 940 } 941 return 0; 942 } 943 944 945 static __init int serverworks_router_probe(struct irq_router *r, 946 struct pci_dev *router, u16 device) 947 { 948 switch (device) { 949 case PCI_DEVICE_ID_SERVERWORKS_OSB4: 950 case PCI_DEVICE_ID_SERVERWORKS_CSB5: 951 r->name = "ServerWorks"; 952 r->get = pirq_serverworks_get; 953 r->set = pirq_serverworks_set; 954 return 1; 955 } 956 return 0; 957 } 958 959 static __init int sis_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 960 { 961 if (device != PCI_DEVICE_ID_SI_503) 962 return 0; 963 964 r->name = "SIS"; 965 r->get = pirq_sis_get; 966 r->set = pirq_sis_set; 967 return 1; 968 } 969 970 static __init int cyrix_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 971 { 972 switch (device) { 973 case PCI_DEVICE_ID_CYRIX_5520: 974 r->name = "NatSemi"; 975 r->get = pirq_cyrix_get; 976 r->set = pirq_cyrix_set; 977 return 1; 978 } 979 return 0; 980 } 981 982 static __init int opti_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 983 { 984 switch (device) { 985 case PCI_DEVICE_ID_OPTI_82C700: 986 r->name = "OPTI"; 987 r->get = pirq_opti_get; 988 r->set = pirq_opti_set; 989 return 1; 990 } 991 return 0; 992 } 993 994 static __init int ite_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 995 { 996 switch (device) { 997 case PCI_DEVICE_ID_ITE_IT8330G_0: 998 r->name = "ITE"; 999 r->get = pirq_ite_get; 1000 r->set = pirq_ite_set; 1001 return 1; 1002 } 1003 return 0; 1004 } 1005 1006 static __init int ali_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1007 { 1008 switch (device) { 1009 case PCI_DEVICE_ID_AL_M1489: 1010 r->name = "FinALi"; 1011 r->get = pirq_finali_get; 1012 r->set = pirq_finali_set; 1013 r->lvl = pirq_finali_lvl; 1014 return 1; 1015 case PCI_DEVICE_ID_AL_M1533: 1016 case PCI_DEVICE_ID_AL_M1563: 1017 r->name = "ALI"; 1018 r->get = pirq_ali_get; 1019 r->set = pirq_ali_set; 1020 return 1; 1021 } 1022 return 0; 1023 } 1024 1025 static __init int amd_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1026 { 1027 switch (device) { 1028 case PCI_DEVICE_ID_AMD_VIPER_740B: 1029 r->name = "AMD756"; 1030 break; 1031 case PCI_DEVICE_ID_AMD_VIPER_7413: 1032 r->name = "AMD766"; 1033 break; 1034 case PCI_DEVICE_ID_AMD_VIPER_7443: 1035 r->name = "AMD768"; 1036 break; 1037 default: 1038 return 0; 1039 } 1040 r->get = pirq_amd756_get; 1041 r->set = pirq_amd756_set; 1042 return 1; 1043 } 1044 1045 static __init int pico_router_probe(struct irq_router *r, struct pci_dev *router, u16 device) 1046 { 1047 switch (device) { 1048 case PCI_DEVICE_ID_PICOPOWER_PT86C523: 1049 r->name = "PicoPower PT86C523"; 1050 r->get = pirq_pico_get; 1051 r->set = pirq_pico_set; 1052 return 1; 1053 1054 case PCI_DEVICE_ID_PICOPOWER_PT86C523BBP: 1055 r->name = "PicoPower PT86C523 rev. BB+"; 1056 r->get = pirq_pico_get; 1057 r->set = pirq_pico_set; 1058 return 1; 1059 } 1060 return 0; 1061 } 1062 1063 static __initdata struct irq_router_handler pirq_routers[] = { 1064 { PCI_VENDOR_ID_INTEL, intel_router_probe }, 1065 { PCI_VENDOR_ID_AL, ali_router_probe }, 1066 { PCI_VENDOR_ID_ITE, ite_router_probe }, 1067 { PCI_VENDOR_ID_VIA, via_router_probe }, 1068 { PCI_VENDOR_ID_OPTI, opti_router_probe }, 1069 { PCI_VENDOR_ID_SI, sis_router_probe }, 1070 { PCI_VENDOR_ID_CYRIX, cyrix_router_probe }, 1071 { PCI_VENDOR_ID_VLSI, vlsi_router_probe }, 1072 { PCI_VENDOR_ID_SERVERWORKS, serverworks_router_probe }, 1073 { PCI_VENDOR_ID_AMD, amd_router_probe }, 1074 { PCI_VENDOR_ID_PICOPOWER, pico_router_probe }, 1075 /* Someone with docs needs to add the ATI Radeon IGP */ 1076 { 0, NULL } 1077 }; 1078 static struct irq_router pirq_router; 1079 static struct pci_dev *pirq_router_dev; 1080 1081 1082 /* 1083 * FIXME: should we have an option to say "generic for 1084 * chipset" ? 1085 */ 1086 1087 static void __init pirq_find_router(struct irq_router *r) 1088 { 1089 struct irq_routing_table *rt = pirq_table; 1090 struct irq_router_handler *h; 1091 1092 #ifdef CONFIG_PCI_BIOS 1093 if (!rt->signature) { 1094 printk(KERN_INFO "PCI: Using BIOS for IRQ routing\n"); 1095 r->set = pirq_bios_set; 1096 r->name = "BIOS"; 1097 return; 1098 } 1099 #endif 1100 1101 /* Default unless a driver reloads it */ 1102 r->name = "default"; 1103 r->get = NULL; 1104 r->set = NULL; 1105 1106 DBG(KERN_DEBUG "PCI: Attempting to find IRQ router for [%04x:%04x]\n", 1107 rt->rtr_vendor, rt->rtr_device); 1108 1109 pirq_router_dev = pci_get_domain_bus_and_slot(0, rt->rtr_bus, 1110 rt->rtr_devfn); 1111 if (!pirq_router_dev) { 1112 DBG(KERN_DEBUG "PCI: Interrupt router not found at " 1113 "%02x:%02x\n", rt->rtr_bus, rt->rtr_devfn); 1114 return; 1115 } 1116 1117 for (h = pirq_routers; h->vendor; h++) { 1118 /* First look for a router match */ 1119 if (rt->rtr_vendor == h->vendor && 1120 h->probe(r, pirq_router_dev, rt->rtr_device)) 1121 break; 1122 /* Fall back to a device match */ 1123 if (pirq_router_dev->vendor == h->vendor && 1124 h->probe(r, pirq_router_dev, pirq_router_dev->device)) 1125 break; 1126 } 1127 dev_info(&pirq_router_dev->dev, "%s IRQ router [%04x:%04x]\n", 1128 pirq_router.name, 1129 pirq_router_dev->vendor, pirq_router_dev->device); 1130 1131 /* The device remains referenced for the kernel lifetime */ 1132 } 1133 1134 static struct irq_info *pirq_get_info(struct pci_dev *dev) 1135 { 1136 struct irq_routing_table *rt = pirq_table; 1137 int entries = (rt->size - sizeof(struct irq_routing_table)) / 1138 sizeof(struct irq_info); 1139 struct irq_info *info; 1140 1141 for (info = rt->slots; entries--; info++) 1142 if (info->bus == dev->bus->number && 1143 PCI_SLOT(info->devfn) == PCI_SLOT(dev->devfn)) 1144 return info; 1145 return NULL; 1146 } 1147 1148 static int pcibios_lookup_irq(struct pci_dev *dev, int assign) 1149 { 1150 u8 pin; 1151 struct irq_info *info; 1152 int i, pirq, newirq; 1153 int irq = 0; 1154 u32 mask; 1155 struct irq_router *r = &pirq_router; 1156 struct pci_dev *dev2 = NULL; 1157 char *msg = NULL; 1158 1159 /* Find IRQ pin */ 1160 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1161 if (!pin) { 1162 dev_dbg(&dev->dev, "no interrupt pin\n"); 1163 return 0; 1164 } 1165 1166 if (io_apic_assign_pci_irqs) 1167 return 0; 1168 1169 /* Find IRQ routing entry */ 1170 1171 if (!pirq_table) 1172 return 0; 1173 1174 info = pirq_get_info(dev); 1175 if (!info) { 1176 dev_dbg(&dev->dev, "PCI INT %c not found in routing table\n", 1177 'A' + pin - 1); 1178 return 0; 1179 } 1180 pirq = info->irq[pin - 1].link; 1181 mask = info->irq[pin - 1].bitmap; 1182 if (!pirq) { 1183 dev_dbg(&dev->dev, "PCI INT %c not routed\n", 'A' + pin - 1); 1184 return 0; 1185 } 1186 dev_dbg(&dev->dev, "PCI INT %c -> PIRQ %02x, mask %04x, excl %04x", 1187 'A' + pin - 1, pirq, mask, pirq_table->exclusive_irqs); 1188 mask &= pcibios_irq_mask; 1189 1190 /* Work around broken HP Pavilion Notebooks which assign USB to 1191 IRQ 9 even though it is actually wired to IRQ 11 */ 1192 1193 if (broken_hp_bios_irq9 && pirq == 0x59 && dev->irq == 9) { 1194 dev->irq = 11; 1195 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11); 1196 r->set(pirq_router_dev, dev, pirq, 11); 1197 } 1198 1199 /* same for Acer Travelmate 360, but with CB and irq 11 -> 10 */ 1200 if (acer_tm360_irqrouting && dev->irq == 11 && 1201 dev->vendor == PCI_VENDOR_ID_O2) { 1202 pirq = 0x68; 1203 mask = 0x400; 1204 dev->irq = r->get(pirq_router_dev, dev, pirq); 1205 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); 1206 } 1207 1208 /* 1209 * Find the best IRQ to assign: use the one 1210 * reported by the device if possible. 1211 */ 1212 newirq = dev->irq; 1213 if (newirq && !((1 << newirq) & mask)) { 1214 if (pci_probe & PCI_USE_PIRQ_MASK) 1215 newirq = 0; 1216 else 1217 dev_warn(&dev->dev, "IRQ %d doesn't match PIRQ mask " 1218 "%#x; try pci=usepirqmask\n", newirq, mask); 1219 } 1220 if (!newirq && assign) { 1221 for (i = 0; i < 16; i++) { 1222 if (!(mask & (1 << i))) 1223 continue; 1224 if (pirq_penalty[i] < pirq_penalty[newirq] && 1225 can_request_irq(i, IRQF_SHARED)) 1226 newirq = i; 1227 } 1228 } 1229 dev_dbg(&dev->dev, "PCI INT %c -> newirq %d", 'A' + pin - 1, newirq); 1230 1231 /* Check if it is hardcoded */ 1232 if ((pirq & 0xf0) == 0xf0) { 1233 irq = pirq & 0xf; 1234 msg = "hardcoded"; 1235 } else if (r->get && (irq = r->get(pirq_router_dev, dev, pirq)) && \ 1236 ((!(pci_probe & PCI_USE_PIRQ_MASK)) || ((1 << irq) & mask))) { 1237 msg = "found"; 1238 if (r->lvl) 1239 r->lvl(pirq_router_dev, dev, pirq, irq); 1240 else 1241 elcr_set_level_irq(irq); 1242 } else if (newirq && r->set && 1243 (dev->class >> 8) != PCI_CLASS_DISPLAY_VGA) { 1244 if (r->set(pirq_router_dev, dev, pirq, newirq)) { 1245 if (r->lvl) 1246 r->lvl(pirq_router_dev, dev, pirq, newirq); 1247 else 1248 elcr_set_level_irq(newirq); 1249 msg = "assigned"; 1250 irq = newirq; 1251 } 1252 } 1253 1254 if (!irq) { 1255 if (newirq && mask == (1 << newirq)) { 1256 msg = "guessed"; 1257 irq = newirq; 1258 } else { 1259 dev_dbg(&dev->dev, "can't route interrupt\n"); 1260 return 0; 1261 } 1262 } 1263 dev_info(&dev->dev, "%s PCI INT %c -> IRQ %d\n", msg, 'A' + pin - 1, irq); 1264 1265 /* Update IRQ for all devices with the same pirq value */ 1266 for_each_pci_dev(dev2) { 1267 pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin); 1268 if (!pin) 1269 continue; 1270 1271 info = pirq_get_info(dev2); 1272 if (!info) 1273 continue; 1274 if (info->irq[pin - 1].link == pirq) { 1275 /* 1276 * We refuse to override the dev->irq 1277 * information. Give a warning! 1278 */ 1279 if (dev2->irq && dev2->irq != irq && \ 1280 (!(pci_probe & PCI_USE_PIRQ_MASK) || \ 1281 ((1 << dev2->irq) & mask))) { 1282 #ifndef CONFIG_PCI_MSI 1283 dev_info(&dev2->dev, "IRQ routing conflict: " 1284 "have IRQ %d, want IRQ %d\n", 1285 dev2->irq, irq); 1286 #endif 1287 continue; 1288 } 1289 dev2->irq = irq; 1290 pirq_penalty[irq]++; 1291 if (dev != dev2) 1292 dev_info(&dev->dev, "sharing IRQ %d with %s\n", 1293 irq, pci_name(dev2)); 1294 } 1295 } 1296 return 1; 1297 } 1298 1299 void __init pcibios_fixup_irqs(void) 1300 { 1301 struct pci_dev *dev = NULL; 1302 u8 pin; 1303 1304 DBG(KERN_DEBUG "PCI: IRQ fixup\n"); 1305 for_each_pci_dev(dev) { 1306 /* 1307 * If the BIOS has set an out of range IRQ number, just 1308 * ignore it. Also keep track of which IRQ's are 1309 * already in use. 1310 */ 1311 if (dev->irq >= 16) { 1312 dev_dbg(&dev->dev, "ignoring bogus IRQ %d\n", dev->irq); 1313 dev->irq = 0; 1314 } 1315 /* 1316 * If the IRQ is already assigned to a PCI device, 1317 * ignore its ISA use penalty 1318 */ 1319 if (pirq_penalty[dev->irq] >= 100 && 1320 pirq_penalty[dev->irq] < 100000) 1321 pirq_penalty[dev->irq] = 0; 1322 pirq_penalty[dev->irq]++; 1323 } 1324 1325 if (io_apic_assign_pci_irqs) 1326 return; 1327 1328 dev = NULL; 1329 for_each_pci_dev(dev) { 1330 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1331 if (!pin) 1332 continue; 1333 1334 /* 1335 * Still no IRQ? Try to lookup one... 1336 */ 1337 if (!dev->irq) 1338 pcibios_lookup_irq(dev, 0); 1339 } 1340 } 1341 1342 /* 1343 * Work around broken HP Pavilion Notebooks which assign USB to 1344 * IRQ 9 even though it is actually wired to IRQ 11 1345 */ 1346 static int __init fix_broken_hp_bios_irq9(const struct dmi_system_id *d) 1347 { 1348 if (!broken_hp_bios_irq9) { 1349 broken_hp_bios_irq9 = 1; 1350 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1351 d->ident); 1352 } 1353 return 0; 1354 } 1355 1356 /* 1357 * Work around broken Acer TravelMate 360 Notebooks which assign 1358 * Cardbus to IRQ 11 even though it is actually wired to IRQ 10 1359 */ 1360 static int __init fix_acer_tm360_irqrouting(const struct dmi_system_id *d) 1361 { 1362 if (!acer_tm360_irqrouting) { 1363 acer_tm360_irqrouting = 1; 1364 printk(KERN_INFO "%s detected - fixing broken IRQ routing\n", 1365 d->ident); 1366 } 1367 return 0; 1368 } 1369 1370 static const struct dmi_system_id pciirq_dmi_table[] __initconst = { 1371 { 1372 .callback = fix_broken_hp_bios_irq9, 1373 .ident = "HP Pavilion N5400 Series Laptop", 1374 .matches = { 1375 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"), 1376 DMI_MATCH(DMI_BIOS_VERSION, "GE.M1.03"), 1377 DMI_MATCH(DMI_PRODUCT_VERSION, 1378 "HP Pavilion Notebook Model GE"), 1379 DMI_MATCH(DMI_BOARD_VERSION, "OmniBook N32N-736"), 1380 }, 1381 }, 1382 { 1383 .callback = fix_acer_tm360_irqrouting, 1384 .ident = "Acer TravelMate 36x Laptop", 1385 .matches = { 1386 DMI_MATCH(DMI_SYS_VENDOR, "Acer"), 1387 DMI_MATCH(DMI_PRODUCT_NAME, "TravelMate 360"), 1388 }, 1389 }, 1390 { } 1391 }; 1392 1393 void __init pcibios_irq_init(void) 1394 { 1395 struct irq_routing_table *rtable = NULL; 1396 1397 DBG(KERN_DEBUG "PCI: IRQ init\n"); 1398 1399 if (raw_pci_ops == NULL) 1400 return; 1401 1402 dmi_check_system(pciirq_dmi_table); 1403 1404 pirq_table = pirq_find_routing_table(); 1405 1406 #ifdef CONFIG_PCI_BIOS 1407 if (!pirq_table && (pci_probe & PCI_BIOS_IRQ_SCAN)) { 1408 pirq_table = pcibios_get_irq_routing_table(); 1409 rtable = pirq_table; 1410 } 1411 #endif 1412 if (pirq_table) { 1413 pirq_peer_trick(); 1414 pirq_find_router(&pirq_router); 1415 if (pirq_table->exclusive_irqs) { 1416 int i; 1417 for (i = 0; i < 16; i++) 1418 if (!(pirq_table->exclusive_irqs & (1 << i))) 1419 pirq_penalty[i] += 100; 1420 } 1421 /* 1422 * If we're using the I/O APIC, avoid using the PCI IRQ 1423 * routing table 1424 */ 1425 if (io_apic_assign_pci_irqs) { 1426 kfree(rtable); 1427 pirq_table = NULL; 1428 } 1429 } 1430 1431 x86_init.pci.fixup_irqs(); 1432 1433 if (io_apic_assign_pci_irqs && pci_routeirq) { 1434 struct pci_dev *dev = NULL; 1435 /* 1436 * PCI IRQ routing is set up by pci_enable_device(), but we 1437 * also do it here in case there are still broken drivers that 1438 * don't use pci_enable_device(). 1439 */ 1440 printk(KERN_INFO "PCI: Routing PCI interrupts for all devices because \"pci=routeirq\" specified\n"); 1441 for_each_pci_dev(dev) 1442 pirq_enable_irq(dev); 1443 } 1444 } 1445 1446 static void pirq_penalize_isa_irq(int irq, int active) 1447 { 1448 /* 1449 * If any ISAPnP device reports an IRQ in its list of possible 1450 * IRQ's, we try to avoid assigning it to PCI devices. 1451 */ 1452 if (irq < 16) { 1453 if (active) 1454 pirq_penalty[irq] += 1000; 1455 else 1456 pirq_penalty[irq] += 100; 1457 } 1458 } 1459 1460 void pcibios_penalize_isa_irq(int irq, int active) 1461 { 1462 #ifdef CONFIG_ACPI 1463 if (!acpi_noirq) 1464 acpi_penalize_isa_irq(irq, active); 1465 else 1466 #endif 1467 pirq_penalize_isa_irq(irq, active); 1468 } 1469 1470 static int pirq_enable_irq(struct pci_dev *dev) 1471 { 1472 u8 pin = 0; 1473 1474 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1475 if (pin && !pcibios_lookup_irq(dev, 1)) { 1476 char *msg = ""; 1477 1478 if (!io_apic_assign_pci_irqs && dev->irq) 1479 return 0; 1480 1481 if (io_apic_assign_pci_irqs) { 1482 #ifdef CONFIG_X86_IO_APIC 1483 struct pci_dev *temp_dev; 1484 int irq; 1485 1486 if (dev->irq_managed && dev->irq > 0) 1487 return 0; 1488 1489 irq = IO_APIC_get_PCI_irq_vector(dev->bus->number, 1490 PCI_SLOT(dev->devfn), pin - 1); 1491 /* 1492 * Busses behind bridges are typically not listed in the MP-table. 1493 * In this case we have to look up the IRQ based on the parent bus, 1494 * parent slot, and pin number. The SMP code detects such bridged 1495 * busses itself so we should get into this branch reliably. 1496 */ 1497 temp_dev = dev; 1498 while (irq < 0 && dev->bus->parent) { /* go back to the bridge */ 1499 struct pci_dev *bridge = dev->bus->self; 1500 1501 pin = pci_swizzle_interrupt_pin(dev, pin); 1502 irq = IO_APIC_get_PCI_irq_vector(bridge->bus->number, 1503 PCI_SLOT(bridge->devfn), 1504 pin - 1); 1505 if (irq >= 0) 1506 dev_warn(&dev->dev, "using bridge %s " 1507 "INT %c to get IRQ %d\n", 1508 pci_name(bridge), 'A' + pin - 1, 1509 irq); 1510 dev = bridge; 1511 } 1512 dev = temp_dev; 1513 if (irq >= 0) { 1514 dev->irq_managed = 1; 1515 dev->irq = irq; 1516 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1517 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1518 return 0; 1519 } else 1520 msg = "; probably buggy MP table"; 1521 #endif 1522 } else if (pci_probe & PCI_BIOS_IRQ_SCAN) 1523 msg = ""; 1524 else 1525 msg = "; please try using pci=biosirq"; 1526 1527 /* 1528 * With IDE legacy devices the IRQ lookup failure is not 1529 * a problem.. 1530 */ 1531 if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE && 1532 !(dev->class & 0x5)) 1533 return 0; 1534 1535 dev_warn(&dev->dev, "can't find IRQ for PCI INT %c%s\n", 1536 'A' + pin - 1, msg); 1537 } 1538 return 0; 1539 } 1540 1541 bool mp_should_keep_irq(struct device *dev) 1542 { 1543 if (dev->power.is_prepared) 1544 return true; 1545 #ifdef CONFIG_PM 1546 if (dev->power.runtime_status == RPM_SUSPENDING) 1547 return true; 1548 #endif 1549 1550 return false; 1551 } 1552 1553 static void pirq_disable_irq(struct pci_dev *dev) 1554 { 1555 if (io_apic_assign_pci_irqs && !mp_should_keep_irq(&dev->dev) && 1556 dev->irq_managed && dev->irq) { 1557 mp_unmap_irq(dev->irq); 1558 dev->irq = 0; 1559 dev->irq_managed = 0; 1560 } 1561 } 1562